nrfx: Update to version 2.10.0
Update nrfx to the recently released version. See https://github.com/NordicSemiconductor/nrfx/blob/v2.10.0/CHANGELOG.md for a list of changes that this version introduces. Origin: nrfx License: BSD 3-Clause URL: https://github.com/NordicSemiconductor/nrfx/tree/v2.10.0 commit: 23fb4437c08a9edfdf6d34f002322f693a15e8fe Purpose: Provide peripheral drivers for Nordic SoCs Maintained-by: External Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
This commit is contained in:
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@ -1,6 +1,28 @@
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# Changelog
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All notable changes to this project are documented in this file.
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## [2.10.0] - 2022-10-25
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### Added
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- Added NRFX_CONFIG_API_VER_2_9 and NRFX_CONFIG_API_VER_2_10 symbols that guard API-breaking changes. Deprecated API is used by default.
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- Added new signature for the event handler in the IPC driver that accepts event index instead of event bitmask. The previous signature is deprecated.
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- Added nrfx_ipc_gpmem_get() function that is used to get data from the GPMEM register in IPC. It should be now used instead of nrfx_ipc_mem_get(), which is deprecated.
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- Added samples for the following drivers: EGU, PWM, RNG, SAADC, SPIM, SPIS, TEMP, TIMER, TWIM, TWIS, UARTE. They are a part of `zephyrproject-rtos/hal_nordic/nrfx` repository.
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- Introduced the NRFX_{PERIPH}_INST_HANDLER_GET() macro for getting interrupt handler associated with the specified driver instance.
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- Introduced the NRFX_{PERIPH}_INST_GET() macro for getting pointer to the structure of the registers of the specified peripheral.
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- Introduced the NRF_TIMER_PRESCALER_CALCULATE() macro for computing prescaler value for given TIMER base frequency and desired frequency.
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- Introduced the NRF_TIMER_BASE_FREQUENCY_GET() macro for getting base frequency in Hz for the specified TIMER instance.
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- Added missing NRFX_RESET_REASON_CTRLAP_MASK in nrfx_reset_reason_mask_t for nRF9160.
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- Added missing NRFX_RESET_REASON_SREQ_MASK in nrfx_reset_reason_mask_t.
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### Changed
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- Updated MDK to version 8.51.0.
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- Refactored the TIMER driver to allow user handler to be NULL.
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- Removed magic numbers from nrf_twim_event_t type in TWIM HAL.
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### Fixed
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- Fixed the NRFX_ROUNDED_DIV() macro for negative numbers.
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- Disabled array bounds warning for nrf_clock_is_running() function that was false positive in GCC 12 and above.
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## [2.9.0] - 2022-07-19
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### Added
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- Added configuration parameter NRFX_NFCT_PARAM_ID_FDT_MIN that allows settting the value of the FRAMEDELAYMIN register.
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@ -2,10 +2,10 @@ nrfx
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####
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Origin:
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https://github.com/NordicSemiconductor/nrfx/tree/v2.9.0
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https://github.com/NordicSemiconductor/nrfx/tree/v2.10.0
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Status:
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v2.9.0
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v2.10.0
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Purpose:
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With added proper shims adapting it to Zephyr's APIs, nrfx will provide
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@ -32,7 +32,7 @@ URL:
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https://github.com/NordicSemiconductor/nrfx
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commit:
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16756cadac53aa72e4262dc3e17db73f6bda715c
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23fb4437c08a9edfdf6d34f002322f693a15e8fe
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Maintained-by:
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External
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@ -41,4 +41,4 @@ License:
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BSD-3-Clause
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License Link:
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https://github.com/NordicSemiconductor/nrfx/blob/v2.9.0/LICENSE
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https://github.com/NordicSemiconductor/nrfx/blob/v2.10.0/LICENSE
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@ -40,7 +40,7 @@ PROJECT_NAME = "nrfx"
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### EDIT THIS ###
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PROJECT_NUMBER = "2.9"
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PROJECT_NUMBER = "2.10"
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# Using the PROJECT_BRIEF tag one can provide an optional one line description
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# for a project that appears at the top of each page and should give viewer a
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@ -2077,15 +2077,7 @@ INCLUDE_FILE_PATTERNS =
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# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
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PREDEFINED = SUPPRESS_INLINE_IMPLEMENTATION \
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__NRFX_DOXYGEN__ \
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CONFIG_PURGE_ENABLED=1 \
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CONFIG_DISASSOCIATE_ENABLED=1 \
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CONFIG_GTS_ENABLED=1 \
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CONFIG_ORPHAN_ENABLED=1 \
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CONFIG_RXE_ENABLED=1 \
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CONFIG_START_ENABLED=1 \
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CONFIG_SYNC_ENABLED=1 \
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CONFIG_PANID_CONFLICT_ENABLED=1
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__NRFX_DOXYGEN__
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# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this
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# tag can be used to specify a list of macro names that should be expanded. The
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@ -1,4 +1,7 @@
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sphinx~=3.5
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sphinx-ncs-theme~=0.6.2
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breathe~=4.28
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m2r2~=0.2
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Sphinx!=5.0.0,<6,>=4.0
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sphinx-ncs-theme==0.6.5
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sphinx-rtd-theme==0.5.2
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breathe==4.34.0
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m2r2==0.3.2
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Jinja2==3.0.3
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docutils<0.17
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@ -253,7 +253,8 @@ void nrfx_clock_calibration_timer_start(uint8_t interval);
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/** @brief Function for stopping the calibration timer. */
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void nrfx_clock_calibration_timer_stop(void);
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/**@brief Function for returning a requested task address for the clock driver module.
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/**
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* @brief Function for returning a requested task address for the clock driver module.
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*
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* @param[in] task One of the peripheral tasks.
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*
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@ -261,7 +262,8 @@ void nrfx_clock_calibration_timer_stop(void);
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*/
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NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_task_addr(nrf_clock_task_t task);
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/**@brief Function for returning a requested event address for the clock driver module.
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/**
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* @brief Function for returning a requested event address for the clock driver module.
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*
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* @param[in] event One of the peripheral events.
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*
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@ -143,6 +143,15 @@ void nrfx_egu_trigger(nrfx_egu_t const * p_instance, uint8_t event_idx);
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*/
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void nrfx_egu_uninit(nrfx_egu_t const * p_instance);
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/**
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* @brief Macro returning EGU interrupt handler.
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*
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* param[in] idx EGU index.
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*
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* @return Interrupt handler.
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*/
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#define NRFX_EGU_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_egu_, idx, _irq_handler)
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/** @} */
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void nrfx_egu_0_irq_handler(void);
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@ -47,13 +47,25 @@ extern "C" {
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* @brief Interprocessor Communication (IPC) peripheral driver.
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*/
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#if NRFX_CHECK(NRFX_CONFIG_API_VER_2_10) || defined(__NRFX_DOXYGEN__)
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/**
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* @brief IPC driver handler type.
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*
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* @param[in] event_idx IPC event index.
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* @param[in] p_context Context passed to the interrupt handler, set on initialization.
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*/
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typedef void (*nrfx_ipc_handler_t)(uint8_t event_idx, void * p_context);
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#elif NRFX_CHECK(NRFX_CONFIG_API_VER_2_9)
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/**
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* @brief IPC driver handler type.
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*
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* @note This function is deprecated. Use @ref NRFX_CONFIG_API_VER_2_10 variant instead.
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*
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* @param[in] event_mask Bitmask with events that triggered the interrupt.
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* @param[in] p_context Context passed to the interrupt handler, set on initialization.
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*/
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typedef void (*nrfx_ipc_handler_t)(uint32_t event_mask, void * p_context);
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#endif
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/** @brief IPC configuration structure. */
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typedef struct
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* @brief Function for initializing the IPC driver.
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*
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* @param irq_priority Interrupt priority.
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* @param handler Event handler provided by the user. Cannot be NULL.
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* @param handler Event handler provided by the user.
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* @param p_context Context passed to event handler.
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*
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* @retval NRFX_SUCCESS Initialization was successful.
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@ -93,21 +105,34 @@ void nrfx_ipc_config_load(nrfx_ipc_config_t const * p_config);
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NRFX_STATIC_INLINE void nrfx_ipc_signal(uint8_t send_index);
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/**
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* @brief Function for storing data in GPMEM register in the IPC peripheral.
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* @brief Function for storing data in the general purpose memory register.
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*
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* @param mem_index Index of the memory cell.
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* @param data Data to be saved.
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*/
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NRFX_STATIC_INLINE void nrfx_ipc_gpmem_set(uint8_t mem_index, uint32_t data);
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#if NRFX_CHECK(NRFX_CONFIG_API_VER_2_10) || defined(__NRFX_DOXYGEN__)
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/**
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* @brief Function for getting data from the general purpose memory register.
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*
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* @param mem_index Index of the memory cell.
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*
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* @return Saved data.
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*/
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NRFX_STATIC_INLINE uint32_t nrfx_ipc_gpmem_get(uint8_t mem_index);
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#elif NRFX_CHECK(NRFX_CONFIG_API_VER_2_9)
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/**
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* @brief Function for getting data from the GPMEM register in the IPC peripheral.
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*
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* @note This function is deprecated. Use @ref nrfx_ipc_gpmem_get instead.
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*
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* @param mem_index Index of the memory cell.
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*
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* @return Saved data.
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*/
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NRFX_STATIC_INLINE uint32_t nrfx_ipc_mem_get(uint8_t mem_index);
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#endif
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/** @brief Function for uninitializing the IPC module. */
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void nrfx_ipc_uninit(void);
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@ -183,7 +208,11 @@ NRFX_STATIC_INLINE void nrfx_ipc_gpmem_set(uint8_t mem_index, uint32_t data)
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nrf_ipc_gpmem_set(NRF_IPC, mem_index, data);
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}
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#if NRFX_CHECK(NRFX_CONFIG_API_VER_2_10)
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NRFX_STATIC_INLINE uint32_t nrfx_ipc_gpmem_get(uint8_t mem_index)
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#elif NRFX_CHECK(NRFX_CONFIG_API_VER_2_9)
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NRFX_STATIC_INLINE uint32_t nrfx_ipc_mem_get(uint8_t mem_index)
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#endif
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{
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NRFX_ASSERT(mem_index < NRFX_ARRAY_SIZE(NRF_IPC->GPMEM));
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return nrf_ipc_gpmem_get(NRF_IPC, mem_index);
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@ -483,6 +483,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_pwm_event_address_get(nrfx_pwm_t const * p_inst
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}
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#endif // NRFX_DECLARE_ONLY
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/**
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* @brief Macro returning PWM interrupt handler.
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*
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* param[in] idx PWM index.
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*
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* @return Interrupt handler.
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*/
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#define NRFX_PWM_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_pwm_, idx, _irq_handler)
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/** @} */
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@ -361,6 +361,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_rtc_event_address_get(nrfx_rtc_t const * p_inst
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}
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#endif // NRFX_DECLARE_ONLY
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/**
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* @brief Macro returning RTC interrupt handler.
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*
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* param[in] idx RTC index.
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*
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* @return Interrupt handler.
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*/
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#define NRFX_RTC_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_rtc_, idx, _irq_handler)
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/** @} */
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@ -328,8 +328,10 @@ nrfx_err_t nrfx_saadc_simple_mode_set(uint32_t channel_mask,
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* @retval NRFX_SUCCESS Initialization was successful.
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* @retval NRFX_ERROR_BUSY There is a conversion or calibration ongoing.
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* @retval NRFX_ERROR_INVALID_PARAM Attempt to activate channel that is not configured.
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* @retval NRFX_ERROR_NOT_SUPPORTED Attempt to activate internal timer or oversampling without burst
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* with multiple channels enabled.
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* @retval NRFX_ERROR_NOT_SUPPORTED Attempt to activate either of the following:
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* * internal timer in the blocking mode,
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* * internal timer with multiple channels enabled,
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* * oversampling without burst with multiple channels enabled.
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*/
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nrfx_err_t nrfx_saadc_advanced_mode_set(uint32_t channel_mask,
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nrf_saadc_resolution_t resolution,
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@ -271,6 +271,15 @@ nrfx_err_t nrfx_spi_xfer(nrfx_spi_t const * p_instance,
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*/
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void nrfx_spi_abort(nrfx_spi_t const * p_instance);
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/**
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* @brief Macro returning SPI interrupt handler.
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*
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* param[in] idx SPI index.
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*
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* @return Interrupt handler.
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*/
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#define NRFX_SPI_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_spi_, idx, _irq_handler)
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/** @} */
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@ -417,6 +417,15 @@ uint32_t nrfx_spim_end_event_get(nrfx_spim_t const * p_instance);
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*/
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void nrfx_spim_abort(nrfx_spim_t const * p_instance);
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/**
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* @brief Macro returning SPIM interrupt handler.
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*
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* param[in] idx SPIM index.
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*
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* @return Interrupt handler.
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*/
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#define NRFX_SPIM_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_spim_, idx, _irq_handler)
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/** @} */
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@ -256,6 +256,15 @@ nrfx_err_t nrfx_spis_buffers_set(nrfx_spis_t const * p_instance,
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uint8_t * p_rx_buffer,
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size_t rx_buffer_length);
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/**
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* @brief Macro returning SPIS interrupt handler.
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*
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* param[in] idx SPIS index.
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*
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* @return Interrupt handler.
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*/
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#define NRFX_SPIS_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_spis_, idx, _irq_handler)
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/** @} */
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@ -131,8 +131,7 @@ typedef void (* nrfx_timer_event_handler_t)(nrf_timer_event_t event_type,
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*
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* @param[in] p_instance Pointer to the driver instance structure.
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* @param[in] p_config Pointer to the structure with the initial configuration.
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* @param[in] timer_event_handler Event handler provided by the user.
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* Must not be NULL.
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* @param[in] timer_event_handler Event handler provided by the user. Can be NULL.
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*
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* @retval NRFX_SUCCESS Initialization was successful.
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* @retval NRFX_ERROR_INVALID_STATE The instance is already initialized.
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@ -386,6 +385,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_timer_ms_to_ticks(nrfx_timer_t const * p_instan
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}
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#endif // NRFX_DECLARE_ONLY
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/**
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* @brief Macro returning TIMER interrupt handler.
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*
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* param[in] idx TIMER index.
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*
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* @return Interrupt handler.
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*/
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#define NRFX_TIMER_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_timer_, idx, _irq_handler)
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/** @} */
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@ -349,6 +349,15 @@ NRFX_STATIC_INLINE nrfx_err_t nrfx_twi_bus_recover(uint32_t scl_pin, uint32_t sd
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}
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#endif
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/**
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* @brief Macro returning TWI interrupt handler.
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*
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* param[in] idx TWI index.
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*
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* @return Interrupt handler.
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*/
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#define NRFX_TWI_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_twi_, idx, _irq_handler)
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/** @} */
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@ -389,6 +389,15 @@ NRFX_STATIC_INLINE nrfx_err_t nrfx_twim_bus_recover(uint32_t scl_pin, uint32_t s
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}
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#endif
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/**
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* @brief Macro returning TWIM interrupt handler.
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*
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* param[in] idx TWIM index.
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*
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* @return Interrupt handler.
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*/
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#define NRFX_TWIM_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_twim_, idx, _irq_handler)
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/** @} */
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void nrfx_twim_0_irq_handler(void);
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@ -404,6 +404,15 @@ NRFX_STATIC_INLINE size_t nrfx_twis_rx_amount(nrfx_twis_t const * p_instance)
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}
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#endif // NRFX_DECLARE_ONLY
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/**
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* @brief Macro returning TWIS interrupt handler.
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*
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* param[in] idx TWIS index.
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*
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* @return Interrupt handler.
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*/
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#define NRFX_TWIS_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_twis_, idx, _irq_handler)
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/** @} */
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@ -384,6 +384,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_uart_event_address_get(nrfx_uart_t const * p_in
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}
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#endif // NRFX_DECLARE_ONLY
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/**
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* @brief Macro returning UART interrupt handler.
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*
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* param[in] idx UART index.
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*
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* @return Interrupt handler.
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*/
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#define NRFX_UART_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_uart_, idx, _irq_handler)
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/** @} */
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@ -399,6 +399,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_uarte_event_address_get(nrfx_uarte_t const * p_
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}
|
||||
#endif // NRFX_DECLARE_ONLY
|
||||
|
||||
/**
|
||||
* @brief Macro returning UARTE interrupt handler.
|
||||
*
|
||||
* param[in] idx UARTE index.
|
||||
*
|
||||
* @return Interrupt handler.
|
||||
*/
|
||||
#define NRFX_UARTE_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_uarte_, idx, _irq_handler)
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
|
|
|
@ -205,6 +205,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_wdt_event_address_get(nrfx_wdt_t const * p_inst
|
|||
}
|
||||
#endif // NRFX_DECLARE_ONLY
|
||||
|
||||
/**
|
||||
* @brief Macro returning WDT interrupt handler.
|
||||
*
|
||||
* param[in] idx WDT index.
|
||||
*
|
||||
* @return Interrupt handler.
|
||||
*/
|
||||
#define NRFX_WDT_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_wdt_, idx, _irq_handler)
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
|
|
|
@ -177,7 +177,8 @@ extern "C" {
|
|||
*
|
||||
* @return Rounded (integer) result of dividing @c a by @c b.
|
||||
*/
|
||||
#define NRFX_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b))
|
||||
#define NRFX_ROUNDED_DIV(a, b) \
|
||||
((((a) < 0) ^ ((b) < 0)) ? (((a) - (b) / 2) / (b)) : (((a) + (b) / 2) / (b)))
|
||||
|
||||
/**
|
||||
* @brief Macro for performing integer division, making sure the result is rounded up.
|
||||
|
@ -212,7 +213,8 @@ extern "C" {
|
|||
*/
|
||||
#define NRFX_OFFSETOF(type, member) ((size_t)&(((type *)0)->member))
|
||||
|
||||
/**@brief Macro for checking if given lengths of EasyDMA transfers do not exceed
|
||||
/**
|
||||
* @brief Macro for checking if given lengths of EasyDMA transfers do not exceed
|
||||
* the limit of the specified peripheral.
|
||||
*
|
||||
* @param[in] peripheral Peripheral to check the lengths against.
|
||||
|
|
|
@ -49,7 +49,6 @@ static ipc_control_block_t m_ipc_cb;
|
|||
|
||||
nrfx_err_t nrfx_ipc_init(uint8_t irq_priority, nrfx_ipc_handler_t handler, void * p_context)
|
||||
{
|
||||
NRFX_ASSERT(handler);
|
||||
if (m_ipc_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
|
||||
{
|
||||
return NRFX_ERROR_ALREADY_INITIALIZED;
|
||||
|
@ -147,18 +146,26 @@ void nrfx_ipc_irq_handler(void)
|
|||
{
|
||||
// Get the information about events that fire this interrupt
|
||||
uint32_t events_map = nrf_ipc_int_pending_get(NRF_IPC);
|
||||
|
||||
// Clear these events
|
||||
uint32_t bitmask = events_map;
|
||||
|
||||
while (bitmask)
|
||||
{
|
||||
uint8_t event_idx = NRF_CTZ(bitmask);
|
||||
bitmask &= ~(1UL << event_idx);
|
||||
nrf_ipc_event_clear(NRF_IPC, nrf_ipc_receive_event_get(event_idx));
|
||||
#if NRFX_CHECK(NRFX_CONFIG_API_VER_2_10)
|
||||
if (m_ipc_cb.handler)
|
||||
{
|
||||
m_ipc_cb.handler(event_idx, m_ipc_cb.p_context);
|
||||
}
|
||||
|
||||
// Execute interrupt handler to provide information about events to app
|
||||
#elif NRFX_CHECK(NRFX_CONFIG_API_VER_2_9)
|
||||
}
|
||||
if (m_ipc_cb.handler)
|
||||
{
|
||||
m_ipc_cb.handler(events_map, m_ipc_cb.p_context);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#endif // NRFX_CHECK(NRFX_IPC_ENABLED)
|
||||
|
|
|
@ -81,7 +81,6 @@ nrfx_err_t nrfx_timer_init(nrfx_timer_t const * p_instance,
|
|||
NRFX_ASSERT(p_instance->p_reg != NRF_TIMER0);
|
||||
#endif
|
||||
NRFX_ASSERT(p_config);
|
||||
NRFX_ASSERT(timer_event_handler);
|
||||
|
||||
nrfx_err_t err_code;
|
||||
|
||||
|
@ -112,7 +111,8 @@ nrfx_err_t nrfx_timer_init(nrfx_timer_t const * p_instance,
|
|||
|
||||
nrf_timer_mode_set(p_instance->p_reg, p_config->mode);
|
||||
nrf_timer_bit_width_set(p_instance->p_reg, p_config->bit_width);
|
||||
nrf_timer_frequency_set(p_instance->p_reg, p_config->frequency);
|
||||
// nrf_timer_frequency_t is mapped to prescaler for 16MHz base clock frequency timers
|
||||
nrf_timer_prescaler_set(p_instance->p_reg, (uint32_t)p_config->frequency);
|
||||
|
||||
p_cb->state = NRFX_DRV_STATE_INITIALIZED;
|
||||
|
||||
|
@ -282,10 +282,13 @@ static void irq_handler(NRF_TIMER_Type * p_reg,
|
|||
{
|
||||
nrf_timer_event_clear(p_reg, event);
|
||||
NRFX_LOG_DEBUG("Compare event, channel: %d.", i);
|
||||
if (p_cb->handler)
|
||||
{
|
||||
p_cb->handler(event, p_cb->context);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#if NRFX_CHECK(NRFX_TIMER0_ENABLED)
|
||||
void nrfx_timer_0_irq_handler(void)
|
||||
|
|
|
@ -42,6 +42,10 @@ extern "C" {
|
|||
#define NRFX_EVENT_READBACK_ENABLED 1
|
||||
#endif
|
||||
|
||||
#if !defined(NRFX_CONFIG_API_VER_2_9) && !defined(NRFX_CONFIG_API_VER_2_10)
|
||||
#define NRFX_CONFIG_API_VER_2_9 1
|
||||
#endif
|
||||
|
||||
#if defined(NRFX_CLZ)
|
||||
#define NRF_CLZ(value) NRFX_CLZ(value)
|
||||
#else
|
||||
|
|
|
@ -47,6 +47,15 @@ extern "C" {
|
|||
* @brief Hardware access layer for managing the Event Generator Unit (EGU) peripheral.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro getting pointer to the structure of registers of the EGU peripheral.
|
||||
*
|
||||
* @param[in] idx EGU instance index.
|
||||
*
|
||||
* @return Pointer to the structure of registers of the EGU peripheral.
|
||||
*/
|
||||
#define NRF_EGU_INST_GET(idx) NRFX_CONCAT_2(NRF_EGU, idx)
|
||||
|
||||
/** @brief EGU tasks. */
|
||||
typedef enum
|
||||
{
|
||||
|
|
|
@ -47,6 +47,15 @@ extern "C" {
|
|||
* @brief Hardware access layer for managing the Pulse Width Modulation (PWM) peripheral.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro getting pointer to the structure of registers of the PWM peripheral.
|
||||
*
|
||||
* @param[in] idx PWM instance index.
|
||||
*
|
||||
* @return Pointer to the structure of registers of the PWM peripheral.
|
||||
*/
|
||||
#define NRF_PWM_INST_GET(idx) NRFX_CONCAT_2(NRF_PWM, idx)
|
||||
|
||||
/**
|
||||
* @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set
|
||||
* function call to specify that a given output channel shall not be
|
||||
|
|
|
@ -47,6 +47,15 @@ extern "C" {
|
|||
* @brief Hardware access layer for managing the Real Time Counter (RTC) peripheral.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro getting pointer to the structure of registers of the RTC peripheral.
|
||||
*
|
||||
* @param[in] idx RTC instance index.
|
||||
*
|
||||
* @return Pointer to the structure of registers of the RTC peripheral.
|
||||
*/
|
||||
#define NRF_RTC_INST_GET(idx) NRFX_CONCAT_2(NRF_RTC, idx)
|
||||
|
||||
/** @brief Macro for getting the number of compare channels available in a given RTC instance. */
|
||||
#define NRF_RTC_CC_CHANNEL_COUNT(id) NRFX_CONCAT_3(RTC, id, _CC_NUM)
|
||||
|
||||
|
|
|
@ -47,6 +47,15 @@ extern "C" {
|
|||
* @brief Hardware access layer for managing the SPI peripheral.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro getting pointer to the structure of registers of the SPI peripheral.
|
||||
*
|
||||
* @param[in] idx SPI instance index.
|
||||
*
|
||||
* @return Pointer to the structure of registers of the SPI peripheral.
|
||||
*/
|
||||
#define NRF_SPI_INST_GET(idx) NRFX_CONCAT_2(NRF_SPI, idx)
|
||||
|
||||
/**
|
||||
* @brief This value can be used as a parameter for the @ref nrf_spi_pins_set
|
||||
* function to specify that a given SPI signal (SCK, MOSI, or MISO)
|
||||
|
|
|
@ -47,6 +47,15 @@ extern "C" {
|
|||
* @brief Hardware access layer for managing the SPIM peripheral.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro getting pointer to the structure of registers of the SPIM peripheral.
|
||||
*
|
||||
* @param[in] idx SPIM instance index.
|
||||
*
|
||||
* @return Pointer to the structure of registers of the SPIM peripheral.
|
||||
*/
|
||||
#define NRF_SPIM_INST_GET(idx) NRFX_CONCAT_2(NRF_SPIM, idx)
|
||||
|
||||
#if defined(SPIM_FREQUENCY_FREQUENCY_M32) || defined(__NRFX_DOXYGEN__)
|
||||
/** @brief Symbol indicating whether 32 MHz clock frequency is available. */
|
||||
#define NRF_SPIM_HAS_32_MHZ_FREQ 1
|
||||
|
|
|
@ -47,6 +47,15 @@ extern "C" {
|
|||
* @brief Hardware access layer for managing the SPIS peripheral.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro getting pointer to the structure of registers of the SPIS peripheral.
|
||||
*
|
||||
* @param[in] idx SPIS instance index.
|
||||
*
|
||||
* @return Pointer to the structure of registers of the SPIS peripheral.
|
||||
*/
|
||||
#define NRF_SPIS_INST_GET(idx) NRFX_CONCAT_2(NRF_SPIS, idx)
|
||||
|
||||
/**
|
||||
* @brief This value can be used as a parameter for the @ref nrf_spis_pins_set
|
||||
* function to specify that a given SPI signal (SCK, MOSI, or MISO)
|
||||
|
|
|
@ -47,6 +47,15 @@ extern "C" {
|
|||
* @brief Hardware access layer for managing the TIMER peripheral.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro getting pointer to the structure of registers of the TIMER peripheral.
|
||||
*
|
||||
* @param[in] idx TIMER instance index.
|
||||
*
|
||||
* @return Pointer to the structure of registers of the TIMER peripheral.
|
||||
*/
|
||||
#define NRF_TIMER_INST_GET(idx) NRFX_CONCAT_2(NRF_TIMER, idx)
|
||||
|
||||
#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__)
|
||||
/** @brief Symbol indicating whether timer has capture/compare channel 4. */
|
||||
#define NRF_TIMER_HAS_CC4 1
|
||||
|
@ -89,6 +98,9 @@ extern "C" {
|
|||
#define NRF_TIMER_HAS_ONE_SHOT 0
|
||||
#endif
|
||||
|
||||
/** @brief Base frequency value 16 MHz for timer. */
|
||||
#define NRF_TIMER_BASE_FREQUENCY_16MHZ (16000000UL)
|
||||
|
||||
/** @brief Maximum value of PRESCALER register. */
|
||||
#define NRF_TIMER_PRESCALER_MAX 9
|
||||
|
||||
|
@ -154,6 +166,24 @@ extern "C" {
|
|||
#error "Not supported timer count"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Macro for getting base frequency value in Hz for the specified timer.
|
||||
*
|
||||
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
|
||||
*/
|
||||
#define NRF_TIMER_BASE_FREQUENCY_GET(p_reg) NRF_TIMER_BASE_FREQUENCY_16MHZ
|
||||
|
||||
/**
|
||||
* @brief Macro for computing prescaler value for given base frequency and desired frequency.
|
||||
*
|
||||
* @warning Not every combination of base frequency and desired frequency is supported.
|
||||
*
|
||||
* @param[in] base_freq Base clock frequency for timer in Hz.
|
||||
* @param[in] frequency Desired frequency value in Hz.
|
||||
*/
|
||||
#define NRF_TIMER_PRESCALER_CALCULATE(base_freq, frequency) \
|
||||
NRF_CTZ((uint32_t)(base_freq) / (uint32_t)(frequency))
|
||||
|
||||
/**
|
||||
* @brief Macro for getting the number of capture/compare channels available
|
||||
* in a given timer instance.
|
||||
|
|
|
@ -47,6 +47,15 @@ extern "C" {
|
|||
* @brief Hardware access layer for managing the TWI peripheral.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro getting pointer to the structure of registers of the TWI peripheral.
|
||||
*
|
||||
* @param[in] idx TWI instance index.
|
||||
*
|
||||
* @return Pointer to the structure of registers of the TWI peripheral.
|
||||
*/
|
||||
#define NRF_TWI_INST_GET(idx) NRFX_CONCAT_2(NRF_TWI, idx)
|
||||
|
||||
/** @brief TWI tasks. */
|
||||
typedef enum
|
||||
{
|
||||
|
|
|
@ -47,6 +47,15 @@ extern "C" {
|
|||
* @brief Hardware access layer for managing the TWIM peripheral.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro getting pointer to the structure of registers of the TWIM peripheral.
|
||||
*
|
||||
* @param[in] idx TWIM instance index.
|
||||
*
|
||||
* @return Pointer to the structure of registers of the TWIM peripheral.
|
||||
*/
|
||||
#define NRF_TWIM_INST_GET(idx) NRFX_CONCAT_2(NRF_TWIM, idx)
|
||||
|
||||
#if defined(TWIM_FREQUENCY_FREQUENCY_K1000) || defined(__NRFX_DOXYGEN__)
|
||||
/** @brief Symbol indicating whether 1000 kHz clock frequency is available. */
|
||||
#define NRF_TWIM_HAS_1000_KHZ_FREQ 1
|
||||
|
@ -69,7 +78,7 @@ typedef enum
|
|||
{
|
||||
NRF_TWIM_EVENT_STOPPED = offsetof(NRF_TWIM_Type, EVENTS_STOPPED), ///< TWI stopped.
|
||||
NRF_TWIM_EVENT_ERROR = offsetof(NRF_TWIM_Type, EVENTS_ERROR), ///< TWI error.
|
||||
NRF_TWIM_EVENT_SUSPENDED = 0x148, ///< TWI suspended.
|
||||
NRF_TWIM_EVENT_SUSPENDED = offsetof(NRF_TWIM_Type, EVENTS_SUSPENDED), ///< TWI suspended.
|
||||
NRF_TWIM_EVENT_RXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_RXSTARTED), ///< Receive sequence started.
|
||||
NRF_TWIM_EVENT_TXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_TXSTARTED), ///< Transmit sequence started.
|
||||
NRF_TWIM_EVENT_LASTRX = offsetof(NRF_TWIM_Type, EVENTS_LASTRX), ///< Byte boundary, starting to receive the last byte.
|
||||
|
|
|
@ -48,6 +48,15 @@ extern "C" {
|
|||
* (TWIS) peripheral.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro getting pointer to the structure of registers of the TWIS peripheral.
|
||||
*
|
||||
* @param[in] idx TWIS instance index.
|
||||
*
|
||||
* @return Pointer to the structure of registers of the TWIS peripheral.
|
||||
*/
|
||||
#define NRF_TWIS_INST_GET(idx) NRFX_CONCAT_2(NRF_TWIS, idx)
|
||||
|
||||
/** @brief TWIS tasks. */
|
||||
typedef enum
|
||||
{
|
||||
|
|
|
@ -49,6 +49,15 @@ extern "C" {
|
|||
* @brief Hardware access layer for managing the UARTE peripheral.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro getting pointer to the structure of registers of the UARTE peripheral.
|
||||
*
|
||||
* @param[in] idx UARTE instance index.
|
||||
*
|
||||
* @return Pointer to the structure of registers of the UARTE peripheral.
|
||||
*/
|
||||
#define NRF_UARTE_INST_GET(idx) NRFX_CONCAT_2(NRF_UARTE, idx)
|
||||
|
||||
/** @brief UARTE tasks. */
|
||||
typedef enum
|
||||
{
|
||||
|
|
|
@ -51,6 +51,15 @@ extern "C" {
|
|||
* @brief Hardware access layer for managing the Watchdog Timer (WDT) peripheral.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro getting pointer to the structure of registers of the WDT peripheral.
|
||||
*
|
||||
* @param[in] idx WDT instance index.
|
||||
*
|
||||
* @return Pointer to the structure of registers of the WDT peripheral.
|
||||
*/
|
||||
#define NRF_WDT_INST_GET(idx) NRFX_CONCAT_2(NRF_WDT, idx)
|
||||
|
||||
/** @brief Number of WDT channels. */
|
||||
#define NRF_WDT_CHANNEL_NUMBER 0x8UL
|
||||
|
||||
|
|
|
@ -59,46 +59,48 @@ extern "C" {
|
|||
typedef enum
|
||||
{
|
||||
#if !NRF_POWER_HAS_RESETREAS || defined(__NRFX_DOXYGEN__)
|
||||
NRFX_RESET_REASON_RESETPIN_MASK = RESET_RESETREAS_RESETPIN_Msk,
|
||||
/**< Reset from pin-reset detected. */
|
||||
NRFX_RESET_REASON_RESETPIN_MASK = RESET_RESETREAS_RESETPIN_Msk,
|
||||
/**< Reset from watchdog/application watchdog timer 0 detected. */
|
||||
NRFX_RESET_REASON_DOG0_MASK = RESET_RESETREAS_DOG0_Msk,
|
||||
/**< Reset from watchdog/application watchdog timer 0 detected. */
|
||||
NRFX_RESET_REASON_DOG_MASK = NRFX_RESET_REASON_DOG0_MASK,
|
||||
/**< Reset from watchdog/application watchdog timer 0 detected. */
|
||||
NRFX_RESET_REASON_CTRLAP_MASK = RESET_RESETREAS_CTRLAP_Msk,
|
||||
/**< Reset from application CTRL-AP detected. */
|
||||
NRFX_RESET_REASON_CTRLAP_MASK = RESET_RESETREAS_CTRLAP_Msk,
|
||||
/**< Reset from soft reset/application soft reset detected. Deprecated. */
|
||||
NRFX_RESETREAS_SREQ_MASK = RESET_RESETREAS_SREQ_Msk,
|
||||
/**< Reset from soft reset/application soft reset detected. */
|
||||
NRFX_RESET_REASON_LOCKUP_MASK = RESET_RESETREAS_LOCKUP_Msk,
|
||||
NRFX_RESET_REASON_SREQ_MASK = RESET_RESETREAS_SREQ_Msk,
|
||||
/**< Reset from CPU lockup/application CPU lockup detected. */
|
||||
NRFX_RESET_REASON_OFF_MASK = RESET_RESETREAS_OFF_Msk,
|
||||
NRFX_RESET_REASON_LOCKUP_MASK = RESET_RESETREAS_LOCKUP_Msk,
|
||||
/**< Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from
|
||||
* GPIO. */
|
||||
NRFX_RESET_REASON_LPCOMP_MASK = RESET_RESETREAS_LPCOMP_Msk,
|
||||
NRFX_RESET_REASON_OFF_MASK = RESET_RESETREAS_OFF_Msk,
|
||||
/**< Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from
|
||||
* LPCOMP. */
|
||||
NRFX_RESET_REASON_DIF_MASK = RESET_RESETREAS_DIF_Msk,
|
||||
NRFX_RESET_REASON_LPCOMP_MASK = RESET_RESETREAS_LPCOMP_Msk,
|
||||
/**< Reset due to wakeup from System OFF mode when wakeup is triggered by entering the debug
|
||||
* interface mode. */
|
||||
NRFX_RESET_REASON_DIF_MASK = RESET_RESETREAS_DIF_Msk,
|
||||
#if NRF_RESET_HAS_NETWORK
|
||||
NRFX_RESET_REASON_LSREQ_MASK = RESET_RESETREAS_LSREQ_Msk,
|
||||
/**< Reset from network soft reset detected. */
|
||||
NRFX_RESET_REASON_LLOCKUP_MASK = RESET_RESETREAS_LLOCKUP_Msk,
|
||||
NRFX_RESET_REASON_LSREQ_MASK = RESET_RESETREAS_LSREQ_Msk,
|
||||
/**< Reset from network CPU lockup detected. */
|
||||
NRFX_RESET_REASON_LDOG_MASK = RESET_RESETREAS_LDOG_Msk,
|
||||
NRFX_RESET_REASON_LLOCKUP_MASK = RESET_RESETREAS_LLOCKUP_Msk,
|
||||
/**< Reset from network watchdog timer detected. */
|
||||
NRFX_RESET_REASON_MFORCEOFF_MASK = RESET_RESETREAS_MFORCEOFF_Msk,
|
||||
NRFX_RESET_REASON_LDOG_MASK = RESET_RESETREAS_LDOG_Msk,
|
||||
/**< Force off reset from application core detected. */
|
||||
NRFX_RESET_REASON_MFORCEOFF_MASK = RESET_RESETREAS_MFORCEOFF_Msk,
|
||||
#endif // NRF_RESET_HAS_NETWORK
|
||||
/**< Reset after wakeup from System OFF mode due to NFC field being detected. */
|
||||
NRFX_RESET_REASON_NFC_MASK = RESET_RESETREAS_NFC_Msk,
|
||||
/**< Reset after wakeup from System OFF mode due to NRF field being detected. */
|
||||
NRFX_RESET_REASON_DOG1_MASK = RESET_RESETREAS_DOG1_Msk,
|
||||
/**< Reset from application watchdog timer 1 detected. */
|
||||
NRFX_RESET_REASON_VBUS_MASK = RESET_RESETREAS_VBUS_Msk,
|
||||
NRFX_RESET_REASON_DOG1_MASK = RESET_RESETREAS_DOG1_Msk,
|
||||
/**< Reset after wakeup from System OFF mode due to VBUS rising into valid range. */
|
||||
NRFX_RESET_REASON_VBUS_MASK = RESET_RESETREAS_VBUS_Msk,
|
||||
#if NRF_RESET_HAS_NETWORK
|
||||
NRFX_RESET_REASON_LCTRLAP_MASK = RESET_RESETREAS_LCTRLAP_Msk,
|
||||
/**< Reset from network CTRL-AP detected. */
|
||||
NRFX_RESET_REASON_LCTRLAP_MASK = RESET_RESETREAS_LCTRLAP_Msk,
|
||||
#endif // NRF_RESET_HAS_NETWORK
|
||||
#else
|
||||
NRFX_RESET_REASON_RESETPIN_MASK = POWER_RESETREAS_RESETPIN_Msk,
|
||||
|
@ -106,6 +108,9 @@ typedef enum
|
|||
NRFX_RESET_REASON_SREQ_MASK = POWER_RESETREAS_SREQ_Msk ,
|
||||
NRFX_RESET_REASON_LOCKUP_MASK = POWER_RESETREAS_LOCKUP_Msk,
|
||||
NRFX_RESET_REASON_OFF_MASK = POWER_RESETREAS_OFF_Msk,
|
||||
#if defined(POWER_RESETREAS_CTRLAP_Msk)
|
||||
NRFX_RESET_REASON_CTRLAP_MASK = POWER_RESETREAS_CTRLAP_Msk,
|
||||
#endif
|
||||
#if defined(POWER_RESETREAS_LPCOMP_Msk)
|
||||
NRFX_RESET_REASON_LPCOMP_MASK = POWER_RESETREAS_LPCOMP_Msk,
|
||||
#endif
|
||||
|
|
|
@ -72,6 +72,10 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
|
||||
#define GET_SP() __current_sp()
|
||||
|
||||
#ifndef __DEPRECATED
|
||||
#define __DEPRECATED(msg) __attribute__((deprecated(msg)))
|
||||
#endif
|
||||
|
||||
#ifndef NRF_STATIC_ASSERT
|
||||
#define NRF_STATIC_ASSERT(cond, msg) \
|
||||
;enum { NRF_STRING_CONCATENATE(static_assert_on_line_, __LINE__) = 1 / (!!(cond)) }
|
||||
|
@ -105,6 +109,10 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
|
||||
#define GET_SP() __current_sp()
|
||||
|
||||
#ifndef __DEPRECATED
|
||||
#define __DEPRECATED(msg) __attribute__((deprecated(msg)))
|
||||
#endif
|
||||
|
||||
#ifndef NRF_STATIC_ASSERT
|
||||
#ifdef __cplusplus
|
||||
#ifndef _Static_assert
|
||||
|
@ -153,6 +161,10 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
|
||||
#define GET_SP() __get_SP()
|
||||
|
||||
#ifndef __DEPRECATED
|
||||
#define __DEPRECATED(msg) __attribute__((deprecated(msg)))
|
||||
#endif
|
||||
|
||||
#ifndef NRF_STATIC_ASSERT
|
||||
#define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
|
||||
#endif
|
||||
|
@ -185,6 +197,10 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
|
||||
#define GET_SP() gcc_current_sp()
|
||||
|
||||
#ifndef __DEPRECATED
|
||||
#define __DEPRECATED(msg) __attribute__((deprecated(msg)))
|
||||
#endif
|
||||
|
||||
static inline unsigned int gcc_current_sp(void)
|
||||
{
|
||||
unsigned int stack_pointer = 0;
|
||||
|
@ -230,6 +246,10 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
|
||||
#define GET_SP() __get_MSP()
|
||||
|
||||
#ifndef __DEPRECATED
|
||||
#define __DEPRECATED(msg)
|
||||
#endif
|
||||
|
||||
#ifndef NRF_STATIC_ASSERT
|
||||
#define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
|
||||
#endif
|
||||
|
|
|
@ -37,7 +37,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
|
||||
/* MDK version */
|
||||
#define MDK_MAJOR_VERSION 8
|
||||
#define MDK_MINOR_VERSION 47
|
||||
#define MDK_MINOR_VERSION 51
|
||||
#define MDK_MICRO_VERSION 0
|
||||
|
||||
|
||||
|
|
|
@ -1,41 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n
|
||||
\n
|
||||
SPDX-License-Identifier: BSD-3-Clause\n
|
||||
\n
|
||||
Redistribution and use in source and binary forms, with or without\n
|
||||
modification, are permitted provided that the following conditions are met:\n
|
||||
\n
|
||||
1. Redistributions of source code must retain the above copyright notice, this\n
|
||||
list of conditions and the following disclaimer.\n
|
||||
\n
|
||||
2. Redistributions in binary form must reproduce the above copyright\n
|
||||
notice, this list of conditions and the following disclaimer in the\n
|
||||
documentation and/or other materials provided with the distribution.\n
|
||||
\n
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
|
||||
contributors may be used to endorse or promote products derived from this\n
|
||||
software without specific prior written permission.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
|
||||
POSSIBILITY OF SUCH DAMAGE.\n
|
||||
*
|
||||
* @file nrf51.h
|
||||
* @brief CMSIS HeaderFile
|
||||
* @version 522
|
||||
* @date 11. May 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:35
|
||||
* @date 19. October 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:46
|
||||
* from File 'nrf51.svd',
|
||||
* last modified on Wednesday, 11.05.2022 10:25:34
|
||||
* last modified on Wednesday, 19.10.2022 09:13:55
|
||||
*/
|
||||
|
||||
|
||||
|
@ -112,6 +112,7 @@ typedef enum {
|
|||
|
||||
/* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */
|
||||
#define __CM0_REV 0x0301U /*!< CM0 Core Revision */
|
||||
#define __INTERRUPTS_MAX 32 /*!< Top interrupt number */
|
||||
#define __DSP_PRESENT 0 /*!< DSP present or not */
|
||||
#define __VTOR_PRESENT 0 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
|
||||
|
|
|
@ -171,6 +171,19 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk
|
||||
#endif
|
||||
|
||||
/* UART */
|
||||
#ifndef PSELRTS
|
||||
#define PSELRTS PSEL.RTS
|
||||
#endif
|
||||
#ifndef PSELTXD
|
||||
#define PSELTXD PSEL.TXD
|
||||
#endif
|
||||
#ifndef PSELCTS
|
||||
#define PSELCTS PSEL.CTS
|
||||
#endif
|
||||
#ifndef PSELRXD
|
||||
#define PSELRXD PSEL.RXD
|
||||
#endif
|
||||
|
||||
/* From nrf51_deprecated.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */
|
||||
|
||||
|
|
|
@ -1,28 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.SPDX-License-Identifier: BSD
|
||||
* -3-ClauseRedistribution and use in source and binary forms, with or withoutmodification, are permitt
|
||||
* ed provided that the following conditions are met:1. Redistributions of source code must retain the
|
||||
* above copyright notice, this list of conditions and the following disclaimer.2. Redistributions in b
|
||||
* inary form must reproduce the above copyright notice, this list of conditions and the following disc
|
||||
* laimer in the documentation and/or other materials provided with the distribution.3. Neither the nam
|
||||
* e of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote pr
|
||||
* oducts derived from this software without specific prior written permission.THIS SOFTWARE IS PROVIDE
|
||||
* D BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
|
||||
* BUT NOT LIMITED TO, THEIMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSEA
|
||||
* RE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BELIABLE FOR ANY DIRECT, I
|
||||
* NDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, ORCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PRO
|
||||
* CUREMENT OFSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESSINTERRUPTION) HOW
|
||||
* EVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER INCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEP
|
||||
* OSSIBILITY OF SUCH DAMAGE.
|
||||
Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* @file nrf52.h
|
||||
* @brief CMSIS HeaderFile
|
||||
* @version 1
|
||||
* @date 11. May 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:39
|
||||
* @date 19. October 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:56
|
||||
* from File 'nrf52.svd',
|
||||
* last modified on Wednesday, 11.05.2022 10:25:34
|
||||
* last modified on Wednesday, 19.10.2022 09:13:55
|
||||
*/
|
||||
|
||||
|
||||
|
@ -117,6 +130,7 @@ typedef enum {
|
|||
|
||||
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */
|
||||
#define __DSP_PRESENT 1 /*!< DSP present or not */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
|
|
|
@ -1,41 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n
|
||||
\n
|
||||
SPDX-License-Identifier: BSD-3-Clause\n
|
||||
\n
|
||||
Redistribution and use in source and binary forms, with or without\n
|
||||
modification, are permitted provided that the following conditions are met:\n
|
||||
\n
|
||||
1. Redistributions of source code must retain the above copyright notice, this\n
|
||||
list of conditions and the following disclaimer.\n
|
||||
\n
|
||||
2. Redistributions in binary form must reproduce the above copyright\n
|
||||
notice, this list of conditions and the following disclaimer in the\n
|
||||
documentation and/or other materials provided with the distribution.\n
|
||||
\n
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
|
||||
contributors may be used to endorse or promote products derived from this\n
|
||||
software without specific prior written permission.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
|
||||
POSSIBILITY OF SUCH DAMAGE.\n
|
||||
*
|
||||
* @file nrf52805.h
|
||||
* @brief CMSIS HeaderFile
|
||||
* @version 1
|
||||
* @date 11. May 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:36
|
||||
* @date 19. October 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:52
|
||||
* from File 'nrf52805.svd',
|
||||
* last modified on Wednesday, 11.05.2022 10:25:34
|
||||
* last modified on Wednesday, 19.10.2022 09:13:55
|
||||
*/
|
||||
|
||||
|
||||
|
@ -117,6 +117,7 @@ typedef enum {
|
|||
|
||||
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */
|
||||
#define __DSP_PRESENT 1 /*!< DSP present or not */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
|
|
|
@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
|
|||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>0</vendorSystickConfig>
|
||||
</cpu>
|
||||
<headerSystemFilename>system_nrf52805</headerSystemFilename>
|
||||
<headerSystemFilename>system_nrf52</headerSystemFilename>
|
||||
<headerDefinitionsPrefix>NRF_</headerDefinitionsPrefix>
|
||||
<vendorExtensions>
|
||||
<ExampleStackSize>2048</ExampleStackSize>
|
||||
|
|
|
@ -1,41 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n
|
||||
\n
|
||||
SPDX-License-Identifier: BSD-3-Clause\n
|
||||
\n
|
||||
Redistribution and use in source and binary forms, with or without\n
|
||||
modification, are permitted provided that the following conditions are met:\n
|
||||
\n
|
||||
1. Redistributions of source code must retain the above copyright notice, this\n
|
||||
list of conditions and the following disclaimer.\n
|
||||
\n
|
||||
2. Redistributions in binary form must reproduce the above copyright\n
|
||||
notice, this list of conditions and the following disclaimer in the\n
|
||||
documentation and/or other materials provided with the distribution.\n
|
||||
\n
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
|
||||
contributors may be used to endorse or promote products derived from this\n
|
||||
software without specific prior written permission.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
|
||||
POSSIBILITY OF SUCH DAMAGE.\n
|
||||
*
|
||||
* @file nrf52810.h
|
||||
* @brief CMSIS HeaderFile
|
||||
* @version 1
|
||||
* @date 11. May 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:36
|
||||
* @date 19. October 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:53
|
||||
* from File 'nrf52810.svd',
|
||||
* last modified on Wednesday, 11.05.2022 10:25:34
|
||||
* last modified on Wednesday, 19.10.2022 09:13:55
|
||||
*/
|
||||
|
||||
|
||||
|
@ -120,6 +120,7 @@ typedef enum {
|
|||
|
||||
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */
|
||||
#define __DSP_PRESENT 1 /*!< DSP present or not */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
|
|
|
@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
|
|||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>0</vendorSystickConfig>
|
||||
</cpu>
|
||||
<headerSystemFilename>system_nrf52810</headerSystemFilename>
|
||||
<headerSystemFilename>system_nrf52</headerSystemFilename>
|
||||
<headerDefinitionsPrefix>NRF_</headerDefinitionsPrefix>
|
||||
<vendorExtensions>
|
||||
<ExampleStackSize>2048</ExampleStackSize>
|
||||
|
|
|
@ -1,41 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n
|
||||
\n
|
||||
SPDX-License-Identifier: BSD-3-Clause\n
|
||||
\n
|
||||
Redistribution and use in source and binary forms, with or without\n
|
||||
modification, are permitted provided that the following conditions are met:\n
|
||||
\n
|
||||
1. Redistributions of source code must retain the above copyright notice, this\n
|
||||
list of conditions and the following disclaimer.\n
|
||||
\n
|
||||
2. Redistributions in binary form must reproduce the above copyright\n
|
||||
notice, this list of conditions and the following disclaimer in the\n
|
||||
documentation and/or other materials provided with the distribution.\n
|
||||
\n
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
|
||||
contributors may be used to endorse or promote products derived from this\n
|
||||
software without specific prior written permission.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
|
||||
POSSIBILITY OF SUCH DAMAGE.\n
|
||||
*
|
||||
* @file nrf52811.h
|
||||
* @brief CMSIS HeaderFile
|
||||
* @version 1
|
||||
* @date 11. May 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:37
|
||||
* @date 19. October 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:54
|
||||
* from File 'nrf52811.svd',
|
||||
* last modified on Wednesday, 11.05.2022 10:25:34
|
||||
* last modified on Wednesday, 19.10.2022 09:13:55
|
||||
*/
|
||||
|
||||
|
||||
|
@ -120,6 +120,7 @@ typedef enum {
|
|||
|
||||
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */
|
||||
#define __DSP_PRESENT 1 /*!< DSP present or not */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
|
|
|
@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
|
|||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>0</vendorSystickConfig>
|
||||
</cpu>
|
||||
<headerSystemFilename>system_nrf52811</headerSystemFilename>
|
||||
<headerSystemFilename>system_nrf52</headerSystemFilename>
|
||||
<headerDefinitionsPrefix>NRF_</headerDefinitionsPrefix>
|
||||
<vendorExtensions>
|
||||
<ExampleStackSize>2048</ExampleStackSize>
|
||||
|
|
|
@ -1,41 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n
|
||||
\n
|
||||
SPDX-License-Identifier: BSD-3-Clause\n
|
||||
\n
|
||||
Redistribution and use in source and binary forms, with or without\n
|
||||
modification, are permitted provided that the following conditions are met:\n
|
||||
\n
|
||||
1. Redistributions of source code must retain the above copyright notice, this\n
|
||||
list of conditions and the following disclaimer.\n
|
||||
\n
|
||||
2. Redistributions in binary form must reproduce the above copyright\n
|
||||
notice, this list of conditions and the following disclaimer in the\n
|
||||
documentation and/or other materials provided with the distribution.\n
|
||||
\n
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
|
||||
contributors may be used to endorse or promote products derived from this\n
|
||||
software without specific prior written permission.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
|
||||
POSSIBILITY OF SUCH DAMAGE.\n
|
||||
*
|
||||
* @file nrf52820.h
|
||||
* @brief CMSIS HeaderFile
|
||||
* @version 1
|
||||
* @date 11. May 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:38
|
||||
* @date 19. October 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:55
|
||||
* from File 'nrf52820.svd',
|
||||
* last modified on Wednesday, 11.05.2022 10:25:34
|
||||
* last modified on Wednesday, 19.10.2022 09:13:55
|
||||
*/
|
||||
|
||||
|
||||
|
@ -119,6 +119,7 @@ typedef enum {
|
|||
|
||||
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */
|
||||
#define __DSP_PRESENT 1 /*!< DSP present or not */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
|
|
|
@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
|
|||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>0</vendorSystickConfig>
|
||||
</cpu>
|
||||
<headerSystemFilename>system_nrf52820</headerSystemFilename>
|
||||
<headerSystemFilename>system_nrf52</headerSystemFilename>
|
||||
<headerDefinitionsPrefix>NRF_</headerDefinitionsPrefix>
|
||||
<vendorExtensions>
|
||||
<ExampleStackSize>2048</ExampleStackSize>
|
||||
|
|
|
@ -1,41 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n
|
||||
\n
|
||||
SPDX-License-Identifier: BSD-3-Clause\n
|
||||
\n
|
||||
Redistribution and use in source and binary forms, with or without\n
|
||||
modification, are permitted provided that the following conditions are met:\n
|
||||
\n
|
||||
1. Redistributions of source code must retain the above copyright notice, this\n
|
||||
list of conditions and the following disclaimer.\n
|
||||
\n
|
||||
2. Redistributions in binary form must reproduce the above copyright\n
|
||||
notice, this list of conditions and the following disclaimer in the\n
|
||||
documentation and/or other materials provided with the distribution.\n
|
||||
\n
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
|
||||
contributors may be used to endorse or promote products derived from this\n
|
||||
software without specific prior written permission.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
|
||||
POSSIBILITY OF SUCH DAMAGE.\n
|
||||
*
|
||||
* @file nrf52833.h
|
||||
* @brief CMSIS HeaderFile
|
||||
* @version 1
|
||||
* @date 11. May 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:41
|
||||
* @date 19. October 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:57
|
||||
* from File 'nrf52833.svd',
|
||||
* last modified on Wednesday, 11.05.2022 10:25:34
|
||||
* last modified on Wednesday, 19.10.2022 09:13:55
|
||||
*/
|
||||
|
||||
|
||||
|
@ -134,6 +134,7 @@ typedef enum {
|
|||
|
||||
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */
|
||||
#define __DSP_PRESENT 1 /*!< DSP present or not */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
|
|
|
@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
|
|||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>0</vendorSystickConfig>
|
||||
</cpu>
|
||||
<headerSystemFilename>system_nrf52833</headerSystemFilename>
|
||||
<headerSystemFilename>system_nrf52</headerSystemFilename>
|
||||
<headerDefinitionsPrefix>NRF_</headerDefinitionsPrefix>
|
||||
<vendorExtensions>
|
||||
<ExampleStackSize>2048</ExampleStackSize>
|
||||
|
|
|
@ -1,41 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n
|
||||
\n
|
||||
SPDX-License-Identifier: BSD-3-Clause\n
|
||||
\n
|
||||
Redistribution and use in source and binary forms, with or without\n
|
||||
modification, are permitted provided that the following conditions are met:\n
|
||||
\n
|
||||
1. Redistributions of source code must retain the above copyright notice, this\n
|
||||
list of conditions and the following disclaimer.\n
|
||||
\n
|
||||
2. Redistributions in binary form must reproduce the above copyright\n
|
||||
notice, this list of conditions and the following disclaimer in the\n
|
||||
documentation and/or other materials provided with the distribution.\n
|
||||
\n
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
|
||||
contributors may be used to endorse or promote products derived from this\n
|
||||
software without specific prior written permission.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
|
||||
POSSIBILITY OF SUCH DAMAGE.\n
|
||||
*
|
||||
* @file nrf52840.h
|
||||
* @brief CMSIS HeaderFile
|
||||
* @version 1
|
||||
* @date 11. May 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:43
|
||||
* @date 19. October 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:59
|
||||
* from File 'nrf52840.svd',
|
||||
* last modified on Wednesday, 11.05.2022 10:25:34
|
||||
* last modified on Wednesday, 19.10.2022 09:13:55
|
||||
*/
|
||||
|
||||
|
||||
|
@ -136,6 +136,7 @@ typedef enum {
|
|||
|
||||
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */
|
||||
#define __DSP_PRESENT 1 /*!< DSP present or not */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
|
|
|
@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
|
|||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>0</vendorSystickConfig>
|
||||
</cpu>
|
||||
<headerSystemFilename>system_nrf52840</headerSystemFilename>
|
||||
<headerSystemFilename>system_nrf52</headerSystemFilename>
|
||||
<headerDefinitionsPrefix>NRF_</headerDefinitionsPrefix>
|
||||
<vendorExtensions>
|
||||
<ExampleStackSize>2048</ExampleStackSize>
|
||||
|
|
|
@ -230,6 +230,7 @@ static bool nrf52_configuration_255(void) __UNUSED;
|
|||
static bool nrf52_configuration_256(void) __UNUSED;
|
||||
static bool nrf52_configuration_257(void) __UNUSED;
|
||||
static bool nrf52_errata_258(void) __UNUSED;
|
||||
static bool nrf52_errata_259(void) __UNUSED;
|
||||
static bool nrf52_errata_262(void) __UNUSED;
|
||||
|
||||
/* ========= Errata 1 ========= */
|
||||
|
@ -13658,6 +13659,88 @@ static bool nrf52_errata_258(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
/* ========= Errata 259 ========= */
|
||||
#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \
|
||||
|| defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \
|
||||
|| defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
|
||||
#define NRF52_ERRATA_259_PRESENT 1
|
||||
#else
|
||||
#define NRF52_ERRATA_259_PRESENT 0
|
||||
#endif
|
||||
|
||||
#ifndef NRF52_ERRATA_259_ENABLE_WORKAROUND
|
||||
#define NRF52_ERRATA_259_ENABLE_WORKAROUND NRF52_ERRATA_259_PRESENT
|
||||
#endif
|
||||
|
||||
static bool nrf52_errata_259(void)
|
||||
{
|
||||
#ifndef NRF52_SERIES
|
||||
return false;
|
||||
#else
|
||||
#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
|
||||
|| defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
|
||||
|| defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
|
||||
uint32_t var1 = *(uint32_t *)0x10000130ul;
|
||||
uint32_t var2 = *(uint32_t *)0x10000134ul;
|
||||
#endif
|
||||
#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
|
||||
if (var1 == 0x08)
|
||||
{
|
||||
switch(var2)
|
||||
{
|
||||
case 0x00ul:
|
||||
return true;
|
||||
case 0x01ul:
|
||||
return true;
|
||||
case 0x02ul:
|
||||
return true;
|
||||
case 0x03ul:
|
||||
return true;
|
||||
case 0x04ul:
|
||||
return true;
|
||||
case 0x05ul:
|
||||
return true;
|
||||
default:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)
|
||||
if (var1 == 0x0D)
|
||||
{
|
||||
switch(var2)
|
||||
{
|
||||
case 0x00ul:
|
||||
return true;
|
||||
case 0x01ul:
|
||||
return true;
|
||||
default:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)
|
||||
if (var1 == 0x10)
|
||||
{
|
||||
switch(var2)
|
||||
{
|
||||
case 0x00ul:
|
||||
return true;
|
||||
case 0x01ul:
|
||||
return true;
|
||||
case 0x02ul:
|
||||
return true;
|
||||
case 0x03ul:
|
||||
return true;
|
||||
default:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ========= Errata 262 ========= */
|
||||
#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \
|
||||
|| defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \
|
||||
|
|
|
@ -1,28 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.SPDX-License-Identifier: BSD
|
||||
* -3-ClauseRedistribution and use in source and binary forms, with or withoutmodification, are permitt
|
||||
* ed provided that the following conditions are met:1. Redistributions of source code must retain the
|
||||
* above copyright notice, this list of conditions and the following disclaimer.2. Redistributions in b
|
||||
* inary form must reproduce the above copyright notice, this list of conditions and the following disc
|
||||
* laimer in the documentation and/or other materials provided with the distribution.3. Neither the nam
|
||||
* e of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote pr
|
||||
* oducts derived from this software without specific prior written permission.THIS SOFTWARE IS PROVIDE
|
||||
* D BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
|
||||
* BUT NOT LIMITED TO, THEIMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSEA
|
||||
* RE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BELIABLE FOR ANY DIRECT, I
|
||||
* NDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, ORCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PRO
|
||||
* CUREMENT OFSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESSINTERRUPTION) HOW
|
||||
* EVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER INCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEP
|
||||
* OSSIBILITY OF SUCH DAMAGE.
|
||||
Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* @file nrf5340_application.h
|
||||
* @brief CMSIS HeaderFile
|
||||
* @version 1
|
||||
* @date 11. May 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:45
|
||||
* @date 19. October 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:24:00
|
||||
* from File 'nrf5340_application.svd',
|
||||
* last modified on Wednesday, 11.05.2022 10:25:34
|
||||
* last modified on Wednesday, 19.10.2022 09:13:55
|
||||
*/
|
||||
|
||||
|
||||
|
@ -122,6 +135,7 @@ typedef enum {
|
|||
|
||||
/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */
|
||||
#define __CM33_REV 0x0004U /*!< CM33 Core Revision */
|
||||
#define __INTERRUPTS_MAX 240 /*!< Top interrupt number */
|
||||
#define __DSP_PRESENT 1 /*!< DSP present or not */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
|
|
@ -54,7 +54,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
<deviceNumInterrupts>69</deviceNumInterrupts>
|
||||
<sauNumRegions>0</sauNumRegions>
|
||||
</cpu>
|
||||
<headerSystemFilename>system_nrf5340_application</headerSystemFilename>
|
||||
<headerSystemFilename>system_nrf53</headerSystemFilename>
|
||||
<headerDefinitionsPrefix>NRF_</headerDefinitionsPrefix>
|
||||
<vendorExtensions>
|
||||
<MaxInterrupts>240</MaxInterrupts>
|
||||
|
@ -40335,7 +40335,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
<fields>
|
||||
<field>
|
||||
<name>SCKDELAY</name>
|
||||
<description>Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns).</description>
|
||||
<description>Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 32 MHz periods (31.25 ns).</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>7</msb>
|
||||
</field>
|
||||
|
@ -40442,13 +40442,13 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
<fields>
|
||||
<field>
|
||||
<name>ENTER</name>
|
||||
<description>Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns.</description>
|
||||
<description>Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 31.25 ns</description>
|
||||
<lsb>0</lsb>
|
||||
<msb>15</msb>
|
||||
</field>
|
||||
<field>
|
||||
<name>EXIT</name>
|
||||
<description>Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns.</description>
|
||||
<description>Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 31.25 ns.</description>
|
||||
<lsb>16</lsb>
|
||||
<msb>31</msb>
|
||||
</field>
|
||||
|
|
|
@ -10555,7 +10555,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
#define QSPI_IFCONFIG1_DPMEN_Exit (0UL) /*!< Exit DPM. */
|
||||
#define QSPI_IFCONFIG1_DPMEN_Enter (1UL) /*!< Enter DPM. */
|
||||
|
||||
/* Bits 7..0 : Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). */
|
||||
/* Bits 7..0 : Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 32 MHz periods (31.25 ns). */
|
||||
#define QSPI_IFCONFIG1_SCKDELAY_Pos (0UL) /*!< Position of SCKDELAY field. */
|
||||
#define QSPI_IFCONFIG1_SCKDELAY_Msk (0xFFUL << QSPI_IFCONFIG1_SCKDELAY_Pos) /*!< Bit mask of SCKDELAY field. */
|
||||
|
||||
|
@ -10581,11 +10581,11 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
/* Register: QSPI_DPMDUR */
|
||||
/* Description: Set the duration required to enter/exit deep power-down mode (DPM). */
|
||||
|
||||
/* Bits 31..16 : Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. */
|
||||
/* Bits 31..16 : Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 31.25 ns. */
|
||||
#define QSPI_DPMDUR_EXIT_Pos (16UL) /*!< Position of EXIT field. */
|
||||
#define QSPI_DPMDUR_EXIT_Msk (0xFFFFUL << QSPI_DPMDUR_EXIT_Pos) /*!< Bit mask of EXIT field. */
|
||||
|
||||
/* Bits 15..0 : Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. */
|
||||
/* Bits 15..0 : Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 31.25 ns */
|
||||
#define QSPI_DPMDUR_ENTER_Pos (0UL) /*!< Position of ENTER field. */
|
||||
#define QSPI_DPMDUR_ENTER_Msk (0xFFFFUL << QSPI_DPMDUR_ENTER_Pos) /*!< Bit mask of ENTER field. */
|
||||
|
||||
|
|
|
@ -52,6 +52,12 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
#define SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler SERIAL3_IRQHandler
|
||||
#define SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn SERIAL3_IRQn
|
||||
|
||||
/* DPPI */
|
||||
#define DPPI_PRESENT DPPIC_PRESENT
|
||||
#define DPPI_COUNT DPPIC_COUNT
|
||||
#define DPPI_CH_NUM DPPIC_CH_NUM
|
||||
#define DPPI_GROUP_NUM DPPIC_GROUP_NUM
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF5340_APPLICATION_NAME_CHANGE_H */
|
||||
|
|
|
@ -107,11 +107,11 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
#define NFCT_EASYDMA_MAXCNT_SIZE 9
|
||||
|
||||
/* Distributed Peripheral to Peripheral Interconnect */
|
||||
#define DPPI_PRESENT
|
||||
#define DPPI_COUNT 1
|
||||
#define DPPIC_PRESENT
|
||||
#define DPPIC_COUNT 1
|
||||
|
||||
#define DPPI_CH_NUM 32
|
||||
#define DPPI_GROUP_NUM 6
|
||||
#define DPPIC_CH_NUM 32
|
||||
#define DPPIC_GROUP_NUM 6
|
||||
|
||||
/* Event Generator Unit */
|
||||
#define EGU_PRESENT
|
||||
|
|
|
@ -1,28 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.SPDX-License-Identifier: BSD
|
||||
* -3-ClauseRedistribution and use in source and binary forms, with or withoutmodification, are permitt
|
||||
* ed provided that the following conditions are met:1. Redistributions of source code must retain the
|
||||
* above copyright notice, this list of conditions and the following disclaimer.2. Redistributions in b
|
||||
* inary form must reproduce the above copyright notice, this list of conditions and the following disc
|
||||
* laimer in the documentation and/or other materials provided with the distribution.3. Neither the nam
|
||||
* e of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote pr
|
||||
* oducts derived from this software without specific prior written permission.THIS SOFTWARE IS PROVIDE
|
||||
* D BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
|
||||
* BUT NOT LIMITED TO, THEIMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSEA
|
||||
* RE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BELIABLE FOR ANY DIRECT, I
|
||||
* NDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, ORCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PRO
|
||||
* CUREMENT OFSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESSINTERRUPTION) HOW
|
||||
* EVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER INCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEP
|
||||
* OSSIBILITY OF SUCH DAMAGE.
|
||||
Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* @file nrf5340_network.h
|
||||
* @brief CMSIS HeaderFile
|
||||
* @version 1
|
||||
* @date 11. May 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:54
|
||||
* @date 19. October 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:24:09
|
||||
* from File 'nrf5340_network.svd',
|
||||
* last modified on Wednesday, 11.05.2022 10:25:34
|
||||
* last modified on Wednesday, 19.10.2022 09:13:55
|
||||
*/
|
||||
|
||||
|
||||
|
@ -101,6 +114,7 @@ typedef enum {
|
|||
|
||||
/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */
|
||||
#define __CM33_REV 0x0004U /*!< CM33 Core Revision */
|
||||
#define __INTERRUPTS_MAX 129 /*!< Top interrupt number */
|
||||
#define __DSP_PRESENT 0 /*!< DSP present or not */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
|
|
@ -54,7 +54,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
<deviceNumInterrupts>30</deviceNumInterrupts>
|
||||
<sauNumRegions>0</sauNumRegions>
|
||||
</cpu>
|
||||
<headerSystemFilename>system_nrf5340_network</headerSystemFilename>
|
||||
<headerSystemFilename>system_nrf53</headerSystemFilename>
|
||||
<headerDefinitionsPrefix>NRF_</headerDefinitionsPrefix>
|
||||
<vendorExtensions>
|
||||
<MaxInterrupts>129</MaxInterrupts>
|
||||
|
|
|
@ -46,6 +46,12 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler SERIAL0_IRQHandler
|
||||
#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn SERIAL0_IRQn
|
||||
|
||||
/* DPPI */
|
||||
#define DPPI_PRESENT DPPIC_PRESENT
|
||||
#define DPPI_COUNT DPPIC_COUNT
|
||||
#define DPPI_CH_NUM DPPIC_CH_NUM
|
||||
#define DPPI_GROUP_NUM DPPIC_GROUP_NUM
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF5340_NETWORK_NAME_CHANGE_H */
|
||||
|
|
|
@ -112,11 +112,11 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
#define CCM_COUNT 1
|
||||
|
||||
/* Distributed Peripheral to Peripheral Interconnect */
|
||||
#define DPPI_PRESENT
|
||||
#define DPPI_COUNT 1
|
||||
#define DPPIC_PRESENT
|
||||
#define DPPIC_COUNT 1
|
||||
|
||||
#define DPPI_CH_NUM 32
|
||||
#define DPPI_GROUP_NUM 6
|
||||
#define DPPIC_CH_NUM 32
|
||||
#define DPPIC_GROUP_NUM 6
|
||||
|
||||
/* Event Generator Unit */
|
||||
#define EGU_PRESENT
|
||||
|
|
|
@ -139,6 +139,9 @@ static bool nrf53_errata_136(void) __UNUSED;
|
|||
static bool nrf53_errata_137(void) __UNUSED;
|
||||
static bool nrf53_errata_138(void) __UNUSED;
|
||||
static bool nrf53_errata_140(void) __UNUSED;
|
||||
static bool nrf53_errata_152(void) __UNUSED;
|
||||
static bool nrf53_errata_153(void) __UNUSED;
|
||||
static bool nrf53_errata_154(void) __UNUSED;
|
||||
|
||||
/* ========= Errata 1 ========= */
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
|
@ -5178,7 +5181,15 @@ static bool nrf53_errata_122(void)
|
|||
}
|
||||
|
||||
/* ========= Errata 133 ========= */
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION)
|
||||
#define NRF53_ERRATA_133_PRESENT 1
|
||||
#else
|
||||
#define NRF53_ERRATA_133_PRESENT 0
|
||||
#endif
|
||||
#else
|
||||
#define NRF53_ERRATA_133_PRESENT 0
|
||||
#endif
|
||||
|
||||
#ifndef NRF53_ERRATA_133_ENABLE_WORKAROUND
|
||||
#define NRF53_ERRATA_133_ENABLE_WORKAROUND NRF53_ERRATA_133_PRESENT
|
||||
|
@ -5189,12 +5200,51 @@ static bool nrf53_errata_133(void)
|
|||
#ifndef NRF53_SERIES
|
||||
return false;
|
||||
#else
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION)
|
||||
#if defined(NRF_TRUSTZONE_NONSECURE)
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
|
||||
#else
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined (NRF_APPLICATION)
|
||||
if (var1 == 0x07)
|
||||
{
|
||||
switch(var2)
|
||||
{
|
||||
case 0x02ul:
|
||||
return false;
|
||||
case 0x03ul:
|
||||
return false;
|
||||
case 0x04ul:
|
||||
return false;
|
||||
case 0x05ul:
|
||||
return true;
|
||||
default:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ========= Errata 134 ========= */
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_NETWORK)
|
||||
#define NRF53_ERRATA_134_PRESENT 1
|
||||
#else
|
||||
#define NRF53_ERRATA_134_PRESENT 0
|
||||
#endif
|
||||
#else
|
||||
#define NRF53_ERRATA_134_PRESENT 0
|
||||
#endif
|
||||
|
||||
#ifndef NRF53_ERRATA_134_ENABLE_WORKAROUND
|
||||
#define NRF53_ERRATA_134_ENABLE_WORKAROUND NRF53_ERRATA_134_PRESENT
|
||||
|
@ -5205,12 +5255,47 @@ static bool nrf53_errata_134(void)
|
|||
#ifndef NRF53_SERIES
|
||||
return false;
|
||||
#else
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_NETWORK)
|
||||
uint32_t var1 = *(uint32_t *)0x01FF0130ul;
|
||||
uint32_t var2 = *(uint32_t *)0x01FF0134ul;
|
||||
#endif
|
||||
#endif
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined (NRF_NETWORK)
|
||||
if (var1 == 0x07)
|
||||
{
|
||||
switch(var2)
|
||||
{
|
||||
case 0x02ul:
|
||||
return false;
|
||||
case 0x03ul:
|
||||
return false;
|
||||
case 0x04ul:
|
||||
return false;
|
||||
case 0x05ul:
|
||||
return true;
|
||||
default:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ========= Errata 135 ========= */
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION) || \
|
||||
defined(NRF_NETWORK)
|
||||
#define NRF53_ERRATA_135_PRESENT 1
|
||||
#else
|
||||
#define NRF53_ERRATA_135_PRESENT 0
|
||||
#endif
|
||||
#else
|
||||
#define NRF53_ERRATA_135_PRESENT 0
|
||||
#endif
|
||||
|
||||
#ifndef NRF53_ERRATA_135_ENABLE_WORKAROUND
|
||||
#define NRF53_ERRATA_135_ENABLE_WORKAROUND NRF53_ERRATA_135_PRESENT
|
||||
|
@ -5221,12 +5306,55 @@ static bool nrf53_errata_135(void)
|
|||
#ifndef NRF53_SERIES
|
||||
return false;
|
||||
#else
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION)
|
||||
#if defined(NRF_TRUSTZONE_NONSECURE)
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
|
||||
#else
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
|
||||
#endif
|
||||
#elif defined(NRF_NETWORK)
|
||||
uint32_t var1 = *(uint32_t *)0x01FF0130ul;
|
||||
uint32_t var2 = *(uint32_t *)0x01FF0134ul;
|
||||
#endif
|
||||
#endif
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined (NRF_APPLICATION)\
|
||||
|| defined (NRF_NETWORK)
|
||||
if (var1 == 0x07)
|
||||
{
|
||||
switch(var2)
|
||||
{
|
||||
case 0x02ul:
|
||||
return false;
|
||||
case 0x03ul:
|
||||
return false;
|
||||
case 0x04ul:
|
||||
return false;
|
||||
case 0x05ul:
|
||||
return true;
|
||||
default:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ========= Errata 136 ========= */
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION)
|
||||
#define NRF53_ERRATA_136_PRESENT 1
|
||||
#else
|
||||
#define NRF53_ERRATA_136_PRESENT 0
|
||||
#endif
|
||||
#else
|
||||
#define NRF53_ERRATA_136_PRESENT 0
|
||||
#endif
|
||||
|
||||
#ifndef NRF53_ERRATA_136_ENABLE_WORKAROUND
|
||||
#define NRF53_ERRATA_136_ENABLE_WORKAROUND NRF53_ERRATA_136_PRESENT
|
||||
|
@ -5237,12 +5365,52 @@ static bool nrf53_errata_136(void)
|
|||
#ifndef NRF53_SERIES
|
||||
return false;
|
||||
#else
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION)
|
||||
#if defined(NRF_TRUSTZONE_NONSECURE)
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
|
||||
#else
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined (NRF_APPLICATION)
|
||||
if (var1 == 0x07)
|
||||
{
|
||||
switch(var2)
|
||||
{
|
||||
case 0x02ul:
|
||||
return false;
|
||||
case 0x03ul:
|
||||
return false;
|
||||
case 0x04ul:
|
||||
return false;
|
||||
case 0x05ul:
|
||||
return true;
|
||||
default:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ========= Errata 137 ========= */
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION) || \
|
||||
defined(NRF_NETWORK)
|
||||
#define NRF53_ERRATA_137_PRESENT 1
|
||||
#else
|
||||
#define NRF53_ERRATA_137_PRESENT 0
|
||||
#endif
|
||||
#else
|
||||
#define NRF53_ERRATA_137_PRESENT 0
|
||||
#endif
|
||||
|
||||
#ifndef NRF53_ERRATA_137_ENABLE_WORKAROUND
|
||||
#define NRF53_ERRATA_137_ENABLE_WORKAROUND NRF53_ERRATA_137_PRESENT
|
||||
|
@ -5253,12 +5421,55 @@ static bool nrf53_errata_137(void)
|
|||
#ifndef NRF53_SERIES
|
||||
return false;
|
||||
#else
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION)
|
||||
#if defined(NRF_TRUSTZONE_NONSECURE)
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
|
||||
#else
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
|
||||
#endif
|
||||
#elif defined(NRF_NETWORK)
|
||||
uint32_t var1 = *(uint32_t *)0x01FF0130ul;
|
||||
uint32_t var2 = *(uint32_t *)0x01FF0134ul;
|
||||
#endif
|
||||
#endif
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined (NRF_APPLICATION)\
|
||||
|| defined (NRF_NETWORK)
|
||||
if (var1 == 0x07)
|
||||
{
|
||||
switch(var2)
|
||||
{
|
||||
case 0x02ul:
|
||||
return false;
|
||||
case 0x03ul:
|
||||
return false;
|
||||
case 0x04ul:
|
||||
return false;
|
||||
case 0x05ul:
|
||||
return true;
|
||||
default:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ========= Errata 138 ========= */
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION)
|
||||
#define NRF53_ERRATA_138_PRESENT 1
|
||||
#else
|
||||
#define NRF53_ERRATA_138_PRESENT 0
|
||||
#endif
|
||||
#else
|
||||
#define NRF53_ERRATA_138_PRESENT 0
|
||||
#endif
|
||||
|
||||
#ifndef NRF53_ERRATA_138_ENABLE_WORKAROUND
|
||||
#define NRF53_ERRATA_138_ENABLE_WORKAROUND NRF53_ERRATA_138_PRESENT
|
||||
|
@ -5269,6 +5480,37 @@ static bool nrf53_errata_138(void)
|
|||
#ifndef NRF53_SERIES
|
||||
return false;
|
||||
#else
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION)
|
||||
#if defined(NRF_TRUSTZONE_NONSECURE)
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
|
||||
#else
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined (NRF_APPLICATION)
|
||||
if (var1 == 0x07)
|
||||
{
|
||||
switch(var2)
|
||||
{
|
||||
case 0x02ul:
|
||||
return false;
|
||||
case 0x03ul:
|
||||
return false;
|
||||
case 0x04ul:
|
||||
return false;
|
||||
case 0x05ul:
|
||||
return true;
|
||||
default:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
@ -5328,4 +5570,179 @@ static bool nrf53_errata_140(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
/* ========= Errata 152 ========= */
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION) || \
|
||||
defined(NRF_NETWORK)
|
||||
#define NRF53_ERRATA_152_PRESENT 1
|
||||
#else
|
||||
#define NRF53_ERRATA_152_PRESENT 0
|
||||
#endif
|
||||
#else
|
||||
#define NRF53_ERRATA_152_PRESENT 0
|
||||
#endif
|
||||
|
||||
#ifndef NRF53_ERRATA_152_ENABLE_WORKAROUND
|
||||
#define NRF53_ERRATA_152_ENABLE_WORKAROUND NRF53_ERRATA_152_PRESENT
|
||||
#endif
|
||||
|
||||
static bool nrf53_errata_152(void)
|
||||
{
|
||||
#ifndef NRF53_SERIES
|
||||
return false;
|
||||
#else
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION)
|
||||
#if defined(NRF_TRUSTZONE_NONSECURE)
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
|
||||
#else
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
|
||||
#endif
|
||||
#elif defined(NRF_NETWORK)
|
||||
uint32_t var1 = *(uint32_t *)0x01FF0130ul;
|
||||
uint32_t var2 = *(uint32_t *)0x01FF0134ul;
|
||||
#endif
|
||||
#endif
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined (NRF_APPLICATION)\
|
||||
|| defined (NRF_NETWORK)
|
||||
if (var1 == 0x07)
|
||||
{
|
||||
switch(var2)
|
||||
{
|
||||
case 0x02ul:
|
||||
return false;
|
||||
case 0x03ul:
|
||||
return false;
|
||||
case 0x04ul:
|
||||
return false;
|
||||
case 0x05ul:
|
||||
return true;
|
||||
default:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ========= Errata 153 ========= */
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION)
|
||||
#define NRF53_ERRATA_153_PRESENT 1
|
||||
#else
|
||||
#define NRF53_ERRATA_153_PRESENT 0
|
||||
#endif
|
||||
#else
|
||||
#define NRF53_ERRATA_153_PRESENT 0
|
||||
#endif
|
||||
|
||||
#ifndef NRF53_ERRATA_153_ENABLE_WORKAROUND
|
||||
#define NRF53_ERRATA_153_ENABLE_WORKAROUND NRF53_ERRATA_153_PRESENT
|
||||
#endif
|
||||
|
||||
static bool nrf53_errata_153(void)
|
||||
{
|
||||
#ifndef NRF53_SERIES
|
||||
return false;
|
||||
#else
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION)
|
||||
#if defined(NRF_TRUSTZONE_NONSECURE)
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
|
||||
#else
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined (NRF_APPLICATION)
|
||||
if (var1 == 0x07)
|
||||
{
|
||||
switch(var2)
|
||||
{
|
||||
case 0x02ul:
|
||||
return false;
|
||||
case 0x03ul:
|
||||
return false;
|
||||
case 0x04ul:
|
||||
return false;
|
||||
case 0x05ul:
|
||||
return true;
|
||||
default:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ========= Errata 154 ========= */
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION) || \
|
||||
defined(NRF_NETWORK)
|
||||
#define NRF53_ERRATA_154_PRESENT 1
|
||||
#else
|
||||
#define NRF53_ERRATA_154_PRESENT 0
|
||||
#endif
|
||||
#else
|
||||
#define NRF53_ERRATA_154_PRESENT 0
|
||||
#endif
|
||||
|
||||
#ifndef NRF53_ERRATA_154_ENABLE_WORKAROUND
|
||||
#define NRF53_ERRATA_154_ENABLE_WORKAROUND NRF53_ERRATA_154_PRESENT
|
||||
#endif
|
||||
|
||||
static bool nrf53_errata_154(void)
|
||||
{
|
||||
#ifndef NRF53_SERIES
|
||||
return false;
|
||||
#else
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined(NRF_APPLICATION)
|
||||
#if defined(NRF_TRUSTZONE_NONSECURE)
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
|
||||
#else
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
|
||||
#endif
|
||||
#elif defined(NRF_NETWORK)
|
||||
uint32_t var1 = *(uint32_t *)0x01FF0130ul;
|
||||
uint32_t var2 = *(uint32_t *)0x01FF0134ul;
|
||||
#endif
|
||||
#endif
|
||||
#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
|
||||
#if defined (NRF_APPLICATION)\
|
||||
|| defined (NRF_NETWORK)
|
||||
if (var1 == 0x07)
|
||||
{
|
||||
switch(var2)
|
||||
{
|
||||
case 0x02ul:
|
||||
return false;
|
||||
case 0x03ul:
|
||||
return false;
|
||||
case 0x04ul:
|
||||
return false;
|
||||
case 0x05ul:
|
||||
return true;
|
||||
default:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* NRF53_ERRATAS_H */
|
||||
|
|
|
@ -1,41 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* @file nrf9160.h
|
||||
* @brief CMSIS HeaderFile
|
||||
* @version 1
|
||||
* @date 11. May 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:55
|
||||
* @date 19. October 2022
|
||||
* @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:24:10
|
||||
* from File 'nrf9160.svd',
|
||||
* last modified on Wednesday, 11.05.2022 10:25:34
|
||||
* last modified on Wednesday, 19.10.2022 09:13:55
|
||||
*/
|
||||
|
||||
|
||||
|
@ -86,10 +86,10 @@ typedef enum {
|
|||
/* ========================================== nrf9160 Specific Interrupt Numbers =========================================== */
|
||||
SPU_IRQn = 3, /*!< 3 SPU */
|
||||
CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */
|
||||
UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn= 8, /*!< 8 UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 */
|
||||
UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQn= 9, /*!< 9 UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 */
|
||||
UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQn= 10, /*!< 10 UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 */
|
||||
UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQn= 11, /*!< 11 UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 */
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn= 8, /*!< 8 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 */
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn= 9, /*!< 9 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 */
|
||||
SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn= 10, /*!< 10 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 */
|
||||
SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn= 11, /*!< 11 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 */
|
||||
GPIOTE0_IRQn = 13, /*!< 13 GPIOTE0 */
|
||||
SAADC_IRQn = 14, /*!< 14 SAADC */
|
||||
TIMER0_IRQn = 15, /*!< 15 TIMER0 */
|
||||
|
@ -125,6 +125,7 @@ typedef enum {
|
|||
|
||||
/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */
|
||||
#define __CM33_REV 0x0004U /*!< CM33 Core Revision */
|
||||
#define __INTERRUPTS_MAX 240 /*!< Top interrupt number */
|
||||
#define __DSP_PRESENT 1 /*!< DSP present or not */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
@ -161,16 +162,25 @@ typedef enum {
|
|||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief FICR_SIPINFO [SIPINFO] (SIP-specific device info)
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t PARTNO; /*!< (@ 0x00000000) SIP part number */
|
||||
__IM uint8_t HWREVISION[4]; /*!< (@ 0x00000004) Description collection: SIP hardware revision,
|
||||
encoded in ASCII, ex B0A or B1A */
|
||||
__IM uint8_t VARIANT[4]; /*!< (@ 0x00000008) Description collection: SIP VARIANT, encoded
|
||||
in ASCII, ex SIAA, SIBA or SICA */
|
||||
} FICR_SIPINFO_Type; /*!< Size = 12 (0xc) */
|
||||
|
||||
|
||||
/**
|
||||
* @brief FICR_INFO [INFO] (Device info)
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t RESERVED;
|
||||
__IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */
|
||||
__IM uint32_t PART; /*!< (@ 0x0000000C) Part code */
|
||||
__IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production
|
||||
configuration */
|
||||
__IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */
|
||||
__IM uint32_t RESERVED1[3];
|
||||
__IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */
|
||||
__IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */
|
||||
__IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size */
|
||||
|
@ -210,11 +220,11 @@ typedef struct {
|
|||
__IOM uint32_t DEST; /*!< (@ 0x00000000) Description cluster: Destination address where
|
||||
content of the key value registers (KEYSLOT.KEYn.VALUE[0-3
|
||||
) will be pushed by KMU. Note that this
|
||||
address MUST match that of a peripherals
|
||||
address must match that of a peripherals
|
||||
APB mapped write-only key registers, else
|
||||
the KMU can push this key value into an
|
||||
address range which the CPU can potentially
|
||||
read! */
|
||||
read. */
|
||||
__IOM uint32_t PERM; /*!< (@ 0x00000004) Description cluster: Define permissions for the
|
||||
key slot. Bits 0-15 and 16-31 can only be
|
||||
written when equal to 0xFFFF. */
|
||||
|
@ -243,11 +253,11 @@ typedef struct {
|
|||
* @brief TAD_PSEL [PSEL] (Unspecified)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin number configuration for TRACECLK */
|
||||
__IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin number configuration for TRACEDATA[0] */
|
||||
__IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin number configuration for TRACEDATA[1] */
|
||||
__IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin number configuration for TRACEDATA[2] */
|
||||
__IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin number configuration for TRACEDATA[3] */
|
||||
__IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin configuration for TRACECLK */
|
||||
__IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin configuration for TRACEDATA[0] */
|
||||
__IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin configuration for TRACEDATA[1] */
|
||||
__IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin configuration for TRACEDATA[2] */
|
||||
__IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin configuration for TRACEDATA[3] */
|
||||
} TAD_PSEL_Type; /*!< Size = 20 (0x14) */
|
||||
|
||||
|
||||
|
@ -335,17 +345,28 @@ typedef struct {
|
|||
} SPU_PERIPHID_Type; /*!< Size = 4 (0x4) */
|
||||
|
||||
|
||||
/**
|
||||
* @brief POWER_LTEMODEM [LTEMODEM] (LTE Modem)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t STARTN; /*!< (@ 0x00000000) Start LTE modem */
|
||||
__IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force off LTE modem */
|
||||
} POWER_LTEMODEM_Type; /*!< Size = 8 (0x8) */
|
||||
|
||||
|
||||
/**
|
||||
* @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified)
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU */
|
||||
__IM uint32_t RXSTATUS; /*!< (@ 0x00000004) Status to indicate if data sent from the debugger
|
||||
to the CPU has been read */
|
||||
__IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */
|
||||
__IM uint32_t RXSTATUS; /*!< (@ 0x00000004) This register shows a status that indicates if
|
||||
data sent from the debugger to the CPU has
|
||||
been read. */
|
||||
__IM uint32_t RESERVED[30];
|
||||
__IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger */
|
||||
__IM uint32_t TXSTATUS; /*!< (@ 0x00000084) Status to indicate if data sent from the CPU
|
||||
to the debugger has been read */
|
||||
__IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */
|
||||
__IM uint32_t TXSTATUS; /*!< (@ 0x00000084) This register shows a status that indicates if
|
||||
the data sent from the CPU to the debugger
|
||||
has been read. */
|
||||
} CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */
|
||||
|
||||
|
||||
|
@ -353,9 +374,10 @@ typedef struct {
|
|||
* @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t LOCK; /*!< (@ 0x00000000) Lock register ERASEPROTECT.DISABLE from being
|
||||
written until next reset */
|
||||
__IOM uint32_t DISABLE; /*!< (@ 0x00000004) Disable ERASEPROTECT and perform ERASEALL */
|
||||
__IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE
|
||||
register from being written until next reset. */
|
||||
__IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register
|
||||
and performs an ERASEALL operation. */
|
||||
} CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */
|
||||
|
||||
|
||||
|
@ -719,11 +741,13 @@ typedef struct {
|
|||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */
|
||||
__IM uint32_t RESERVED[128];
|
||||
__IM uint32_t RESERVED[80];
|
||||
__IOM FICR_SIPINFO_Type SIPINFO; /*!< (@ 0x00000140) SIP-specific device info */
|
||||
__IM uint32_t RESERVED1[45];
|
||||
__IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */
|
||||
__IM uint32_t RESERVED1[53];
|
||||
__IM uint32_t RESERVED2[53];
|
||||
__IOM FICR_TRIMCNF_Type TRIMCNF[256]; /*!< (@ 0x00000300) Unspecified */
|
||||
__IM uint32_t RESERVED2[64];
|
||||
__IM uint32_t RESERVED3[64];
|
||||
__IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */
|
||||
} NRF_FICR_Type; /*!< Size = 3104 (0xc20) */
|
||||
|
||||
|
@ -745,7 +769,10 @@ typedef struct { /*!< (@ 0x00FF8000) UICR_S Struc
|
|||
__IM uint32_t RESERVED1;
|
||||
__IOM uint32_t HFXOSRC; /*!< (@ 0x0000001C) HFXO clock source selection */
|
||||
__IOM uint32_t HFXOCNT; /*!< (@ 0x00000020) HFXO startup counter */
|
||||
__IM uint32_t RESERVED2[2];
|
||||
__IOM uint32_t APPNVMCPOFGUARD; /*!< (@ 0x00000024) Enable blocking NVM WRITE and aborting NVM ERASE
|
||||
for Application NVM in POFWARN condition
|
||||
. */
|
||||
__IM uint32_t RESERVED2;
|
||||
__IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000002C) Secure access port protection */
|
||||
__IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000030) Erase protection */
|
||||
__IM uint32_t RESERVED3[53];
|
||||
|
@ -766,12 +793,13 @@ typedef struct { /*!< (@ 0x00FF8000) UICR_S Struc
|
|||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0xE0080000) TAD_S Structure */
|
||||
__OM uint32_t CLOCKSTART; /*!< (@ 0x00000000) Start all trace and debug clocks. */
|
||||
__OM uint32_t CLOCKSTOP; /*!< (@ 0x00000004) Stop all trace and debug clocks. */
|
||||
__OM uint32_t TASKS_CLOCKSTART; /*!< (@ 0x00000000) Start all trace and debug clocks. */
|
||||
__OM uint32_t TASKS_CLOCKSTOP; /*!< (@ 0x00000004) Stop all trace and debug clocks. */
|
||||
__IM uint32_t RESERVED[318];
|
||||
__IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */
|
||||
__IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */
|
||||
__IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface */
|
||||
__IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface
|
||||
Reset behavior is the same as debug components */
|
||||
} NRF_TAD_Type; /*!< Size = 1308 (0x51c) */
|
||||
|
||||
|
||||
|
@ -835,7 +863,9 @@ typedef struct { /*!< (@ 0x50003000) SPU_S Struct
|
|||
typedef struct { /*!< (@ 0x40004000) REGULATORS_NS Structure */
|
||||
__IM uint32_t RESERVED[320];
|
||||
__OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */
|
||||
__IM uint32_t RESERVED1[29];
|
||||
__IM uint32_t RESERVED1[4];
|
||||
__IOM uint32_t EXTPOFCON; /*!< (@ 0x00000514) External power failure warning configuration */
|
||||
__IM uint32_t RESERVED2[24];
|
||||
__IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC mode of the main voltage regulator. */
|
||||
} NRF_REGULATORS_Type; /*!< Size = 1404 (0x57c) */
|
||||
|
||||
|
@ -931,7 +961,9 @@ typedef struct { /*!< (@ 0x40005000) POWER_NS Str
|
|||
__IM uint32_t RESERVED9[54];
|
||||
__IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention
|
||||
register */
|
||||
} NRF_POWER_Type; /*!< Size = 1316 (0x524) */
|
||||
__IM uint32_t RESERVED10[59];
|
||||
__IOM POWER_LTEMODEM_Type LTEMODEM; /*!< (@ 0x00000610) LTE Modem */
|
||||
} NRF_POWER_Type; /*!< Size = 1560 (0x618) */
|
||||
|
||||
|
||||
|
||||
|
@ -1289,8 +1321,8 @@ typedef struct { /*!< (@ 0x40008000) UARTE0_NS St
|
|||
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
|
||||
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
|
||||
__IM uint32_t RESERVED17[93];
|
||||
__IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write
|
||||
one to clear. */
|
||||
__IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one
|
||||
to clear. */
|
||||
__IM uint32_t RESERVED18[31];
|
||||
__IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */
|
||||
__IM uint32_t RESERVED19;
|
||||
|
@ -1351,7 +1383,7 @@ typedef struct { /*!< (@ 0x5000D000) GPIOTE0_S St
|
|||
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
|
||||
__IM uint32_t RESERVED7[129];
|
||||
__IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n],
|
||||
SET[n] and CLR[n] tasks and IN[n] event */
|
||||
SET[n], and CLR[n] tasks and IN[n] event */
|
||||
} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */
|
||||
|
||||
|
||||
|
@ -1527,7 +1559,7 @@ typedef struct { /*!< (@ 0x40014000) RTC0_NS Stru
|
|||
|
||||
|
||||
/**
|
||||
* @brief Distributed Programmable Peripheral Interconnect Controller 0 (DPPIC_NS)
|
||||
* @brief Distributed programmable peripheral interconnect controller 0 (DPPIC_NS)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x40017000) DPPIC_NS Structure */
|
||||
|
@ -1540,8 +1572,9 @@ typedef struct { /*!< (@ 0x40017000) DPPIC_NS Str
|
|||
__IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */
|
||||
__IM uint32_t RESERVED2[189];
|
||||
__IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note:
|
||||
Writes to this register is ignored if either
|
||||
SUBSCRIBE_CHG[n].EN/DIS are enabled. */
|
||||
Writes to this register are ignored if either
|
||||
SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS
|
||||
is enabled */
|
||||
} NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */
|
||||
|
||||
|
||||
|
@ -1785,18 +1818,18 @@ typedef struct { /*!< (@ 0x40028000) I2S_NS Struc
|
|||
|
||||
|
||||
/**
|
||||
* @brief Inter Processor Communication 0 (IPC_NS)
|
||||
* @brief Interprocessor communication 0 (IPC_NS)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x4002A000) IPC_NS Structure */
|
||||
__OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger events on channel
|
||||
enabled in SEND_CNF[n]. */
|
||||
__OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger events on IPC
|
||||
channel enabled in SEND_CNF[n] */
|
||||
__IM uint32_t RESERVED[24];
|
||||
__IOM uint32_t SUBSCRIBE_SEND[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration
|
||||
for task SEND[n] */
|
||||
__IM uint32_t RESERVED1[24];
|
||||
__IOM uint32_t EVENTS_RECEIVE[8]; /*!< (@ 0x00000100) Description collection: Event received on one
|
||||
or more of the enabled channels in RECEIVE_CNF[n]. */
|
||||
or more of the enabled IPC channels in RECEIVE_CNF[n] */
|
||||
__IM uint32_t RESERVED2[24];
|
||||
__IOM uint32_t PUBLISH_RECEIVE[8]; /*!< (@ 0x00000180) Description collection: Publish configuration
|
||||
for event RECEIVE[n] */
|
||||
|
@ -1807,12 +1840,12 @@ typedef struct { /*!< (@ 0x4002A000) IPC_NS Struc
|
|||
__IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */
|
||||
__IM uint32_t RESERVED4[128];
|
||||
__IOM uint32_t SEND_CNF[8]; /*!< (@ 0x00000510) Description collection: Send event configuration
|
||||
for TASKS_SEND[n]. */
|
||||
for TASKS_SEND[n] */
|
||||
__IM uint32_t RESERVED5[24];
|
||||
__IOM uint32_t RECEIVE_CNF[8]; /*!< (@ 0x00000590) Description collection: Receive event configuration
|
||||
for EVENTS_RECEIVE[n]. */
|
||||
for EVENTS_RECEIVE[n] */
|
||||
__IM uint32_t RESERVED6[24];
|
||||
__IOM uint32_t GPMEM[4]; /*!< (@ 0x00000610) Description collection: General purpose memory. */
|
||||
__IOM uint32_t GPMEM[4]; /*!< (@ 0x00000610) Description collection: General purpose memory */
|
||||
} NRF_IPC_Type; /*!< Size = 1568 (0x620) */
|
||||
|
||||
|
||||
|
|
1436
nrfx/mdk/nrf9160.svd
1436
nrfx/mdk/nrf9160.svd
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -53,6 +53,27 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Unlocked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked
|
||||
#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Locked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked
|
||||
|
||||
/* DPPI */
|
||||
#define DPPI_PRESENT DPPIC_PRESENT
|
||||
#define DPPI_COUNT DPPIC_COUNT
|
||||
#define DPPI_CH_NUM DPPIC_CH_NUM
|
||||
#define DPPI_GROUP_NUM DPPIC_GROUP_NUM
|
||||
|
||||
/* Serial box enums */
|
||||
#define UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0
|
||||
#define UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1
|
||||
#define UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2
|
||||
#define UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3
|
||||
|
||||
/* TAD */
|
||||
|
||||
#define TAD_CLOCKSTART_START_Pos TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos
|
||||
#define TAD_CLOCKSTART_START_Msk TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk
|
||||
#define TAD_CLOCKSTART_START_Start TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Trigger
|
||||
#define TAD_CLOCKSTOP_STOP_Pos TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos
|
||||
#define TAD_CLOCKSTOP_STOP_Msk TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Msk
|
||||
#define TAD_CLOCKSTOP_STOP_Stop TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Trigger
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF9160_NAME_CHANGE_H */
|
||||
|
|
|
@ -61,11 +61,11 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||
|
||||
/* Distributed Peripheral to Peripheral Interconnect */
|
||||
#define DPPI_PRESENT
|
||||
#define DPPI_COUNT 1
|
||||
#define DPPIC_PRESENT
|
||||
#define DPPIC_COUNT 1
|
||||
|
||||
#define DPPI_CH_NUM 16
|
||||
#define DPPI_GROUP_NUM 6
|
||||
#define DPPIC_CH_NUM 16
|
||||
#define DPPIC_GROUP_NUM 6
|
||||
|
||||
/* Event Generator Unit */
|
||||
#define EGU_PRESENT
|
||||
|
|
|
@ -64,6 +64,7 @@ static bool nrf91_errata_30(void) __UNUSED;
|
|||
static bool nrf91_errata_31(void) __UNUSED;
|
||||
static bool nrf91_errata_32(void) __UNUSED;
|
||||
static bool nrf91_errata_33(void) __UNUSED;
|
||||
static bool nrf91_errata_35(void) __UNUSED;
|
||||
|
||||
/* ========= Errata 1 ========= */
|
||||
#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
|
||||
|
@ -1165,4 +1166,48 @@ static bool nrf91_errata_33(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
/* ========= Errata 35 ========= */
|
||||
#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
|
||||
#define NRF91_ERRATA_35_PRESENT 1
|
||||
#else
|
||||
#define NRF91_ERRATA_35_PRESENT 0
|
||||
#endif
|
||||
|
||||
#ifndef NRF91_ERRATA_35_ENABLE_WORKAROUND
|
||||
#define NRF91_ERRATA_35_ENABLE_WORKAROUND 0
|
||||
#endif
|
||||
|
||||
static bool nrf91_errata_35(void)
|
||||
{
|
||||
#ifndef NRF91_SERIES
|
||||
return false;
|
||||
#else
|
||||
#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
|
||||
#if defined(NRF_TRUSTZONE_NONSECURE)
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
|
||||
#else
|
||||
uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
|
||||
uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
|
||||
#endif
|
||||
#endif
|
||||
#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
|
||||
__DSB();
|
||||
if (var1 == 0x09)
|
||||
{
|
||||
switch(var2)
|
||||
{
|
||||
case 0x01ul:
|
||||
return true;
|
||||
case 0x02ul:
|
||||
return true;
|
||||
default:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* NRF91_ERRATAS_H */
|
||||
|
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
|
||||
Copyright (c) 2009-2022 ARM Limited. All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_NRF53_H
|
||||
#define SYSTEM_NRF53_H
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* SYSTEM_NRF53_H */
|
|
@ -28,7 +28,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
|||
#include "nrf.h"
|
||||
#include "nrf_peripherals.h"
|
||||
#include "nrf53_erratas.h"
|
||||
#include "system_nrf5340_application.h"
|
||||
#include "system_nrf53.h"
|
||||
#include "system_nrf53_approtect.h"
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
|
|
@ -27,7 +27,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
|||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
#include "nrf53_erratas.h"
|
||||
#include "system_nrf5340_network.h"
|
||||
#include "system_nrf53.h"
|
||||
#include "system_nrf53_approtect.h"
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
|
|
@ -0,0 +1,326 @@
|
|||
/*
|
||||
|
||||
Copyright (c) 2009-2022 ARM Limited. All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
*/
|
||||
|
||||
/* NOTE: Template files (including this one) are application specific and therefore expected to
|
||||
be copied into the application project folder prior to its use! */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
#include "nrf_peripherals.h"
|
||||
#include "nrf91_erratas.h"
|
||||
#include "system_nrf91.h"
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
||||
void SystemStoreFICRNS();
|
||||
|
||||
#define __SYSTEM_CLOCK (64000000UL) /*!< nRF91 Application core uses a fixed System Clock Frequency of 64MHz */
|
||||
|
||||
#define TRACE_PIN_CNF_VALUE ( (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | \
|
||||
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \
|
||||
(GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | \
|
||||
(GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | \
|
||||
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) )
|
||||
#define TRACE_TRACECLK_PIN (21)
|
||||
#define TRACE_TRACEDATA0_PIN (22)
|
||||
#define TRACE_TRACEDATA1_PIN (23)
|
||||
#define TRACE_TRACEDATA2_PIN (24)
|
||||
#define TRACE_TRACEDATA3_PIN (25)
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
|
||||
#elif defined ( __ICCARM__ )
|
||||
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK;
|
||||
#elif defined ( __GNUC__ )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
|
||||
#endif
|
||||
|
||||
/* Global values used used in Secure mode SystemInit. */
|
||||
#if !defined(NRF_TRUSTZONE_NONSECURE)
|
||||
/* Global values used by UICR erase fix algorithm. */
|
||||
static uint32_t uicr_erased_value;
|
||||
static uint32_t uicr_new_value;
|
||||
#endif
|
||||
|
||||
/* Errata are only handled in secure mode since they usually need access to FICR. */
|
||||
#if !defined(NRF_TRUSTZONE_NONSECURE)
|
||||
static bool uicr_HFXOSRC_erased(void);
|
||||
static bool uicr_HFXOCNT_erased(void);
|
||||
static bool is_empty_word(uint32_t const volatile * word);
|
||||
#endif
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
}
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if !defined(NRF_TRUSTZONE_NONSECURE)
|
||||
/* Perform Secure-mode initialization routines. */
|
||||
|
||||
/* Set all ARM SAU regions to NonSecure if TrustZone extensions are enabled.
|
||||
* Nordic SPU should handle Secure Attribution tasks */
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
|
||||
#endif
|
||||
|
||||
/* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/index.jsp */
|
||||
if (nrf91_errata_6()){
|
||||
NRF_POWER_S->EVENTS_SLEEPENTER = (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos);
|
||||
NRF_POWER_S->EVENTS_SLEEPEXIT = (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos);
|
||||
}
|
||||
|
||||
/* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/index.jsp */
|
||||
if (nrf91_errata_14()){
|
||||
*((volatile uint32_t *)0x50004A38) = 0x01ul;
|
||||
NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 15 "REGULATORS: LDO mode at startup" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/index.jsp */
|
||||
if (nrf91_errata_15()){
|
||||
NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 20 "RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/index.jsp */
|
||||
if (nrf91_errata_20()){
|
||||
*((volatile uint32_t *)0x5003AEE4) = 0xE;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 31 "XOSC32k Startup Failure" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/index.jsp */
|
||||
if (nrf91_errata_31()){
|
||||
*((volatile uint32_t *)0x5000470Cul) = 0x0;
|
||||
*((volatile uint32_t *)0x50004710ul) = 0x1;
|
||||
}
|
||||
|
||||
#if !defined(NRF_SKIP_FICR_NS_COPY_TO_RAM)
|
||||
SystemStoreFICRNS();
|
||||
#endif
|
||||
|
||||
/* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
|
||||
until one ADDR is not initialized. */
|
||||
|
||||
for (uint32_t index = 0; index < 256ul && !is_empty_word(&NRF_FICR_S->TRIMCNF[index].ADDR); index++){
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma diag_suppress=Pa082
|
||||
#endif
|
||||
*(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma diag_default=Pa082
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Set UICR->HFXOSRC and UICR->HFXOCNT to working defaults if UICR was erased */
|
||||
if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) {
|
||||
__DSB();
|
||||
/* Wait for pending NVMC operations to finish */
|
||||
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
|
||||
|
||||
/* Enable write mode in NVMC */
|
||||
NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen;
|
||||
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
|
||||
|
||||
if (uicr_HFXOSRC_erased()){
|
||||
/* Write default value to UICR->HFXOSRC */
|
||||
uicr_erased_value = NRF_UICR_S->HFXOSRC;
|
||||
uicr_new_value = (uicr_erased_value & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO;
|
||||
NRF_UICR_S->HFXOSRC = uicr_new_value;
|
||||
__DSB();
|
||||
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
|
||||
}
|
||||
|
||||
if (uicr_HFXOCNT_erased()){
|
||||
/* Write default value to UICR->HFXOCNT */
|
||||
uicr_erased_value = NRF_UICR_S->HFXOCNT;
|
||||
uicr_new_value = (uicr_erased_value & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20;
|
||||
NRF_UICR_S->HFXOCNT = uicr_new_value;
|
||||
__DSB();
|
||||
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
|
||||
}
|
||||
|
||||
/* Enable read mode in NVMC */
|
||||
NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren;
|
||||
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
|
||||
|
||||
/* Reset to apply clock select update */
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
|
||||
Specification to see which ones). */
|
||||
#if defined (ENABLE_TRACE)
|
||||
// Enable Trace And Debug peripheral
|
||||
NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk;
|
||||
NRF_TAD_S->TASKS_CLOCKSTART = TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk;
|
||||
|
||||
// Set up Trace pads SPU firewall
|
||||
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACECLK_PIN);
|
||||
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA0_PIN);
|
||||
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA1_PIN);
|
||||
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA2_PIN);
|
||||
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA3_PIN);
|
||||
|
||||
// Configure trace port pads
|
||||
NRF_P0_S->PIN_CNF[TRACE_TRACECLK_PIN] = TRACE_PIN_CNF_VALUE;
|
||||
NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE;
|
||||
NRF_P0_S->PIN_CNF[TRACE_TRACEDATA1_PIN] = TRACE_PIN_CNF_VALUE;
|
||||
NRF_P0_S->PIN_CNF[TRACE_TRACEDATA2_PIN] = TRACE_PIN_CNF_VALUE;
|
||||
NRF_P0_S->PIN_CNF[TRACE_TRACEDATA3_PIN] = TRACE_PIN_CNF_VALUE;
|
||||
|
||||
// Select trace pins
|
||||
NRF_TAD_S->PSEL.TRACECLK = TRACE_TRACECLK_PIN;
|
||||
NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN;
|
||||
NRF_TAD_S->PSEL.TRACEDATA1 = TRACE_TRACEDATA1_PIN;
|
||||
NRF_TAD_S->PSEL.TRACEDATA2 = TRACE_TRACEDATA2_PIN;
|
||||
NRF_TAD_S->PSEL.TRACEDATA3 = TRACE_TRACEDATA3_PIN;
|
||||
|
||||
// Set trace port speed to 32 MHz
|
||||
NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz;
|
||||
|
||||
*((volatile uint32_t *)(0xE0053000ul)) = 0x00000001ul;
|
||||
|
||||
*((volatile uint32_t *)(0xE005AFB0ul)) = 0xC5ACCE55ul;
|
||||
*((volatile uint32_t *)(0xE005A000ul)) &= 0xFFFFFF00ul;
|
||||
*((volatile uint32_t *)(0xE005A004ul)) = 0x00000009ul;
|
||||
*((volatile uint32_t *)(0xE005A000ul)) = 0x00000303ul;
|
||||
*((volatile uint32_t *)(0xE005AFB0ul)) = 0x00000000ul;
|
||||
|
||||
*((volatile uint32_t *)(0xE005BFB0ul)) = 0xC5ACCE55ul;
|
||||
*((volatile uint32_t *)(0xE005B000ul)) &= 0xFFFFFF00ul;
|
||||
*((volatile uint32_t *)(0xE005B004ul)) = 0x00003000ul;
|
||||
*((volatile uint32_t *)(0xE005B000ul)) = 0x00000308ul;
|
||||
*((volatile uint32_t *)(0xE005BFB0ul)) = 0x00000000ul;
|
||||
|
||||
*((volatile uint32_t *)(0xE0058FB0ul)) = 0xC5ACCE55ul;
|
||||
*((volatile uint32_t *)(0xE0058000ul)) = 0x00000000ul;
|
||||
*((volatile uint32_t *)(0xE0058004ul)) = 0x00000000ul;
|
||||
*((volatile uint32_t *)(0xE0058FB0ul)) = 0x00000000ul;
|
||||
|
||||
/* Rom table does not list ETB, or TPIU base addresses.
|
||||
* Some debug probes may require manual configuration of these peripherals to enable tracing.
|
||||
* ETB_BASE = 0xE0051000
|
||||
* TPIU_BASE = 0xE0054000
|
||||
*/
|
||||
#endif
|
||||
|
||||
/* Allow Non-Secure code to run FPU instructions.
|
||||
* If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */
|
||||
SCB->NSACR |= (3UL << 10);
|
||||
#endif
|
||||
|
||||
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
|
||||
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
|
||||
* operations are not used in your code. */
|
||||
#if (__FPU_USED == 1)
|
||||
SCB->CPACR |= (3UL << 20) | (3UL << 22);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
|
||||
#if !defined(NRF_TRUSTZONE_NONSECURE)
|
||||
|
||||
bool uicr_HFXOCNT_erased()
|
||||
{
|
||||
if (is_empty_word(&NRF_UICR_S->HFXOCNT)) {
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
bool uicr_HFXOSRC_erased()
|
||||
{
|
||||
uint32_t HFXOSRC_readout = NRF_UICR_S->HFXOSRC;
|
||||
__DSB();
|
||||
if ((HFXOSRC_readout & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) {
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool is_empty_word(uint32_t const volatile * word)
|
||||
{
|
||||
uint32_t val = *word;
|
||||
__DSB();
|
||||
return val == 0xFFFFFFFFul;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* Workaround to allow NS code to access FICR. Override NRF_FICR_NS to move FICR_NS buffer. */
|
||||
#define FICR_SIZE 0x1000ul
|
||||
#define RAM_BASE 0x20000000ul
|
||||
#define RAM_END 0x2FFFFFFFul
|
||||
|
||||
/* Copy FICR_S to FICR_NS RAM region */
|
||||
void SystemStoreFICRNS()
|
||||
{
|
||||
if ((uint32_t)NRF_FICR_NS < RAM_BASE || (uint32_t)NRF_FICR_NS + FICR_SIZE > RAM_END)
|
||||
{
|
||||
/* FICR_NS is not in RAM. */
|
||||
return;
|
||||
}
|
||||
/* Copy FICR to NS-accessible RAM block. */
|
||||
volatile uint32_t * from = (volatile uint32_t *)((uint32_t)NRF_FICR_S + (FICR_SIZE - sizeof(uint32_t)));
|
||||
volatile uint32_t * to = (volatile uint32_t *)((uint32_t)NRF_FICR_NS + (FICR_SIZE - sizeof(uint32_t)));
|
||||
volatile uint32_t * copy_from_end = (volatile uint32_t *)NRF_FICR_S;
|
||||
while (from >= copy_from_end)
|
||||
{
|
||||
*(to--) = *(from--);
|
||||
}
|
||||
|
||||
/* Make RAM region NS. */
|
||||
uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE;
|
||||
__DSB();
|
||||
NRF_SPU_S->RAMREGION[ram_region].PERM &= ~(1 << SPU_RAMREGION_PERM_SECATTR_Pos);
|
||||
}
|
||||
|
||||
/* Block write and execute access to FICR RAM region */
|
||||
void SystemLockFICRNS()
|
||||
{
|
||||
if ((uint32_t)NRF_FICR_NS < RAM_BASE || (uint32_t)NRF_FICR_NS + FICR_SIZE > RAM_END)
|
||||
{
|
||||
/* FICR_NS is not in RAM. */
|
||||
return;
|
||||
}
|
||||
|
||||
uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE;
|
||||
__DSB();
|
||||
NRF_SPU_S->RAMREGION[ram_region].PERM &=
|
||||
~(
|
||||
(1 << SPU_RAMREGION_PERM_WRITE_Pos) |
|
||||
(1 << SPU_RAMREGION_PERM_EXECUTE_Pos)
|
||||
);
|
||||
NRF_SPU_S->RAMREGION[ram_region].PERM |= 1 << SPU_RAMREGION_PERM_LOCK_Pos;
|
||||
}
|
||||
|
||||
/*lint --flb "Leave library region" */
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
|
||||
Copyright (c) 2009-2022 ARM Limited. All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_NRF91_H
|
||||
#define SYSTEM_NRF91_H
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* SYSTEM_NRF91_H */
|
|
@ -1,325 +1,35 @@
|
|||
/*
|
||||
|
||||
Copyright (c) 2009-2022 ARM Limited. All rights reserved.
|
||||
Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
www.apache.org/licenses/LICENSE-2.0
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
/* NOTE: Template files (including this one) are application specific and therefore expected to
|
||||
be copied into the application project folder prior to its use! */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
#include "nrf_peripherals.h"
|
||||
#include "nrf91_erratas.h"
|
||||
#include "system_nrf9160.h"
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
||||
void SystemStoreFICRNS();
|
||||
|
||||
#define __SYSTEM_CLOCK (64000000UL) /*!< nRF9160 Application core uses a fixed System Clock Frequency of 64MHz */
|
||||
|
||||
#define TRACE_PIN_CNF_VALUE ( (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | \
|
||||
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \
|
||||
(GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | \
|
||||
(GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | \
|
||||
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) )
|
||||
#define TRACE_TRACECLK_PIN (21)
|
||||
#define TRACE_TRACEDATA0_PIN (22)
|
||||
#define TRACE_TRACEDATA1_PIN (23)
|
||||
#define TRACE_TRACEDATA2_PIN (24)
|
||||
#define TRACE_TRACEDATA3_PIN (25)
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
|
||||
#elif defined ( __ICCARM__ )
|
||||
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK;
|
||||
#elif defined ( __GNUC__ )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
|
||||
#endif
|
||||
|
||||
/* Global values used used in Secure mode SystemInit. */
|
||||
#if !defined(NRF_TRUSTZONE_NONSECURE)
|
||||
/* Global values used by UICR erase fix algorithm. */
|
||||
static uint32_t uicr_erased_value;
|
||||
static uint32_t uicr_new_value;
|
||||
#endif
|
||||
|
||||
/* Errata are only handled in secure mode since they usually need access to FICR. */
|
||||
#if !defined(NRF_TRUSTZONE_NONSECURE)
|
||||
static bool uicr_HFXOSRC_erased(void);
|
||||
static bool uicr_HFXOCNT_erased(void);
|
||||
static bool is_empty_word(uint32_t const volatile * word);
|
||||
#endif
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
}
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if !defined(NRF_TRUSTZONE_NONSECURE)
|
||||
/* Perform Secure-mode initialization routines. */
|
||||
|
||||
/* Set all ARM SAU regions to NonSecure if TrustZone extensions are enabled.
|
||||
* Nordic SPU should handle Secure Attribution tasks */
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
|
||||
#endif
|
||||
|
||||
/* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/index.jsp */
|
||||
if (nrf91_errata_6()){
|
||||
NRF_POWER_S->EVENTS_SLEEPENTER = (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos);
|
||||
NRF_POWER_S->EVENTS_SLEEPEXIT = (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos);
|
||||
}
|
||||
|
||||
/* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/index.jsp */
|
||||
if (nrf91_errata_14()){
|
||||
*((volatile uint32_t *)0x50004A38) = 0x01ul;
|
||||
NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 15 "REGULATORS: LDO mode at startup" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/index.jsp */
|
||||
if (nrf91_errata_15()){
|
||||
NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 20 "RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/index.jsp */
|
||||
if (nrf91_errata_20()){
|
||||
*((volatile uint32_t *)0x5003AEE4) = 0xE;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 31 "XOSC32k Startup Failure" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/index.jsp */
|
||||
if (nrf91_errata_31()){
|
||||
*((volatile uint32_t *)0x5000470Cul) = 0x0;
|
||||
*((volatile uint32_t *)0x50004710ul) = 0x1;
|
||||
}
|
||||
|
||||
#if !defined(NRF_SKIP_FICR_NS_COPY_TO_RAM)
|
||||
SystemStoreFICRNS();
|
||||
#endif
|
||||
|
||||
/* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
|
||||
until one ADDR is not initialized. */
|
||||
|
||||
for (uint32_t index = 0; index < 256ul && !is_empty_word(&NRF_FICR_S->TRIMCNF[index].ADDR); index++){
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma diag_suppress=Pa082
|
||||
#endif
|
||||
*(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma diag_default=Pa082
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Set UICR->HFXOSRC and UICR->HFXOCNT to working defaults if UICR was erased */
|
||||
if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) {
|
||||
/* Wait for pending NVMC operations to finish */
|
||||
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
|
||||
|
||||
/* Enable write mode in NVMC */
|
||||
NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen;
|
||||
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
|
||||
|
||||
if (uicr_HFXOSRC_erased()){
|
||||
/* Write default value to UICR->HFXOSRC */
|
||||
uicr_erased_value = NRF_UICR_S->HFXOSRC;
|
||||
uicr_new_value = (uicr_erased_value & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO;
|
||||
NRF_UICR_S->HFXOSRC = uicr_new_value;
|
||||
__DSB();
|
||||
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
|
||||
}
|
||||
|
||||
if (uicr_HFXOCNT_erased()){
|
||||
/* Write default value to UICR->HFXOCNT */
|
||||
uicr_erased_value = NRF_UICR_S->HFXOCNT;
|
||||
uicr_new_value = (uicr_erased_value & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20;
|
||||
NRF_UICR_S->HFXOCNT = uicr_new_value;
|
||||
__DSB();
|
||||
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
|
||||
}
|
||||
|
||||
/* Enable read mode in NVMC */
|
||||
NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren;
|
||||
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
|
||||
|
||||
/* Reset to apply clock select update */
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
|
||||
Specification to see which ones). */
|
||||
#if defined (ENABLE_TRACE)
|
||||
// Enable Trace And Debug peripheral
|
||||
NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk;
|
||||
NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk;
|
||||
|
||||
// Set up Trace pads SPU firewall
|
||||
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACECLK_PIN);
|
||||
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA0_PIN);
|
||||
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA1_PIN);
|
||||
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA2_PIN);
|
||||
NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA3_PIN);
|
||||
|
||||
// Configure trace port pads
|
||||
NRF_P0_S->PIN_CNF[TRACE_TRACECLK_PIN] = TRACE_PIN_CNF_VALUE;
|
||||
NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE;
|
||||
NRF_P0_S->PIN_CNF[TRACE_TRACEDATA1_PIN] = TRACE_PIN_CNF_VALUE;
|
||||
NRF_P0_S->PIN_CNF[TRACE_TRACEDATA2_PIN] = TRACE_PIN_CNF_VALUE;
|
||||
NRF_P0_S->PIN_CNF[TRACE_TRACEDATA3_PIN] = TRACE_PIN_CNF_VALUE;
|
||||
|
||||
// Select trace pins
|
||||
NRF_TAD_S->PSEL.TRACECLK = TRACE_TRACECLK_PIN;
|
||||
NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN;
|
||||
NRF_TAD_S->PSEL.TRACEDATA1 = TRACE_TRACEDATA1_PIN;
|
||||
NRF_TAD_S->PSEL.TRACEDATA2 = TRACE_TRACEDATA2_PIN;
|
||||
NRF_TAD_S->PSEL.TRACEDATA3 = TRACE_TRACEDATA3_PIN;
|
||||
|
||||
// Set trace port speed to 32 MHz
|
||||
NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz;
|
||||
|
||||
*((volatile uint32_t *)(0xE0053000ul)) = 0x00000001ul;
|
||||
|
||||
*((volatile uint32_t *)(0xE005AFB0ul)) = 0xC5ACCE55ul;
|
||||
*((volatile uint32_t *)(0xE005A000ul)) &= 0xFFFFFF00ul;
|
||||
*((volatile uint32_t *)(0xE005A004ul)) = 0x00000009ul;
|
||||
*((volatile uint32_t *)(0xE005A000ul)) = 0x00000303ul;
|
||||
*((volatile uint32_t *)(0xE005AFB0ul)) = 0x00000000ul;
|
||||
|
||||
*((volatile uint32_t *)(0xE005BFB0ul)) = 0xC5ACCE55ul;
|
||||
*((volatile uint32_t *)(0xE005B000ul)) &= 0xFFFFFF00ul;
|
||||
*((volatile uint32_t *)(0xE005B004ul)) = 0x00003000ul;
|
||||
*((volatile uint32_t *)(0xE005B000ul)) = 0x00000308ul;
|
||||
*((volatile uint32_t *)(0xE005BFB0ul)) = 0x00000000ul;
|
||||
|
||||
*((volatile uint32_t *)(0xE0058FB0ul)) = 0xC5ACCE55ul;
|
||||
*((volatile uint32_t *)(0xE0058000ul)) = 0x00000000ul;
|
||||
*((volatile uint32_t *)(0xE0058004ul)) = 0x00000000ul;
|
||||
*((volatile uint32_t *)(0xE0058FB0ul)) = 0x00000000ul;
|
||||
|
||||
/* Rom table does not list ETB, or TPIU base addresses.
|
||||
* Some debug probes may require manual configuration of these peripherals to enable tracing.
|
||||
* ETB_BASE = 0xE0051000
|
||||
* TPIU_BASE = 0xE0054000
|
||||
*/
|
||||
#endif
|
||||
|
||||
/* Allow Non-Secure code to run FPU instructions.
|
||||
* If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */
|
||||
SCB->NSACR |= (3UL << 10);
|
||||
#endif
|
||||
|
||||
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
|
||||
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
|
||||
* operations are not used in your code. */
|
||||
#if (__FPU_USED == 1)
|
||||
SCB->CPACR |= (3UL << 20) | (3UL << 22);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
|
||||
#if !defined(NRF_TRUSTZONE_NONSECURE)
|
||||
|
||||
bool uicr_HFXOCNT_erased()
|
||||
{
|
||||
if (is_empty_word(&NRF_UICR_S->HFXOCNT)) {
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
bool uicr_HFXOSRC_erased()
|
||||
{
|
||||
uint32_t HFXOSRC_readout = NRF_UICR_S->HFXOSRC;
|
||||
__DSB();
|
||||
if ((HFXOSRC_readout & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) {
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool is_empty_word(uint32_t const volatile * word)
|
||||
{
|
||||
uint32_t val = *word;
|
||||
__DSB();
|
||||
return val == 0xFFFFFFFFul;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* Workaround to allow NS code to access FICR. Override NRF_FICR_NS to move FICR_NS buffer. */
|
||||
#define FICR_SIZE 0x1000ul
|
||||
#define RAM_BASE 0x20000000ul
|
||||
#define RAM_END 0x2FFFFFFFul
|
||||
|
||||
/* Copy FICR_S to FICR_NS RAM region */
|
||||
void SystemStoreFICRNS()
|
||||
{
|
||||
if ((uint32_t)NRF_FICR_NS < RAM_BASE || (uint32_t)NRF_FICR_NS + FICR_SIZE > RAM_END)
|
||||
{
|
||||
/* FICR_NS is not in RAM. */
|
||||
return;
|
||||
}
|
||||
/* Copy FICR to NS-accessible RAM block. */
|
||||
volatile uint32_t * from = (volatile uint32_t *)((uint32_t)NRF_FICR_S + (FICR_SIZE - sizeof(uint32_t)));
|
||||
volatile uint32_t * to = (volatile uint32_t *)((uint32_t)NRF_FICR_NS + (FICR_SIZE - sizeof(uint32_t)));
|
||||
volatile uint32_t * copy_from_end = (volatile uint32_t *)NRF_FICR_S;
|
||||
while (from >= copy_from_end)
|
||||
{
|
||||
*(to--) = *(from--);
|
||||
}
|
||||
|
||||
/* Make RAM region NS. */
|
||||
uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE;
|
||||
__DSB();
|
||||
NRF_SPU_S->RAMREGION[ram_region].PERM &= ~(1 << SPU_RAMREGION_PERM_SECATTR_Pos);
|
||||
}
|
||||
|
||||
/* Block write and execute access to FICR RAM region */
|
||||
void SystemLockFICRNS()
|
||||
{
|
||||
if ((uint32_t)NRF_FICR_NS < RAM_BASE || (uint32_t)NRF_FICR_NS + FICR_SIZE > RAM_END)
|
||||
{
|
||||
/* FICR_NS is not in RAM. */
|
||||
return;
|
||||
}
|
||||
|
||||
uint32_t ram_region = ((uint32_t)NRF_FICR_NS - (uint32_t)RAM_BASE) / SPU_RAMREGION_SIZE;
|
||||
__DSB();
|
||||
NRF_SPU_S->RAMREGION[ram_region].PERM &=
|
||||
~(
|
||||
(1 << SPU_RAMREGION_PERM_WRITE_Pos) |
|
||||
(1 << SPU_RAMREGION_PERM_EXECUTE_Pos)
|
||||
);
|
||||
NRF_SPU_S->RAMREGION[ram_region].PERM |= 1 << SPU_RAMREGION_PERM_LOCK_Pos;
|
||||
}
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
#include "system_nrf91.c"
|
||||
|
|
|
@ -0,0 +1,44 @@
|
|||
# Changelog
|
||||
All notable changes to this project are documented in this file.
|
||||
|
||||
## [2.10.0] - 2022-10-25
|
||||
### Added
|
||||
- Added this CHANGELOG.md file.
|
||||
- Added README.md file with introduction and configuration.
|
||||
- Added README.md file with description for each specfic example.
|
||||
- Added documentation generated using Doxygen tool.
|
||||
- Added documentation generated using Breathe and Sphinx tools.
|
||||
- Added example for the EGU driver.
|
||||
- Added example for the RNG driver.
|
||||
- Added below examples for the TIMER driver:
|
||||
- counter
|
||||
- timer
|
||||
- Added below examples for the TEMP driver:
|
||||
- blocking
|
||||
- non-blocking
|
||||
- Added below examples for the PWM driver:
|
||||
- common mode
|
||||
- grouped mode
|
||||
- Added below examples for the GPPI driver:
|
||||
- one-to-one
|
||||
- fork
|
||||
- Added below examples for the SPIM driver:
|
||||
- blocking
|
||||
- non-blocking
|
||||
- Added below examples for the SPIM and SPIS drivers:
|
||||
- non-blocking
|
||||
- advanced non-blocking
|
||||
- Added below examples for the TWIM and TWIS drivers:
|
||||
- tx-rx blocking
|
||||
- tx-rx non-blocking
|
||||
- tx-rx
|
||||
- tx-tx
|
||||
- Added below examples for the UARTE driver:
|
||||
- rx double-buffered
|
||||
- tx-rx non-blocking
|
||||
- Added below examples for the SAADC driver:
|
||||
- simple blocking
|
||||
- simple non-blocking
|
||||
- advanced blocking
|
||||
- advanced non-blocking with internal timer
|
||||
- maximum performance
|
|
@ -0,0 +1,33 @@
|
|||
# File containing common functions, macros and variables used across all examples.
|
||||
# This file should be included in each CMakeLists.txt if compiled with west tool under Zephyr.
|
||||
|
||||
# Add common Kconfig file to project.
|
||||
list(APPEND CONF_FILE "${CMAKE_CURRENT_LIST_DIR}/common.conf")
|
||||
|
||||
# Add project Kconfig file if it exists.
|
||||
set(PRJ_CONF_FILE "${CMAKE_CURRENT_SOURCE_DIR}/prj.conf")
|
||||
if(EXISTS ${PRJ_CONF_FILE})
|
||||
list(APPEND CONF_FILE ${PRJ_CONF_FILE})
|
||||
endif()
|
||||
|
||||
# Macro adding overlay file and Kconfig file for specified board in given directory.
|
||||
# If board-specific files have been found they are added to DTC_OVERLAY_FILE and CONF_FILE
|
||||
# symbols that are used in west build system.
|
||||
macro(GET_DEVICE_CONFIG_FILES BOARD BOARDS_DIR)
|
||||
if(NOT IS_ABSOLUTE BOARDS_DIR)
|
||||
set(_BOARDS_DIR ${CMAKE_CURRENT_LIST_DIR}/${BOARDS_DIR})
|
||||
get_filename_component(BOARDS_DIR_ABSOLUTE "${_BOARDS_DIR}" ABSOLUTE)
|
||||
else()
|
||||
set(BOARDS_DIR_ABSOLUTE {BOARDS_DIR})
|
||||
endif()
|
||||
|
||||
set(OVERLAY_FILE "${BOARDS_DIR_ABSOLUTE}/${BOARD}.overlay")
|
||||
if(EXISTS ${OVERLAY_FILE})
|
||||
list(APPEND DTC_OVERLAY_FILE "${OVERLAY_FILE}")
|
||||
endif()
|
||||
|
||||
set(CONFIG_FILE "${BOARDS_DIR_ABSOLUTE}/${BOARD}.conf")
|
||||
if(EXISTS ${CONFIG_FILE})
|
||||
list(APPEND CONF_FILE "${CONFIG_FILE}")
|
||||
endif()
|
||||
endmacro()
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_LOG=y
|
||||
CONFIG_BOOT_BANNER=n
|
||||
CONFIG_ASSERT=y
|
||||
CONFIG_LOG_PROCESS_THREAD=n
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef NRFX_EXAMPLE_H__
|
||||
#define NRFX_EXAMPLE_H__
|
||||
|
||||
#if defined(__ZEPHYR__)
|
||||
#include <zephyr/logging/log_ctrl.h>
|
||||
#define NRFX_EXAMPLE_LOG_INIT() LOG_INIT()
|
||||
#define NRFX_EXAMPLE_LOG_PROCESS() while (LOG_PROCESS())
|
||||
#else
|
||||
#define NRFX_EXAMPLE_LOG_INIT()
|
||||
#define NRFX_EXAMPLE_LOG_PROCESS()
|
||||
#endif
|
||||
|
||||
#if defined(NRF52_SERIES)
|
||||
#define LOOPBACK_PIN_1A 3
|
||||
#define LOOPBACK_PIN_1B 31
|
||||
#define LOOPBACK_PIN_2A 4
|
||||
#define LOOPBACK_PIN_2B 30
|
||||
#define LOOPBACK_PIN_3A 28
|
||||
#define LOOPBACK_PIN_3B 29
|
||||
#define LOOPBACK_PIN_4A 26
|
||||
#define LOOPBACK_PIN_4B 27
|
||||
#define ANALOG_INPUT_A0 1
|
||||
#define ANALOG_INPUT_A1 2
|
||||
#define ANALOG_INPUT_A2 4
|
||||
#if defined(NRF52832_XXAA) || defined (NRF52832_XXAB)
|
||||
#define LED1_PIN 17
|
||||
#define LED2_PIN 18
|
||||
#define LED3_PIN 19
|
||||
#define LED4_PIN 20
|
||||
#else
|
||||
#define LED1_PIN 13
|
||||
#define LED2_PIN 14
|
||||
#define LED3_PIN 15
|
||||
#define LED4_PIN 16
|
||||
#endif
|
||||
#elif defined(NRF53_SERIES)
|
||||
#define LOOPBACK_PIN_1A 4
|
||||
#define LOOPBACK_PIN_1B 26
|
||||
#define LOOPBACK_PIN_2A 5
|
||||
#define LOOPBACK_PIN_2B 25
|
||||
#define LOOPBACK_PIN_3A 6
|
||||
#define LOOPBACK_PIN_3B 7
|
||||
#define LOOPBACK_PIN_4A 34
|
||||
#define LOOPBACK_PIN_4B 35
|
||||
#define ANALOG_INPUT_A0 0
|
||||
#define ANALOG_INPUT_A1 1
|
||||
#define ANALOG_INPUT_A2 2
|
||||
#define LED1_PIN 28
|
||||
#define LED2_PIN 29
|
||||
#define LED3_PIN 30
|
||||
#define LED4_PIN 31
|
||||
#elif defined(NRF91_SERIES)
|
||||
#define LOOPBACK_PIN_1A 14
|
||||
#define LOOPBACK_PIN_1B 19
|
||||
#define LOOPBACK_PIN_2A 15
|
||||
#define LOOPBACK_PIN_2B 18
|
||||
#define LOOPBACK_PIN_3A 16
|
||||
#define LOOPBACK_PIN_3B 17
|
||||
#define LOOPBACK_PIN_4A 30
|
||||
#define LOOPBACK_PIN_4B 31
|
||||
#define ANALOG_INPUT_A0 1
|
||||
#define ANALOG_INPUT_A1 2
|
||||
#define ANALOG_INPUT_A2 3
|
||||
#define LED1_PIN 2
|
||||
#define LED2_PIN 3
|
||||
#define LED3_PIN 4
|
||||
#define LED4_PIN 5
|
||||
#else
|
||||
#error "Unknown device."
|
||||
#endif
|
||||
|
||||
#define ANALOG_INPUT_TO_SAADC_AIN(x) ((x) + 1)
|
||||
|
||||
#define ANALOG_INPUT_TO_COMP_AIN(x) (x)
|
||||
|
||||
#endif // NRFX_EXAMPLE_H__
|
|
@ -0,0 +1,41 @@
|
|||
# Building the documentation
|
||||
|
||||
## Doxygen
|
||||
|
||||
Generate the Doxygen-based documentation by running:
|
||||
|
||||
```shell
|
||||
doxygen nrfx_examples.doxyfile
|
||||
```
|
||||
|
||||
You can also use the provided script `generate_html_doc.sh` located in the `doc` folder.
|
||||
The output can be viewed by navigating to `html` folder and opening `index.html` file.
|
||||
|
||||
## Sphinx
|
||||
|
||||
All the necessary files to compile the Sphinx based documentation for `nrfx_examples`
|
||||
are located under `sphinx` folder. As of today the content should match with
|
||||
the one produced using `doxygen` only.
|
||||
|
||||
### Requirements
|
||||
|
||||
You will need to have Python 3 installed as well as some dependencies, which can
|
||||
be installed by running:
|
||||
|
||||
```shell
|
||||
pip install -r requirements.txt
|
||||
```
|
||||
|
||||
### Build
|
||||
|
||||
You may want to use the provided script `generate_sphinx_doc.sh`. The result can be viewed by opening `html_sphinx/index.html`.
|
||||
|
||||
If you want to do it manually you can run the following commands from `doc`
|
||||
directory:
|
||||
|
||||
```shell
|
||||
# compile doxygen documentation (required to generate XML metadata)
|
||||
doxygen nrfx_examples.doxyfile
|
||||
# compile Sphinx documentation
|
||||
sphinx-build -b html sphinx html_sphinx
|
||||
```
|
|
@ -0,0 +1,501 @@
|
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|
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|
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|
||||
img:not(.png) {
|
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|
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|
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|
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|
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|
||||
|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
|
||||
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|
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
display: table;
|
||||
width: 100%;
|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
.sdkversion {
|
||||
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|
||||
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|
||||
|
||||
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|
||||
font-size: 12px;
|
||||
font-style: italic;
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
|
||||
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|
||||
color: #0081B7;
|
||||
border-color: #0081B7;
|
||||
}
|
||||
|
||||
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|
||||
color: #7f7f7f;
|
||||
border-color: #7f7f7f;
|
||||
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|
||||
|
||||
div.whichnRF {
|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
border-top:1px solid #8EA7B0;
|
||||
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|
||||
|
||||
|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
|
||||
/* overrides */
|
||||
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|
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text-align: right;
|
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// margin-top: 1px;
|
||||
padding-right: 10px;
|
||||
box-shadow: inset 0px 1px 0px 0px #e0e0e0;
|
||||
font-size: 13px;
|
||||
}
|
Binary file not shown.
After Width: | Height: | Size: 26 KiB |
|
@ -0,0 +1,10 @@
|
|||
<div id="nav-path" class="topicfooter">
|
||||
<a href="https://github.com/NordicSemiconductor/nrfx/issues" target="_blank">nrfx feedback</a> | <a href="https://devzone.nordicsemi.com/" target="_blank">Nordic DevZone</a> | <a href="http://response.nordicsemi.com/subscribe-to-our-newsletters" target="_blank">Subscribe</a> | Updated <span id="date"/>
|
||||
|
||||
<script>
|
||||
var date = new Date("$date" + " UTC");
|
||||
document.getElementById("date").innerHTML = date.toJSON().slice(0, 10);
|
||||
</script>
|
||||
</div>
|
||||
</body>
|
||||
</html>
|
|
@ -0,0 +1,58 @@
|
|||
<!-- HTML header for doxygen 1.8.3.1-->
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
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|
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|
||||
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|
||||
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|
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|
||||
<!--BEGIN PROJECT_NAME--><title>$projectname $projectnumber: $title</title><!--END PROJECT_NAME-->
|
||||
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|
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|
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|
||||
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|
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|
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|
||||
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|
||||
<link href="$relpath^nordic.css" rel="stylesheet" type="text/css" />
|
||||
<link rel="Shortcut icon" href="./favicon.ico" type="image/x-icon" />
|
||||
</head>
|
||||
<body>
|
||||
|
||||
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
|
||||
|
||||
<!--BEGIN TITLEAREA-->
|
||||
<div id="titlearea">
|
||||
<table cellspacing="0" cellpadding="0" width="100%" class="blank">
|
||||
<tbody>
|
||||
<tr style="height: 56px;">
|
||||
<!--BEGIN PROJECT_LOGO-->
|
||||
<td id="projectlogo"><img alt="Nordic Semiconductor" src="$relpath^$projectlogo"/></td>
|
||||
<!--END PROJECT_LOGO-->
|
||||
<!--BEGIN PROJECT_NAME-->
|
||||
<td style="padding-left: 0.5em;">
|
||||
<div id="projectname">$projectname
|
||||
<!--BEGIN PROJECT_NUMBER--> <span id="projectnumber">$projectnumber</span><!--END PROJECT_NUMBER-->
|
||||
</div>
|
||||
<!--BEGIN PROJECT_BRIEF--><div id="projectbrief">$projectbrief</div><!--END PROJECT_BRIEF-->
|
||||
</td>
|
||||
<!--END PROJECT_NAME-->
|
||||
<!--BEGIN !PROJECT_NAME-->
|
||||
<!--BEGIN PROJECT_BRIEF-->
|
||||
<td style="padding-left: 0.5em;">
|
||||
<div id="projectbrief">$projectbrief</div>
|
||||
</td>
|
||||
<!--END PROJECT_BRIEF-->
|
||||
<!--END !PROJECT_NAME-->
|
||||
<!--BEGIN DISABLE_INDEX-->
|
||||
<!--BEGIN SEARCHENGINE-->
|
||||
<td>$searchbox</td>
|
||||
<!--END SEARCHENGINE-->
|
||||
<!--END DISABLE_INDEX-->
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
</div>
|
||||
<!--END TITLEAREA-->
|
||||
<!-- end header part -->
|
|
@ -0,0 +1,181 @@
|
|||
<doxygenlayout version="1.0">
|
||||
<!-- Navigation index tabs for HTML output -->
|
||||
<navindex>
|
||||
<tab type="mainpage" visible="yes" title="Home"/>
|
||||
<tab type="pages" visible="yes" title="" intro=""/>
|
||||
<tab type="modules" visible="yes" title="Examples Reference" intro=""/>
|
||||
<tab type="namespaces" visible="no" title="">
|
||||
<tab type="namespacelist" visible="yes" title="" intro=""/>
|
||||
<tab type="namespacemembers" visible="yes" title="" intro=""/>
|
||||
</tab>
|
||||
<tab type="files" visible="no" title="">
|
||||
<tab type="filelist" visible="yes" title="" intro=""/>
|
||||
<tab type="globals" visible="yes" title="" intro=""/>
|
||||
</tab>
|
||||
<tab type="examples" visible="yes" title="Source" intro=""/>
|
||||
</navindex>
|
||||
|
||||
<!-- Layout definition for a class page -->
|
||||
<class>
|
||||
<briefdescription visible="yes"/>
|
||||
<includes visible="$SHOW_INCLUDE_FILES"/>
|
||||
<inheritancegraph visible="$CLASS_GRAPH"/>
|
||||
<collaborationgraph visible="$COLLABORATION_GRAPH"/>
|
||||
<memberdecl>
|
||||
<nestedclasses visible="yes" title=""/>
|
||||
<publictypes title=""/>
|
||||
<publicslots title=""/>
|
||||
<signals title=""/>
|
||||
<publicmethods title=""/>
|
||||
<publicstaticmethods title=""/>
|
||||
<publicattributes title=""/>
|
||||
<publicstaticattributes title=""/>
|
||||
<protectedtypes title=""/>
|
||||
<protectedslots title=""/>
|
||||
<protectedmethods title=""/>
|
||||
<protectedstaticmethods title=""/>
|
||||
<protectedattributes title=""/>
|
||||
<protectedstaticattributes title=""/>
|
||||
<packagetypes title=""/>
|
||||
<packagemethods title=""/>
|
||||
<packagestaticmethods title=""/>
|
||||
<packageattributes title=""/>
|
||||
<packagestaticattributes title=""/>
|
||||
<properties title=""/>
|
||||
<events title=""/>
|
||||
<privatetypes title=""/>
|
||||
<privateslots title=""/>
|
||||
<privatemethods title=""/>
|
||||
<privatestaticmethods title=""/>
|
||||
<privateattributes title=""/>
|
||||
<privatestaticattributes title=""/>
|
||||
<friends title=""/>
|
||||
<related title="" subtitle=""/>
|
||||
<membergroups visible="yes"/>
|
||||
</memberdecl>
|
||||
<detaileddescription title=""/>
|
||||
<memberdef>
|
||||
<inlineclasses title=""/>
|
||||
<typedefs title=""/>
|
||||
<enums title=""/>
|
||||
<constructors title=""/>
|
||||
<functions title=""/>
|
||||
<related title=""/>
|
||||
<variables title=""/>
|
||||
<properties title=""/>
|
||||
<events title=""/>
|
||||
</memberdef>
|
||||
<allmemberslink visible="yes"/>
|
||||
<usedfiles visible="$SHOW_USED_FILES"/>
|
||||
<authorsection visible="yes"/>
|
||||
</class>
|
||||
|
||||
<!-- Layout definition for a namespace page -->
|
||||
<namespace>
|
||||
<briefdescription visible="yes"/>
|
||||
<memberdecl>
|
||||
<nestednamespaces visible="yes" title=""/>
|
||||
<classes visible="yes" title=""/>
|
||||
<typedefs title=""/>
|
||||
<enums title=""/>
|
||||
<functions title=""/>
|
||||
<variables title=""/>
|
||||
<membergroups visible="yes"/>
|
||||
</memberdecl>
|
||||
<detaileddescription title=""/>
|
||||
<memberdef>
|
||||
<inlineclasses title=""/>
|
||||
<typedefs title=""/>
|
||||
<enums title=""/>
|
||||
<functions title=""/>
|
||||
<variables title=""/>
|
||||
</memberdef>
|
||||
<authorsection visible="yes"/>
|
||||
</namespace>
|
||||
|
||||
<!-- Layout definition for a file page -->
|
||||
<file>
|
||||
<briefdescription visible="yes"/>
|
||||
<includes visible="$SHOW_INCLUDE_FILES"/>
|
||||
<includegraph visible="$INCLUDE_GRAPH"/>
|
||||
<includedbygraph visible="$INCLUDED_BY_GRAPH"/>
|
||||
<sourcelink visible="yes"/>
|
||||
<memberdecl>
|
||||
<classes visible="yes" title=""/>
|
||||
<namespaces visible="yes" title=""/>
|
||||
<defines title=""/>
|
||||
<typedefs title=""/>
|
||||
<enums title=""/>
|
||||
<functions title=""/>
|
||||
<variables title=""/>
|
||||
<membergroups visible="yes"/>
|
||||
</memberdecl>
|
||||
<detaileddescription title=""/>
|
||||
<memberdef>
|
||||
<inlineclasses title=""/>
|
||||
<defines title=""/>
|
||||
<typedefs title=""/>
|
||||
<enums title=""/>
|
||||
<functions title=""/>
|
||||
<variables title=""/>
|
||||
</memberdef>
|
||||
<authorsection/>
|
||||
</file>
|
||||
|
||||
<!-- Layout definition for a group page -->
|
||||
<group>
|
||||
<briefdescription visible="yes"/>
|
||||
<groupgraph visible="$GROUP_GRAPHS"/>
|
||||
<memberdecl>
|
||||
<nestedgroups visible="yes" title=""/>
|
||||
<dirs visible="yes" title=""/>
|
||||
<files visible="yes" title=""/>
|
||||
<namespaces visible="yes" title=""/>
|
||||
<classes visible="yes" title=""/>
|
||||
<defines title=""/>
|
||||
<typedefs title=""/>
|
||||
<enums title=""/>
|
||||
<enumvalues title=""/>
|
||||
<functions title=""/>
|
||||
<variables title=""/>
|
||||
<signals title=""/>
|
||||
<publicslots title=""/>
|
||||
<protectedslots title=""/>
|
||||
<privateslots title=""/>
|
||||
<events title=""/>
|
||||
<properties title=""/>
|
||||
<friends title=""/>
|
||||
<membergroups visible="yes"/>
|
||||
</memberdecl>
|
||||
<detaileddescription title=""/>
|
||||
<memberdef>
|
||||
<pagedocs/>
|
||||
<inlineclasses title=""/>
|
||||
<defines title=""/>
|
||||
<typedefs title=""/>
|
||||
<enums title=""/>
|
||||
<enumvalues title=""/>
|
||||
<functions title=""/>
|
||||
<variables title=""/>
|
||||
<signals title=""/>
|
||||
<publicslots title=""/>
|
||||
<protectedslots title=""/>
|
||||
<privateslots title=""/>
|
||||
<events title=""/>
|
||||
<properties title=""/>
|
||||
<friends title=""/>
|
||||
</memberdef>
|
||||
<authorsection visible="yes"/>
|
||||
</group>
|
||||
|
||||
<!-- Layout definition for a directory page -->
|
||||
<directory>
|
||||
<briefdescription visible="yes"/>
|
||||
<directorygraph visible="yes"/>
|
||||
<memberdecl>
|
||||
<dirs visible="yes"/>
|
||||
<files visible="yes"/>
|
||||
</memberdecl>
|
||||
<detaileddescription title=""/>
|
||||
</directory>
|
||||
</doxygenlayout>
|
Binary file not shown.
After Width: | Height: | Size: 4.2 KiB |
|
@ -0,0 +1,2 @@
|
|||
del html\*.* xml\*.* /Q
|
||||
doxygen nrfx_examples.doxyfile
|
|
@ -0,0 +1,4 @@
|
|||
rm -rf html xml
|
||||
|
||||
# Running doxygen
|
||||
doxygen nrfx_examples.doxyfile
|
|
@ -0,0 +1,3 @@
|
|||
del html\*.* xml\*.* html_sphinx\*.* /Q
|
||||
doxygen nrfx_examples.doxyfile
|
||||
sphinx-build -b html sphinx html_sphinx
|
|
@ -0,0 +1,3 @@
|
|||
rm -rf html xml html_sphinx
|
||||
doxygen nrfx_examples.doxyfile
|
||||
sphinx-build -b html sphinx html_sphinx
|
Binary file not shown.
After Width: | Height: | Size: 3.3 MiB |
Binary file not shown.
After Width: | Height: | Size: 8.0 MiB |
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,73 @@
|
|||
/**
|
||||
@page nrfx_examples_desc Examples Descriptions
|
||||
The complete base, where you can find all the necessary information about examples:
|
||||
- @subpage nrfx_egu_example_desc
|
||||
- @subpage nrfx_gppi_example_desc
|
||||
- @subpage nrfx_pwm_example_desc
|
||||
- @subpage nrfx_rng_example_desc
|
||||
- @subpage nrfx_saadc_example_desc
|
||||
- @subpage nrfx_spim_example_desc
|
||||
- @subpage nrfx_spim_spis_example_desc
|
||||
- @subpage nrfx_temp_example_desc
|
||||
- @subpage nrfx_timer_example_desc
|
||||
- @subpage nrfx_twim_twis_example_desc
|
||||
- @subpage nrfx_uarte_example_desc
|
||||
|
||||
@page nrfx_egu_example_desc EGU
|
||||
Here you can find all the necessary information about following examples:
|
||||
- @subpage egu_basic_desc
|
||||
|
||||
@page nrfx_gppi_example_desc GPPI
|
||||
Here you can find all the necessary information about following examples:
|
||||
- @subpage gppi_basic_fork_desc
|
||||
- @subpage gppi_basic_one_to_one_desc
|
||||
|
||||
@page nrfx_pwm_example_desc PWM
|
||||
Here you can find all the necessary information about following examples:
|
||||
- @subpage pwm_common_desc
|
||||
- @subpage pwm_grouped_desc
|
||||
|
||||
@page nrfx_rng_example_desc RNG
|
||||
Here you can find all the necessary information about following examples:
|
||||
- @subpage rng_basic_desc
|
||||
|
||||
@page nrfx_saadc_example_desc SAADC
|
||||
Here you can find all the necessary information about following examples:
|
||||
- @subpage saadc_simple_blocking
|
||||
- @subpage saadc_simple_non_blocking
|
||||
- @subpage saadc_advanced_blocking
|
||||
- @subpage saadc_advanced_non_blocking_internal_timer
|
||||
- @subpage saadc_maximum_performance
|
||||
|
||||
@page nrfx_spim_example_desc SPIM
|
||||
Here you can find all the necessary information about following examples:
|
||||
- @subpage spim_basic_blocking
|
||||
- @subpage spim_basic_non_blocking
|
||||
|
||||
@page nrfx_spim_spis_example_desc SPIM with SPIS
|
||||
Here you can find all the necessary information about following examples:
|
||||
- @subpage spim_spis_non_blocking
|
||||
- @subpage spim_spis_advanced_non_blocking_example
|
||||
|
||||
@page nrfx_temp_example_desc TEMP
|
||||
Here you can find all the necessary information about following examples:
|
||||
- @subpage temp_blocking
|
||||
- @subpage temp_non_blocking
|
||||
|
||||
@page nrfx_timer_example_desc TIMER
|
||||
Here you can find all the necessary information about following examples:
|
||||
- @subpage timer_basic
|
||||
- @subpage timer_counter
|
||||
|
||||
@page nrfx_twim_twis_example_desc TWIM with TWIS
|
||||
Here you can find all the necessary information about following examples:
|
||||
- @subpage twim_twis_tx_rx_blocking
|
||||
- @subpage twim_twis_tx_rx_non_blocking
|
||||
- @subpage twim_twis_txrx
|
||||
- @subpage twim_twis_txtx
|
||||
|
||||
@page nrfx_uarte_example_desc UARTE
|
||||
Here you can find all the necessary information about following examples:
|
||||
- @subpage uarte_tx_rx_non_blocking
|
||||
- @subpage uarte_rx_double_buffered
|
||||
*/
|
|
@ -0,0 +1,3 @@
|
|||
:root {
|
||||
--docset-color: #412ee8;
|
||||
}
|
|
@ -0,0 +1 @@
|
|||
.. mdinclude:: ../../CHANGELOG.md
|
|
@ -0,0 +1,51 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
from pathlib import Path
|
||||
import re
|
||||
|
||||
|
||||
CONF_DIR = Path(__file__).absolute().parent
|
||||
"""conf.py directory."""
|
||||
|
||||
with open(CONF_DIR / ".." / "nrfx_examples.doxyfile") as f:
|
||||
VERSION = re.search(r'PROJECT_NUMBER\s+=\s+"(.*)"', f.read()).group(1)
|
||||
|
||||
# General configuration --------------------------------------------------------
|
||||
|
||||
project = "nrfx_examples"
|
||||
copyright = "2022, Nordic Semiconductor ASA"
|
||||
author = "Nordic Semiconductor"
|
||||
version = VERSION
|
||||
|
||||
extensions = ["breathe", "m2r2"]
|
||||
source_suffix = {
|
||||
".rst": "restructuredtext",
|
||||
".md": "markdown"
|
||||
}
|
||||
master_doc = "index"
|
||||
exclude_patterns = ["theme"]
|
||||
|
||||
# Options for HTML output ------------------------------------------------------
|
||||
|
||||
html_theme = "sphinx_ncs_theme"
|
||||
html_static_path = [str(CONF_DIR / "_static")]
|
||||
html_last_updated_fmt = "%b %d, %Y"
|
||||
html_show_sphinx = False
|
||||
|
||||
# Options for Breathe ----------------------------------------------------------
|
||||
|
||||
breathe_projects = {"nrfx_examples": str(CONF_DIR / ".." / "xml")}
|
||||
breathe_default_project = "nrfx_examples"
|
||||
breathe_domain_by_extension = {"h": "c", "c": "c"}
|
||||
breathe_separate_member_pages = True
|
||||
|
||||
c_id_attributes = [
|
||||
"NRF_STATIC_INLINE",
|
||||
"NRFX_STATIC_INLINE",
|
||||
"__STATIC_INLINE",
|
||||
]
|
||||
cpp_id_attributes = c_id_attributes
|
||||
|
||||
|
||||
def setup(app):
|
||||
app.add_css_file("css/nrfx_examples.css")
|
|
@ -0,0 +1,18 @@
|
|||
Examples Descriptions
|
||||
=====================
|
||||
|
||||
.. toctree::
|
||||
:glob:
|
||||
|
||||
examples_desc/egu/index
|
||||
examples_desc/gppi/index
|
||||
examples_desc/pwm/index
|
||||
examples_desc/rng/index
|
||||
examples_desc/saadc/index
|
||||
examples_desc/spim/index
|
||||
examples_desc/spim_spis/index
|
||||
examples_desc/temp/index
|
||||
examples_desc/timer/index
|
||||
examples_desc/twim_twis/index
|
||||
examples_desc/uarte/index
|
||||
|
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Reference in New Issue