nrfx: Update to version 2.10.0

Update nrfx to the recently released version. See
https://github.com/NordicSemiconductor/nrfx/blob/v2.10.0/CHANGELOG.md
for a list of changes that this version introduces.

Origin: nrfx
License: BSD 3-Clause
URL: https://github.com/NordicSemiconductor/nrfx/tree/v2.10.0
commit: 23fb4437c08a9edfdf6d34f002322f693a15e8fe
Purpose: Provide peripheral drivers for Nordic SoCs
Maintained-by: External

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
pull/123/head
Adam Wojasinski 3 months ago committed by Andrzej Głąbek
parent 249199ec5a
commit 4ee20fd6ca

@ -1,6 +1,28 @@
# Changelog
All notable changes to this project are documented in this file.
## [2.10.0] - 2022-10-25
### Added
- Added NRFX_CONFIG_API_VER_2_9 and NRFX_CONFIG_API_VER_2_10 symbols that guard API-breaking changes. Deprecated API is used by default.
- Added new signature for the event handler in the IPC driver that accepts event index instead of event bitmask. The previous signature is deprecated.
- Added nrfx_ipc_gpmem_get() function that is used to get data from the GPMEM register in IPC. It should be now used instead of nrfx_ipc_mem_get(), which is deprecated.
- Added samples for the following drivers: EGU, PWM, RNG, SAADC, SPIM, SPIS, TEMP, TIMER, TWIM, TWIS, UARTE. They are a part of `zephyrproject-rtos/hal_nordic/nrfx` repository.
- Introduced the NRFX_{PERIPH}_INST_HANDLER_GET() macro for getting interrupt handler associated with the specified driver instance.
- Introduced the NRFX_{PERIPH}_INST_GET() macro for getting pointer to the structure of the registers of the specified peripheral.
- Introduced the NRF_TIMER_PRESCALER_CALCULATE() macro for computing prescaler value for given TIMER base frequency and desired frequency.
- Introduced the NRF_TIMER_BASE_FREQUENCY_GET() macro for getting base frequency in Hz for the specified TIMER instance.
- Added missing NRFX_RESET_REASON_CTRLAP_MASK in nrfx_reset_reason_mask_t for nRF9160.
- Added missing NRFX_RESET_REASON_SREQ_MASK in nrfx_reset_reason_mask_t.
### Changed
- Updated MDK to version 8.51.0.
- Refactored the TIMER driver to allow user handler to be NULL.
- Removed magic numbers from nrf_twim_event_t type in TWIM HAL.
### Fixed
- Fixed the NRFX_ROUNDED_DIV() macro for negative numbers.
- Disabled array bounds warning for nrf_clock_is_running() function that was false positive in GCC 12 and above.
## [2.9.0] - 2022-07-19
### Added
- Added configuration parameter NRFX_NFCT_PARAM_ID_FDT_MIN that allows settting the value of the FRAMEDELAYMIN register.

@ -2,10 +2,10 @@ nrfx
####
Origin:
https://github.com/NordicSemiconductor/nrfx/tree/v2.9.0
https://github.com/NordicSemiconductor/nrfx/tree/v2.10.0
Status:
v2.9.0
v2.10.0
Purpose:
With added proper shims adapting it to Zephyr's APIs, nrfx will provide
@ -32,7 +32,7 @@ URL:
https://github.com/NordicSemiconductor/nrfx
commit:
16756cadac53aa72e4262dc3e17db73f6bda715c
23fb4437c08a9edfdf6d34f002322f693a15e8fe
Maintained-by:
External
@ -41,4 +41,4 @@ License:
BSD-3-Clause
License Link:
https://github.com/NordicSemiconductor/nrfx/blob/v2.9.0/LICENSE
https://github.com/NordicSemiconductor/nrfx/blob/v2.10.0/LICENSE

@ -40,7 +40,7 @@ PROJECT_NAME = "nrfx"
### EDIT THIS ###
PROJECT_NUMBER = "2.9"
PROJECT_NUMBER = "2.10"
# Using the PROJECT_BRIEF tag one can provide an optional one line description
# for a project that appears at the top of each page and should give viewer a
@ -2077,15 +2077,7 @@ INCLUDE_FILE_PATTERNS =
# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
PREDEFINED = SUPPRESS_INLINE_IMPLEMENTATION \
__NRFX_DOXYGEN__ \
CONFIG_PURGE_ENABLED=1 \
CONFIG_DISASSOCIATE_ENABLED=1 \
CONFIG_GTS_ENABLED=1 \
CONFIG_ORPHAN_ENABLED=1 \
CONFIG_RXE_ENABLED=1 \
CONFIG_START_ENABLED=1 \
CONFIG_SYNC_ENABLED=1 \
CONFIG_PANID_CONFLICT_ENABLED=1
__NRFX_DOXYGEN__
# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this
# tag can be used to specify a list of macro names that should be expanded. The

@ -1,4 +1,7 @@
sphinx~=3.5
sphinx-ncs-theme~=0.6.2
breathe~=4.28
m2r2~=0.2
Sphinx!=5.0.0,<6,>=4.0
sphinx-ncs-theme==0.6.5
sphinx-rtd-theme==0.5.2
breathe==4.34.0
m2r2==0.3.2
Jinja2==3.0.3
docutils<0.17

@ -253,7 +253,8 @@ void nrfx_clock_calibration_timer_start(uint8_t interval);
/** @brief Function for stopping the calibration timer. */
void nrfx_clock_calibration_timer_stop(void);
/**@brief Function for returning a requested task address for the clock driver module.
/**
* @brief Function for returning a requested task address for the clock driver module.
*
* @param[in] task One of the peripheral tasks.
*
@ -261,7 +262,8 @@ void nrfx_clock_calibration_timer_stop(void);
*/
NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_task_addr(nrf_clock_task_t task);
/**@brief Function for returning a requested event address for the clock driver module.
/**
* @brief Function for returning a requested event address for the clock driver module.
*
* @param[in] event One of the peripheral events.
*

@ -143,6 +143,15 @@ void nrfx_egu_trigger(nrfx_egu_t const * p_instance, uint8_t event_idx);
*/
void nrfx_egu_uninit(nrfx_egu_t const * p_instance);
/**
* @brief Macro returning EGU interrupt handler.
*
* param[in] idx EGU index.
*
* @return Interrupt handler.
*/
#define NRFX_EGU_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_egu_, idx, _irq_handler)
/** @} */
void nrfx_egu_0_irq_handler(void);

@ -47,13 +47,25 @@ extern "C" {
* @brief Interprocessor Communication (IPC) peripheral driver.
*/
#if NRFX_CHECK(NRFX_CONFIG_API_VER_2_10) || defined(__NRFX_DOXYGEN__)
/**
* @brief IPC driver handler type.
*
* @param[in] event_idx IPC event index.
* @param[in] p_context Context passed to the interrupt handler, set on initialization.
*/
typedef void (*nrfx_ipc_handler_t)(uint8_t event_idx, void * p_context);
#elif NRFX_CHECK(NRFX_CONFIG_API_VER_2_9)
/**
* @brief IPC driver handler type.
*
* @note This function is deprecated. Use @ref NRFX_CONFIG_API_VER_2_10 variant instead.
*
* @param[in] event_mask Bitmask with events that triggered the interrupt.
* @param[in] p_context Context passed to the interrupt handler, set on initialization.
*/
typedef void (*nrfx_ipc_handler_t)(uint32_t event_mask, void * p_context);
#endif
/** @brief IPC configuration structure. */
typedef struct
@ -67,7 +79,7 @@ typedef struct
* @brief Function for initializing the IPC driver.
*
* @param irq_priority Interrupt priority.
* @param handler Event handler provided by the user. Cannot be NULL.
* @param handler Event handler provided by the user.
* @param p_context Context passed to event handler.
*
* @retval NRFX_SUCCESS Initialization was successful.
@ -93,21 +105,34 @@ void nrfx_ipc_config_load(nrfx_ipc_config_t const * p_config);
NRFX_STATIC_INLINE void nrfx_ipc_signal(uint8_t send_index);
/**
* @brief Function for storing data in GPMEM register in the IPC peripheral.
* @brief Function for storing data in the general purpose memory register.
*
* @param mem_index Index of the memory cell.
* @param data Data to be saved.
*/
NRFX_STATIC_INLINE void nrfx_ipc_gpmem_set(uint8_t mem_index, uint32_t data);
#if NRFX_CHECK(NRFX_CONFIG_API_VER_2_10) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for getting data from the general purpose memory register.
*
* @param mem_index Index of the memory cell.
*
* @return Saved data.
*/
NRFX_STATIC_INLINE uint32_t nrfx_ipc_gpmem_get(uint8_t mem_index);
#elif NRFX_CHECK(NRFX_CONFIG_API_VER_2_9)
/**
* @brief Function for getting data from the GPMEM register in the IPC peripheral.
*
* @note This function is deprecated. Use @ref nrfx_ipc_gpmem_get instead.
*
* @param mem_index Index of the memory cell.
*
* @return Saved data.
*/
NRFX_STATIC_INLINE uint32_t nrfx_ipc_mem_get(uint8_t mem_index);
#endif
/** @brief Function for uninitializing the IPC module. */
void nrfx_ipc_uninit(void);
@ -183,7 +208,11 @@ NRFX_STATIC_INLINE void nrfx_ipc_gpmem_set(uint8_t mem_index, uint32_t data)
nrf_ipc_gpmem_set(NRF_IPC, mem_index, data);
}
#if NRFX_CHECK(NRFX_CONFIG_API_VER_2_10)
NRFX_STATIC_INLINE uint32_t nrfx_ipc_gpmem_get(uint8_t mem_index)
#elif NRFX_CHECK(NRFX_CONFIG_API_VER_2_9)
NRFX_STATIC_INLINE uint32_t nrfx_ipc_mem_get(uint8_t mem_index)
#endif
{
NRFX_ASSERT(mem_index < NRFX_ARRAY_SIZE(NRF_IPC->GPMEM));
return nrf_ipc_gpmem_get(NRF_IPC, mem_index);

@ -483,6 +483,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_pwm_event_address_get(nrfx_pwm_t const * p_inst
}
#endif // NRFX_DECLARE_ONLY
/**
* @brief Macro returning PWM interrupt handler.
*
* param[in] idx PWM index.
*
* @return Interrupt handler.
*/
#define NRFX_PWM_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_pwm_, idx, _irq_handler)
/** @} */

@ -361,6 +361,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_rtc_event_address_get(nrfx_rtc_t const * p_inst
}
#endif // NRFX_DECLARE_ONLY
/**
* @brief Macro returning RTC interrupt handler.
*
* param[in] idx RTC index.
*
* @return Interrupt handler.
*/
#define NRFX_RTC_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_rtc_, idx, _irq_handler)
/** @} */

@ -328,8 +328,10 @@ nrfx_err_t nrfx_saadc_simple_mode_set(uint32_t channel_mask,
* @retval NRFX_SUCCESS Initialization was successful.
* @retval NRFX_ERROR_BUSY There is a conversion or calibration ongoing.
* @retval NRFX_ERROR_INVALID_PARAM Attempt to activate channel that is not configured.
* @retval NRFX_ERROR_NOT_SUPPORTED Attempt to activate internal timer or oversampling without burst
* with multiple channels enabled.
* @retval NRFX_ERROR_NOT_SUPPORTED Attempt to activate either of the following:
* * internal timer in the blocking mode,
* * internal timer with multiple channels enabled,
* * oversampling without burst with multiple channels enabled.
*/
nrfx_err_t nrfx_saadc_advanced_mode_set(uint32_t channel_mask,
nrf_saadc_resolution_t resolution,

@ -271,6 +271,15 @@ nrfx_err_t nrfx_spi_xfer(nrfx_spi_t const * p_instance,
*/
void nrfx_spi_abort(nrfx_spi_t const * p_instance);
/**
* @brief Macro returning SPI interrupt handler.
*
* param[in] idx SPI index.
*
* @return Interrupt handler.
*/
#define NRFX_SPI_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_spi_, idx, _irq_handler)
/** @} */

@ -417,6 +417,15 @@ uint32_t nrfx_spim_end_event_get(nrfx_spim_t const * p_instance);
*/
void nrfx_spim_abort(nrfx_spim_t const * p_instance);
/**
* @brief Macro returning SPIM interrupt handler.
*
* param[in] idx SPIM index.
*
* @return Interrupt handler.
*/
#define NRFX_SPIM_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_spim_, idx, _irq_handler)
/** @} */

@ -256,6 +256,15 @@ nrfx_err_t nrfx_spis_buffers_set(nrfx_spis_t const * p_instance,
uint8_t * p_rx_buffer,
size_t rx_buffer_length);
/**
* @brief Macro returning SPIS interrupt handler.
*
* param[in] idx SPIS index.
*
* @return Interrupt handler.
*/
#define NRFX_SPIS_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_spis_, idx, _irq_handler)
/** @} */

@ -131,8 +131,7 @@ typedef void (* nrfx_timer_event_handler_t)(nrf_timer_event_t event_type,
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_config Pointer to the structure with the initial configuration.
* @param[in] timer_event_handler Event handler provided by the user.
* Must not be NULL.
* @param[in] timer_event_handler Event handler provided by the user. Can be NULL.
*
* @retval NRFX_SUCCESS Initialization was successful.
* @retval NRFX_ERROR_INVALID_STATE The instance is already initialized.
@ -386,6 +385,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_timer_ms_to_ticks(nrfx_timer_t const * p_instan
}
#endif // NRFX_DECLARE_ONLY
/**
* @brief Macro returning TIMER interrupt handler.
*
* param[in] idx TIMER index.
*
* @return Interrupt handler.
*/
#define NRFX_TIMER_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_timer_, idx, _irq_handler)
/** @} */

@ -349,6 +349,15 @@ NRFX_STATIC_INLINE nrfx_err_t nrfx_twi_bus_recover(uint32_t scl_pin, uint32_t sd
}
#endif
/**
* @brief Macro returning TWI interrupt handler.
*
* param[in] idx TWI index.
*
* @return Interrupt handler.
*/
#define NRFX_TWI_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_twi_, idx, _irq_handler)
/** @} */

@ -389,6 +389,15 @@ NRFX_STATIC_INLINE nrfx_err_t nrfx_twim_bus_recover(uint32_t scl_pin, uint32_t s
}
#endif
/**
* @brief Macro returning TWIM interrupt handler.
*
* param[in] idx TWIM index.
*
* @return Interrupt handler.
*/
#define NRFX_TWIM_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_twim_, idx, _irq_handler)
/** @} */
void nrfx_twim_0_irq_handler(void);

@ -404,6 +404,15 @@ NRFX_STATIC_INLINE size_t nrfx_twis_rx_amount(nrfx_twis_t const * p_instance)
}
#endif // NRFX_DECLARE_ONLY
/**
* @brief Macro returning TWIS interrupt handler.
*
* param[in] idx TWIS index.
*
* @return Interrupt handler.
*/
#define NRFX_TWIS_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_twis_, idx, _irq_handler)
/** @} */

@ -384,6 +384,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_uart_event_address_get(nrfx_uart_t const * p_in
}
#endif // NRFX_DECLARE_ONLY
/**
* @brief Macro returning UART interrupt handler.
*
* param[in] idx UART index.
*
* @return Interrupt handler.
*/
#define NRFX_UART_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_uart_, idx, _irq_handler)
/** @} */

@ -399,6 +399,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_uarte_event_address_get(nrfx_uarte_t const * p_
}
#endif // NRFX_DECLARE_ONLY
/**
* @brief Macro returning UARTE interrupt handler.
*
* param[in] idx UARTE index.
*
* @return Interrupt handler.
*/
#define NRFX_UARTE_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_uarte_, idx, _irq_handler)
/** @} */

@ -87,7 +87,7 @@ enum {
.drv_inst_idx = NRFX_CONCAT_3(NRFX_WDT, id, _INST_IDX), \
}
/**@brief Struct for WDT initialization. */
/** @brief Struct for WDT initialization. */
typedef struct
{
nrf_wdt_behaviour_t behaviour; /**< WDT behaviour when CPU in sleep/halt mode. */
@ -205,6 +205,15 @@ NRFX_STATIC_INLINE uint32_t nrfx_wdt_event_address_get(nrfx_wdt_t const * p_inst
}
#endif // NRFX_DECLARE_ONLY
/**
* @brief Macro returning WDT interrupt handler.
*
* param[in] idx WDT index.
*
* @return Interrupt handler.
*/
#define NRFX_WDT_INST_HANDLER_GET(idx) NRFX_CONCAT_3(nrfx_wdt_, idx, _irq_handler)
/** @} */

@ -177,7 +177,8 @@ extern "C" {
*
* @return Rounded (integer) result of dividing @c a by @c b.
*/
#define NRFX_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b))
#define NRFX_ROUNDED_DIV(a, b) \
((((a) < 0) ^ ((b) < 0)) ? (((a) - (b) / 2) / (b)) : (((a) + (b) / 2) / (b)))
/**
* @brief Macro for performing integer division, making sure the result is rounded up.
@ -212,7 +213,8 @@ extern "C" {
*/
#define NRFX_OFFSETOF(type, member) ((size_t)&(((type *)0)->member))
/**@brief Macro for checking if given lengths of EasyDMA transfers do not exceed
/**
* @brief Macro for checking if given lengths of EasyDMA transfers do not exceed
* the limit of the specified peripheral.
*
* @param[in] peripheral Peripheral to check the lengths against.

@ -127,7 +127,7 @@ typedef enum
} nrfx_clock_cal_state_t;
#endif
/**@brief CLOCK control block. */
/** @brief CLOCK control block. */
typedef struct
{
nrfx_clock_event_handler_t event_handler;

@ -49,7 +49,6 @@ static ipc_control_block_t m_ipc_cb;
nrfx_err_t nrfx_ipc_init(uint8_t irq_priority, nrfx_ipc_handler_t handler, void * p_context)
{
NRFX_ASSERT(handler);
if (m_ipc_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
{
return NRFX_ERROR_ALREADY_INITIALIZED;
@ -147,18 +146,26 @@ void nrfx_ipc_irq_handler(void)
{
// Get the information about events that fire this interrupt
uint32_t events_map = nrf_ipc_int_pending_get(NRF_IPC);
// Clear these events
uint32_t bitmask = events_map;
while (bitmask)
{
uint8_t event_idx = NRF_CTZ(bitmask);
bitmask &= ~(1UL << event_idx);
nrf_ipc_event_clear(NRF_IPC, nrf_ipc_receive_event_get(event_idx));
#if NRFX_CHECK(NRFX_CONFIG_API_VER_2_10)
if (m_ipc_cb.handler)
{
m_ipc_cb.handler(event_idx, m_ipc_cb.p_context);
}
#elif NRFX_CHECK(NRFX_CONFIG_API_VER_2_9)
}
if (m_ipc_cb.handler)
{
m_ipc_cb.handler(events_map, m_ipc_cb.p_context);
#endif
}
// Execute interrupt handler to provide information about events to app
m_ipc_cb.handler(events_map, m_ipc_cb.p_context);
}
#endif // NRFX_CHECK(NRFX_IPC_ENABLED)

@ -136,7 +136,7 @@ typedef enum
NRFX_NFC_FIELD_STATE_UNKNOWN /**< Both NFCT field events have been set - ambiguous state. */
} nrfx_nfct_field_state_t;
/**@brief NFCT control block. */
/** @brief NFCT control block. */
typedef struct
{
nrfx_nfct_config_t config;
@ -175,7 +175,7 @@ static void nrfx_nfct_frame_delay_max_set(bool default_delay)
}
}
/**@brief Function for evaluating and handling the NFC field events.
/** @brief Function for evaluating and handling the NFC field events.
*
* @param[in] field_state Current field state.
*/

@ -55,7 +55,7 @@
"UNKNOWN EVENT"))))))
/**@brief RTC driver instance control block structure. */
/** @brief RTC driver instance control block structure. */
typedef struct
{
nrfx_drv_state_t state; /**< Instance state. */

@ -101,7 +101,7 @@ static void csn_event_handler(nrfx_gpiote_pin_t pin,
#endif
/**@brief States of the SPI transaction state machine. */
/** @brief States of the SPI transaction state machine. */
typedef enum
{
SPIS_STATE_INIT, /**< Initialization state. In this state the module waits for a call to @ref spi_slave_buffers_set. */
@ -110,7 +110,7 @@ typedef enum
SPIS_XFER_COMPLETED /**< State where SPI transaction has been completed. */
} nrfx_spis_state_t;
/**@brief SPIS control block - driver instance local data. */
/** @brief SPIS control block - driver instance local data. */
typedef struct
{
volatile uint32_t tx_buffer_size; //!< SPI slave TX buffer size in bytes.
@ -344,7 +344,7 @@ void nrfx_spis_uninit(nrfx_spis_t const * p_instance)
}
/**@brief Function for executing the state entry action. */
/** @brief Function for executing the state entry action. */
static void spis_state_entry_action_execute(NRF_SPIS_Type * p_spis,
spis_cb_t * p_cb)
{
@ -383,7 +383,7 @@ static void spis_state_entry_action_execute(NRF_SPIS_Type * p_spis,
}
}
/**@brief Function for changing the state of the SPI state machine.
/** @brief Function for changing the state of the SPI state machine.
*
* @param[in] p_spis SPIS instance register.
* @param[in] p_cb SPIS instance control block.

@ -62,7 +62,7 @@
#define NRFX_LOG_MODULE TIMER
#include <nrfx_log.h>
/**@brief Timer control block. */
/** @brief Timer control block. */
typedef struct
{
nrfx_timer_event_handler_t handler;
@ -81,7 +81,6 @@ nrfx_err_t nrfx_timer_init(nrfx_timer_t const * p_instance,
NRFX_ASSERT(p_instance->p_reg != NRF_TIMER0);
#endif
NRFX_ASSERT(p_config);
NRFX_ASSERT(timer_event_handler);
nrfx_err_t err_code;
@ -112,7 +111,8 @@ nrfx_err_t nrfx_timer_init(nrfx_timer_t const * p_instance,
nrf_timer_mode_set(p_instance->p_reg, p_config->mode);
nrf_timer_bit_width_set(p_instance->p_reg, p_config->bit_width);
nrf_timer_frequency_set(p_instance->p_reg, p_config->frequency);
// nrf_timer_frequency_t is mapped to prescaler for 16MHz base clock frequency timers
nrf_timer_prescaler_set(p_instance->p_reg, (uint32_t)p_config->frequency);
p_cb->state = NRFX_DRV_STATE_INITIALIZED;
@ -282,7 +282,10 @@ static void irq_handler(NRF_TIMER_Type * p_reg,
{
nrf_timer_event_clear(p_reg, event);
NRFX_LOG_DEBUG("Compare event, channel: %d.", i);
p_cb->handler(event, p_cb->context);
if (p_cb->handler)
{
p_cb->handler(event, p_cb->context);
}
}
}
}

@ -42,6 +42,10 @@ extern "C" {
#define NRFX_EVENT_READBACK_ENABLED 1
#endif
#if !defined(NRFX_CONFIG_API_VER_2_9) && !defined(NRFX_CONFIG_API_VER_2_10)
#define NRFX_CONFIG_API_VER_2_9 1
#endif
#if defined(NRFX_CLZ)
#define NRF_CLZ(value) NRFX_CLZ(value)
#else

@ -47,6 +47,15 @@ extern "C" {
* @brief Hardware access layer for managing the Event Generator Unit (EGU) peripheral.
*/
/**
* @brief Macro getting pointer to the structure of registers of the EGU peripheral.
*
* @param[in] idx EGU instance index.
*
* @return Pointer to the structure of registers of the EGU peripheral.
*/
#define NRF_EGU_INST_GET(idx) NRFX_CONCAT_2(NRF_EGU, idx)
/** @brief EGU tasks. */
typedef enum
{

@ -47,6 +47,15 @@ extern "C" {
* @brief Hardware access layer for managing the Pulse Width Modulation (PWM) peripheral.
*/
/**
* @brief Macro getting pointer to the structure of registers of the PWM peripheral.
*
* @param[in] idx PWM instance index.
*
* @return Pointer to the structure of registers of the PWM peripheral.
*/
#define NRF_PWM_INST_GET(idx) NRFX_CONCAT_2(NRF_PWM, idx)
/**
* @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set
* function call to specify that a given output channel shall not be

@ -47,6 +47,15 @@ extern "C" {
* @brief Hardware access layer for managing the Real Time Counter (RTC) peripheral.
*/
/**
* @brief Macro getting pointer to the structure of registers of the RTC peripheral.
*
* @param[in] idx RTC instance index.
*
* @return Pointer to the structure of registers of the RTC peripheral.
*/
#define NRF_RTC_INST_GET(idx) NRFX_CONCAT_2(NRF_RTC, idx)
/** @brief Macro for getting the number of compare channels available in a given RTC instance. */
#define NRF_RTC_CC_CHANNEL_COUNT(id) NRFX_CONCAT_3(RTC, id, _CC_NUM)

@ -47,6 +47,15 @@ extern "C" {
* @brief Hardware access layer for managing the SPI peripheral.
*/
/**
* @brief Macro getting pointer to the structure of registers of the SPI peripheral.
*
* @param[in] idx SPI instance index.
*
* @return Pointer to the structure of registers of the SPI peripheral.
*/
#define NRF_SPI_INST_GET(idx) NRFX_CONCAT_2(NRF_SPI, idx)
/**
* @brief This value can be used as a parameter for the @ref nrf_spi_pins_set
* function to specify that a given SPI signal (SCK, MOSI, or MISO)

@ -47,6 +47,15 @@ extern "C" {
* @brief Hardware access layer for managing the SPIM peripheral.
*/
/**
* @brief Macro getting pointer to the structure of registers of the SPIM peripheral.
*
* @param[in] idx SPIM instance index.
*
* @return Pointer to the structure of registers of the SPIM peripheral.
*/
#define NRF_SPIM_INST_GET(idx) NRFX_CONCAT_2(NRF_SPIM, idx)
#if defined(SPIM_FREQUENCY_FREQUENCY_M32) || defined(__NRFX_DOXYGEN__)
/** @brief Symbol indicating whether 32 MHz clock frequency is available. */
#define NRF_SPIM_HAS_32_MHZ_FREQ 1

@ -47,6 +47,15 @@ extern "C" {
* @brief Hardware access layer for managing the SPIS peripheral.
*/
/**
* @brief Macro getting pointer to the structure of registers of the SPIS peripheral.
*
* @param[in] idx SPIS instance index.
*
* @return Pointer to the structure of registers of the SPIS peripheral.
*/
#define NRF_SPIS_INST_GET(idx) NRFX_CONCAT_2(NRF_SPIS, idx)
/**
* @brief This value can be used as a parameter for the @ref nrf_spis_pins_set
* function to specify that a given SPI signal (SCK, MOSI, or MISO)

@ -47,6 +47,15 @@ extern "C" {
* @brief Hardware access layer for managing the TIMER peripheral.
*/
/**
* @brief Macro getting pointer to the structure of registers of the TIMER peripheral.
*
* @param[in] idx TIMER instance index.
*
* @return Pointer to the structure of registers of the TIMER peripheral.
*/
#define NRF_TIMER_INST_GET(idx) NRFX_CONCAT_2(NRF_TIMER, idx)
#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__)
/** @brief Symbol indicating whether timer has capture/compare channel 4. */
#define NRF_TIMER_HAS_CC4 1
@ -89,6 +98,9 @@ extern "C" {
#define NRF_TIMER_HAS_ONE_SHOT 0
#endif
/** @brief Base frequency value 16 MHz for timer. */
#define NRF_TIMER_BASE_FREQUENCY_16MHZ (16000000UL)
/** @brief Maximum value of PRESCALER register. */
#define NRF_TIMER_PRESCALER_MAX 9
@ -154,6 +166,24 @@ extern "C" {
#error "Not supported timer count"
#endif
/**
* @brief Macro for getting base frequency value in Hz for the specified timer.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
#define NRF_TIMER_BASE_FREQUENCY_GET(p_reg) NRF_TIMER_BASE_FREQUENCY_16MHZ
/**
* @brief Macro for computing prescaler value for given base frequency and desired frequency.
*
* @warning Not every combination of base frequency and desired frequency is supported.
*
* @param[in] base_freq Base clock frequency for timer in Hz.
* @param[in] frequency Desired frequency value in Hz.
*/
#define NRF_TIMER_PRESCALER_CALCULATE(base_freq, frequency) \
NRF_CTZ((uint32_t)(base_freq) / (uint32_t)(frequency))
/**
* @brief Macro for getting the number of capture/compare channels available
* in a given timer instance.

@ -47,6 +47,15 @@ extern "C" {
* @brief Hardware access layer for managing the TWI peripheral.
*/
/**
* @brief Macro getting pointer to the structure of registers of the TWI peripheral.
*
* @param[in] idx TWI instance index.
*
* @return Pointer to the structure of registers of the TWI peripheral.
*/
#define NRF_TWI_INST_GET(idx) NRFX_CONCAT_2(NRF_TWI, idx)
/** @brief TWI tasks. */
typedef enum
{

@ -47,6 +47,15 @@ extern "C" {
* @brief Hardware access layer for managing the TWIM peripheral.
*/
/**
* @brief Macro getting pointer to the structure of registers of the TWIM peripheral.
*
* @param[in] idx TWIM instance index.
*
* @return Pointer to the structure of registers of the TWIM peripheral.
*/
#define NRF_TWIM_INST_GET(idx) NRFX_CONCAT_2(NRF_TWIM, idx)
#if defined(TWIM_FREQUENCY_FREQUENCY_K1000) || defined(__NRFX_DOXYGEN__)
/** @brief Symbol indicating whether 1000 kHz clock frequency is available. */
#define NRF_TWIM_HAS_1000_KHZ_FREQ 1
@ -69,7 +78,7 @@ typedef enum
{
NRF_TWIM_EVENT_STOPPED = offsetof(NRF_TWIM_Type, EVENTS_STOPPED), ///< TWI stopped.
NRF_TWIM_EVENT_ERROR = offsetof(NRF_TWIM_Type, EVENTS_ERROR), ///< TWI error.
NRF_TWIM_EVENT_SUSPENDED = 0x148, ///< TWI suspended.
NRF_TWIM_EVENT_SUSPENDED = offsetof(NRF_TWIM_Type, EVENTS_SUSPENDED), ///< TWI suspended.
NRF_TWIM_EVENT_RXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_RXSTARTED), ///< Receive sequence started.
NRF_TWIM_EVENT_TXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_TXSTARTED), ///< Transmit sequence started.
NRF_TWIM_EVENT_LASTRX = offsetof(NRF_TWIM_Type, EVENTS_LASTRX), ///< Byte boundary, starting to receive the last byte.

@ -48,6 +48,15 @@ extern "C" {
* (TWIS) peripheral.
*/
/**
* @brief Macro getting pointer to the structure of registers of the TWIS peripheral.
*
* @param[in] idx TWIS instance index.
*
* @return Pointer to the structure of registers of the TWIS peripheral.
*/
#define NRF_TWIS_INST_GET(idx) NRFX_CONCAT_2(NRF_TWIS, idx)
/** @brief TWIS tasks. */
typedef enum
{

@ -49,6 +49,15 @@ extern "C" {
* @brief Hardware access layer for managing the UARTE peripheral.
*/
/**
* @brief Macro getting pointer to the structure of registers of the UARTE peripheral.
*
* @param[in] idx UARTE instance index.
*
* @return Pointer to the structure of registers of the UARTE peripheral.
*/
#define NRF_UARTE_INST_GET(idx) NRFX_CONCAT_2(NRF_UARTE, idx)
/** @brief UARTE tasks. */
typedef enum
{

@ -51,6 +51,15 @@ extern "C" {
* @brief Hardware access layer for managing the Watchdog Timer (WDT) peripheral.
*/
/**
* @brief Macro getting pointer to the structure of registers of the WDT peripheral.
*
* @param[in] idx WDT instance index.
*
* @return Pointer to the structure of registers of the WDT peripheral.
*/
#define NRF_WDT_INST_GET(idx) NRFX_CONCAT_2(NRF_WDT, idx)
/** @brief Number of WDT channels. */
#define NRF_WDT_CHANNEL_NUMBER 0x8UL

@ -59,46 +59,48 @@ extern "C" {
typedef enum
{
#if !NRF_POWER_HAS_RESETREAS || defined(__NRFX_DOXYGEN__)
NRFX_RESET_REASON_RESETPIN_MASK = RESET_RESETREAS_RESETPIN_Msk,
/**< Reset from pin-reset detected. */
NRFX_RESET_REASON_RESETPIN_MASK = RESET_RESETREAS_RESETPIN_Msk,
/**< Reset from watchdog/application watchdog timer 0 detected. */
NRFX_RESET_REASON_DOG0_MASK = RESET_RESETREAS_DOG0_Msk,
/**< Reset from watchdog/application watchdog timer 0 detected. */
NRFX_RESET_REASON_DOG_MASK = NRFX_RESET_REASON_DOG0_MASK,
/**< Reset from watchdog/application watchdog timer 0 detected. */
NRFX_RESET_REASON_CTRLAP_MASK = RESET_RESETREAS_CTRLAP_Msk,
/**< Reset from application CTRL-AP detected. */
NRFX_RESET_REASON_CTRLAP_MASK = RESET_RESETREAS_CTRLAP_Msk,
/**< Reset from soft reset/application soft reset detected. Deprecated. */
NRFX_RESETREAS_SREQ_MASK = RESET_RESETREAS_SREQ_Msk,
/**< Reset from soft reset/application soft reset detected. */
NRFX_RESET_REASON_LOCKUP_MASK = RESET_RESETREAS_LOCKUP_Msk,
NRFX_RESET_REASON_SREQ_MASK = RESET_RESETREAS_SREQ_Msk,
/**< Reset from CPU lockup/application CPU lockup detected. */
NRFX_RESET_REASON_OFF_MASK = RESET_RESETREAS_OFF_Msk,
NRFX_RESET_REASON_LOCKUP_MASK = RESET_RESETREAS_LOCKUP_Msk,
/**< Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from
* GPIO. */
NRFX_RESET_REASON_LPCOMP_MASK = RESET_RESETREAS_LPCOMP_Msk,
NRFX_RESET_REASON_OFF_MASK = RESET_RESETREAS_OFF_Msk,
/**< Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from
* LPCOMP. */
NRFX_RESET_REASON_DIF_MASK = RESET_RESETREAS_DIF_Msk,
NRFX_RESET_REASON_LPCOMP_MASK = RESET_RESETREAS_LPCOMP_Msk,
/**< Reset due to wakeup from System OFF mode when wakeup is triggered by entering the debug
* interface mode. */
NRFX_RESET_REASON_DIF_MASK = RESET_RESETREAS_DIF_Msk,
#if NRF_RESET_HAS_NETWORK
NRFX_RESET_REASON_LSREQ_MASK = RESET_RESETREAS_LSREQ_Msk,
/**< Reset from network soft reset detected. */
NRFX_RESET_REASON_LLOCKUP_MASK = RESET_RESETREAS_LLOCKUP_Msk,
NRFX_RESET_REASON_LSREQ_MASK = RESET_RESETREAS_LSREQ_Msk,
/**< Reset from network CPU lockup detected. */
NRFX_RESET_REASON_LDOG_MASK = RESET_RESETREAS_LDOG_Msk,
NRFX_RESET_REASON_LLOCKUP_MASK = RESET_RESETREAS_LLOCKUP_Msk,
/**< Reset from network watchdog timer detected. */
NRFX_RESET_REASON_MFORCEOFF_MASK = RESET_RESETREAS_MFORCEOFF_Msk,
NRFX_RESET_REASON_LDOG_MASK = RESET_RESETREAS_LDOG_Msk,
/**< Force off reset from application core detected. */
NRFX_RESET_REASON_MFORCEOFF_MASK = RESET_RESETREAS_MFORCEOFF_Msk,
#endif // NRF_RESET_HAS_NETWORK
/**< Reset after wakeup from System OFF mode due to NFC field being detected. */
NRFX_RESET_REASON_NFC_MASK = RESET_RESETREAS_NFC_Msk,
/**< Reset after wakeup from System OFF mode due to NRF field being detected. */
NRFX_RESET_REASON_DOG1_MASK = RESET_RESETREAS_DOG1_Msk,
/**< Reset from application watchdog timer 1 detected. */
NRFX_RESET_REASON_VBUS_MASK = RESET_RESETREAS_VBUS_Msk,
NRFX_RESET_REASON_DOG1_MASK = RESET_RESETREAS_DOG1_Msk,
/**< Reset after wakeup from System OFF mode due to VBUS rising into valid range. */
NRFX_RESET_REASON_VBUS_MASK = RESET_RESETREAS_VBUS_Msk,
#if NRF_RESET_HAS_NETWORK
NRFX_RESET_REASON_LCTRLAP_MASK = RESET_RESETREAS_LCTRLAP_Msk,
/**< Reset from network CTRL-AP detected. */
NRFX_RESET_REASON_LCTRLAP_MASK = RESET_RESETREAS_LCTRLAP_Msk,
#endif // NRF_RESET_HAS_NETWORK
#else
NRFX_RESET_REASON_RESETPIN_MASK = POWER_RESETREAS_RESETPIN_Msk,
@ -106,6 +108,9 @@ typedef enum
NRFX_RESET_REASON_SREQ_MASK = POWER_RESETREAS_SREQ_Msk ,
NRFX_RESET_REASON_LOCKUP_MASK = POWER_RESETREAS_LOCKUP_Msk,
NRFX_RESET_REASON_OFF_MASK = POWER_RESETREAS_OFF_Msk,
#if defined(POWER_RESETREAS_CTRLAP_Msk)
NRFX_RESET_REASON_CTRLAP_MASK = POWER_RESETREAS_CTRLAP_Msk,
#endif
#if defined(POWER_RESETREAS_LPCOMP_Msk)
NRFX_RESET_REASON_LPCOMP_MASK = POWER_RESETREAS_LPCOMP_Msk,
#endif

@ -57,7 +57,7 @@ POSSIBILITY OF SUCH DAMAGE.
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __ALIGN
#define __ALIGN(n) __align(n)
#endif
@ -72,6 +72,10 @@ POSSIBILITY OF SUCH DAMAGE.
#define GET_SP() __current_sp()
#ifndef __DEPRECATED
#define __DEPRECATED(msg) __attribute__((deprecated(msg)))
#endif
#ifndef NRF_STATIC_ASSERT
#define NRF_STATIC_ASSERT(cond, msg) \
;enum { NRF_STRING_CONCATENATE(static_assert_on_line_, __LINE__) = 1 / (!!(cond)) }
@ -105,6 +109,10 @@ POSSIBILITY OF SUCH DAMAGE.
#define GET_SP() __current_sp()
#ifndef __DEPRECATED
#define __DEPRECATED(msg) __attribute__((deprecated(msg)))
#endif
#ifndef NRF_STATIC_ASSERT
#ifdef __cplusplus
#ifndef _Static_assert
@ -153,6 +161,10 @@ POSSIBILITY OF SUCH DAMAGE.
#define GET_SP() __get_SP()
#ifndef __DEPRECATED
#define __DEPRECATED(msg) __attribute__((deprecated(msg)))
#endif
#ifndef NRF_STATIC_ASSERT
#define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
#endif
@ -185,6 +197,10 @@ POSSIBILITY OF SUCH DAMAGE.
#define GET_SP() gcc_current_sp()
#ifndef __DEPRECATED
#define __DEPRECATED(msg) __attribute__((deprecated(msg)))
#endif
static inline unsigned int gcc_current_sp(void)
{
unsigned int stack_pointer = 0;
@ -230,6 +246,10 @@ POSSIBILITY OF SUCH DAMAGE.
#define GET_SP() __get_MSP()
#ifndef __DEPRECATED
#define __DEPRECATED(msg)
#endif
#ifndef NRF_STATIC_ASSERT
#define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
#endif

@ -37,7 +37,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* MDK version */
#define MDK_MAJOR_VERSION 8
#define MDK_MINOR_VERSION 47
#define MDK_MINOR_VERSION 51
#define MDK_MICRO_VERSION 0

@ -1,41 +1,41 @@
/*
* Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.\n
\n
SPDX-License-Identifier: BSD-3-Clause\n
\n
Redistribution and use in source and binary forms, with or without\n
modification, are permitted provided that the following conditions are met:\n
\n
1. Redistributions of source code must retain the above copyright notice, this\n
list of conditions and the following disclaimer.\n
\n
2. Redistributions in binary form must reproduce the above copyright\n
notice, this list of conditions and the following disclaimer in the\n
documentation and/or other materials provided with the distribution.\n
\n
3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
contributors may be used to endorse or promote products derived from this\n
software without specific prior written permission.\n
\n
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
POSSIBILITY OF SUCH DAMAGE.\n
*
* @file nrf51.h
* @brief CMSIS HeaderFile
* @version 522
* @date 11. May 2022
* @note Generated by SVDConv V3.3.35 on Wednesday, 11.05.2022 12:25:35
* @date 19. October 2022
* @note Generated by SVDConv V3.3.35 on Wednesday, 19.10.2022 11:23:46
* from File 'nrf51.svd',
* last modified on Wednesday, 11.05.2022 10:25:34
* last modified on Wednesday, 19.10.2022 09:13:55
*/
@ -112,6 +112,7 @@ typedef enum {
/* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */
#define __CM0_REV 0x0301U /*!< CM0 Core Revision */
#define __INTERRUPTS_MAX 32 /*!< Top interrupt number */
#define __DSP_PRESENT 0 /*!< DSP present or not */
#define __VTOR_PRESENT 0 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */

@ -171,6 +171,19 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk
#endif
/* UART */
#ifndef PSELRTS
#define PSELRTS PSEL.RTS
#endif
#ifndef PSELTXD
#define PSELTXD PSEL.TXD
#endif
#ifndef PSELCTS
#define PSELCTS PSEL.CTS
#endif
#ifndef PSELRXD
#define PSELRXD PSEL.RXD
#endif
/* From nrf51_deprecated.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */

@ -1,28 +1,41 @@
/*
* Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.SPDX-License-Identifier: BSD
* -3-ClauseRedistribution and use in source and binary forms, with or withoutmodification, are permitt
* ed provided that the following conditions are met:1. Redistributions of source code must retain the
* above copyright notice, this list of conditions and the following disclaimer.2. Redistributions in b
* inary form must reproduce the above copyright notice, this list of conditions and the following disc
* laimer in the documentation and/or other materials provided with the distribution.3. Neither the nam
* e of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote pr
* oducts derived from this software without specific prior written permission.THIS SOFTWARE IS PROVIDE
* D BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
* BUT NOT LIMITED TO, THEIMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSEA
* RE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BELIABLE FOR ANY DIRECT, I
* NDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, ORCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PRO
* CUREMENT OFSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESSINTERRUPTION) HOW
* EVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER INCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEP
* OSSIBILITY OF SUCH DAMAGE.
Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*
* @file nrf52.h
* @brief CMSIS HeaderFile
* @version 1