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ext : hal : mec1501 Add the MEC1501 external headers. 

Origin: Microchip CPG
Purpose: Peripheral firmware library for MEC1501
Version: 0.1
License: Apache
Maintained-by: External

Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit is contained in:
Scott Worley 2019-04-01 17:52:43 -04:00 committed by Andrew Boie
parent e7347ab101
commit d9ba0d14f7
28 changed files with 8684 additions and 1 deletions
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2
CMakeLists.txt
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zephyr_include_directories_ifdef(CONFIG_HAS_MEC_HAL mec)
add_subdirectory_ifdef(CONFIG_HAS_MEC_HAL mec)

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mec/CMakeLists.txt Normal file
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#
# Copyright (c) 2019, Microchip Technology Inc.
#
# SPDX-License-Identifier: Apache-2.0
#
zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_MEC1701X .)
zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_MEC1501X common)
zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_MEC1501X mec1501)

288
mec/common/mec_cpu.h Normal file
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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file cpu.h
*MEC1701 CPU abstractions
*/
/** @defgroup cpu
*/
#ifndef _CPU_H
#define _CPU_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __CC_ARM /* Keil ARM MDK */
#ifndef UINT8_C
#define UINT8_C(x) (unsigned char)(x)
#endif
#ifndef UINT16_C
#define UINT16_C(x) (unsigned int)(x)
#endif
#ifndef UINT32_C
#define UINT32_C(x) (unsigned long)(x)
#endif
#define USED __attribute__((used))
#define WEAK __attribute__((weak))
#define INLINE __inline
#define NORETURN __declspec(noreturn)
#define PACKED __packed
#define CPU_GET_INTERRUPT_STATE() __get_PRIMASK()
#define CPU_SET_INTERRUPT_STATE(x) __set_PRIMASK((x))
/*
* Keil MDK intrisic __disable_irq() returns the value of MSR PRIMASK
* before disabling interrupts.
*/
#define CPU_DISABLE_INTERRUPTS() __disable_irq()
#define CPU_GET_DISABLE_INTERRUPTS(x) {(x) = __disable_irq();}
#define CPU_RESTORE_INTERRUPTS(x) { if (!(x)) { __enable_irq(); } }
#define CPU_ENABLE_INTERRUPTS() __enable_irq()
#define CPU_NOP() __nop()
#define CPU_WAIT_FOR_INTR() __wfi()
#define CPU_REV(x) __rev(x)
#define CPU_CLZ(x) __clz(x)
/*
* The microsecond delay register is implemented in a Normal Data Memory
* Region. Normal regions have relaxed data ordering semantics. This can
* cause issues because writes to this register can complete before a
* previous write to Device or Strongly ordered memory. Please use the
* inline code after this definition. It uses the Data Synchronization
* Barrier instruction to insure all outstanding writes complete before
* the instruction after DSB is executed.
* #define MEC2016_DELAY_REG *((volatile uint8_t*) MEC2016_DELAY_REG_BASE)
*/
static inline void MICROSEC_DELAY(unsigned char n)
{
volatile unsigned long *pdly_reg;
pdly_reg = (volatile unsigned long *)0x10000000ul;
__asm volatile (
"\tstrb n, [pdly_reg]\n"
"\tldrb n, [pdly_reg]\n"
"\tadd n, #0\n"
"\tdmb\n"
);
}
#elif defined(__XC32_PART_SUPPORT_VERSION) /* Microchip XC32 compiler customized GCC */
#error "!!! FORCED BUILD ERROR: compiler.h XC32 support has not been implemented !!!"
#elif defined(__GNUC__) && defined(__ARM_EABI__) /* GCC for ARM (arm-none-eabi-gcc) */
#include <stdint.h>
#include <stddef.h>
#ifndef __always_inline
#define __always_inline inline __attribute__((always_inline))
#endif
static __always_inline void __NOP_THUMB2(void)
{
__asm volatile ("nop");
}
#define CPU_NOP() __NOP_THUMB2()
static __always_inline void __WFI_THUMB2(void)
{
__asm volatile ("dsb");
__asm volatile ("isb");
__asm volatile ("wfi");
__asm volatile ("nop");
__asm volatile ("nop");
__asm volatile ("nop");
}
#define CPU_WAIT_FOR_INTR() __WFI_THUMB2()
/* We require user have ARM CMSIS header files available and configured
* core_cmFunc.h includes inlines for global interrupt control.
* For some reason, CMSIS __disable_irq for GCC does not return current PRIMASK
* value. */
static __always_inline uint32_t __get_disable_irq(void)
{
uint32_t pri_mask;
__asm volatile (
"\tmrs %0, primask\n"
"\tcpsid i\n"
"\tdsb\n"
"\tisb\n"
: "=r" (pri_mask) :: "memory"
);
return pri_mask;
}
static __always_inline uint32_t __get_primask(void)
{
uint32_t pri_mask;
__asm volatile (
"\tmrs %0, primask\n"
"\tisb\n"
: "=r" (pri_mask) :: "memory"
);
return pri_mask;
}
static __always_inline void __enable_irqs(void)
{
__asm volatile ("cpsie i" : : : "memory");
}
static __always_inline void __disable_irqs(void)
{
__asm volatile (
"\tcpsid i\n"
"\tdsb\n"
"\tisb\n" : : : "memory");
}
#define CPU_GET_INTERRUPT_STATE() __get_primask()
#define CPU_GET_DISABLE_INTERRUPTS(x) {(x) = __get_disable_irq();}
#define CPU_RESTORE_INTERRUPTS(x) { if (!(x)) { __enable_irqs(); } }
#define CPU_ENABLE_INTERRUPTS() __enable_irqs()
#define CPU_DISABLE_INTERRUPTS() __disable_irqs()
static __always_inline uint32_t __REV_THUMB2(uint32_t u32)
{
return __builtin_bswap32(u32);
}
#define CPU_REV(x) __REV_THUMB2(x)
/*
* __builtin_clz() will not be available if user compiles with built-ins disabled flag.
*/
#define CPU_CLZ(x) __builtin_clz(x)
static inline __attribute__((always_inline, noreturn)) void CPU_JMP(uint32_t addr)
{
addr |= (1ul << 0);
__asm volatile (
"\n\t"
"\tBX %0 \n"
"\tNOP \n"
: /* no outputs */
:"r"(addr)
:);
while(1);
}
/*
* The microsecond delay register is implemented in a Normal Data Memory
* Region. Normal regions have relaxed data ordering semantics. This can
* cause issues because writes to this register can complete before a
* previous write to Device or Strongly ordered memory. Please use the
* inline code after this definition. It uses the Data Synchronization
* Barrier instruction to insure all outstanding writes complete before
* the instruction after DSB is executed.
* #define MEC2016_DELAY_REG *((volatile uint8_t*) MEC2016_DELAY_REG_BASE)
*/
static __always_inline void MICROSEC_DELAY(uint8_t n)
{
uint32_t dly_reg_addr = 0x10000000ul;
__asm volatile (
"\tstrb %0, [%1]\n"
"\tldrb %0, [%1]\n"
"\tadd %0, #0\n"
"\tdmb\n"
:
: "r" (n), "r" (dly_reg_addr)
: "memory"
);
}
static __always_inline void write_read_back8(volatile uint8_t* addr, uint8_t val)
{
__asm__ __volatile__ (
"\n\t"
"strb %1, [%0] \n\t"
"ldrb %1, [%0] \n\t"
: /* No outputs */
: "r" (addr), "r" (val)
: "memory"
);
}
static __always_inline void write_read_back16(volatile uint16_t* addr, uint16_t val)
{
__asm__ __volatile__ (
"\n\t"
"strh %1, [%0] \n\t"
"ldrh %1, [%0] \n\t"
: /* No outputs */
: "r" (addr), "r" (val)
: "memory"
);
}
static __always_inline void write_read_back32(volatile uint32_t* addr, uint32_t val)
{
__asm__ __volatile__ (
"\n\t"
"str %1, [%0] \n\t"
"ldr %1, [%0] \n\t"
: /* No outputs */
: "r" (addr), "r" (val)
: "memory"
);
}
#else /* Unknown compiler */
#error "!!! FORCED BUILD ERROR: cpu.h Unknown compiler !!!"
#endif
#endif /* #ifndef _CPU_H */
/** @}
*/

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mec/common/mec_retval.h Normal file
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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file mec_retval.h
*MEC Peripheral library return values
*/
/** @defgroup MEC Peripherals Return values
*/
#ifndef _MEC_RETVAL_H
#define _MEC_RETVAL_H
#define MCHP_RET_OK 0
#define MCHP_RET_ERR 1
#define MCHP_RET_ERR_INVAL 2 /* bad parameter */
#define MCHP_RET_ERR_BUSY 3
#define MCHP_RET_ERR_NOP 4
#define MCHP_RET_ERR_XFR 5
#define MCHP_RET_ERR_TIMEOUT 6
#define MCHP_RET_ERR_NACK 7 /* a device did not respond */
#define MCHP_RET_ERR_HW 8
#define MCHP_FALSE 0
#define MCHP_TRUE 1
#define MCHP_OFF 0
#define MCHP_ON 1
#endif // #ifndef _MEC_RETVAL_H
/* end mec_retval.h */
/** @}
*/

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mec/common/regaccess.h Normal file
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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _REGACCESS_H
#define _REGACCESS_H
#include <stdint.h>
#define MMCR32(a) *((volatile uint32_t *)(uintptr_t)(a))
#define MMCR16(a) *((volatile uint16_t *)(uintptr_t)(a))
#define MMCR8(a) *((volatile uint8_t *)(uintptr_t)(a))
#define MMCR_RD32(a, v) v = *((volatile uint32_t *)(uintptr_t)(a))
#define MMCR_RD16(a, v) v = *((volatile uint16_t *)(uintptr_t)(a))
#define MMCR_RD8(a, v) v = *((volatile uint8_t *)(uintptr_t)(a))
#define MMCR_WR32(a, d) *((volatile uint32_t *)(uintptr_t)(a)) = (uint32_t)(d)
#define MMCR_WR16(a, h) *((volatile uint16_t *)(uintptr_t)(a)) = (uint16_t)(h)
#define MMCR_WR8(a, b) *((volatile uint8_t *)(uintptr_t)(a)) = (uint8_t)(b)
#define REG32(a) *((volatile uint32_t *)(uintptr_t)(a))
#define REG16(a) *((volatile uint16_t *)(uintptr_t)(a))
#define REG8(a) *((volatile uint8_t *)(uintptr_t)(a))
#define REG32W(a, d) *((volatile uint32_t *)(uintptr_t)(a)) = (uint32_t)(d)
#define REG16W(a, h) *((volatile uint16_t *)(uintptr_t)(a)) = (uint16_t)(h)
#define REG8W(a, b) *((volatile uint8_t *)(uintptr_t)(a)) = (uint8_t)(b)
#define REG32R(a, d) (d) = *(volatile uint32_t *)(uintptr_t)(a)
#define REG16R(a, h) (h) = *(volatile uint16_t *)(uintptr_t)(a)
#define REG8R(a, b) (b) = *(volatile uint8_t *)(uintptr_t)(a)
#define REG32_OFS(a, ofs) *(volatile uint32_t *)((uintptr_t)(a) + (uintptr_t)(ofs))
#define REG16_OFS(a, ofs) *(volatile uint16_t *)((uintptr_t)(a) + (uintptr_t)(ofs))
#define REG8_OFS(a, ofs) *(volatile uint8_t *)((uintptr_t)(a) + (uintptr_t)(ofs))
#endif // #ifndef _REGACCESS_H

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mec/mec1501/MEC1501hsz.h Normal file
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/**************************************************************************//**
* @file MEC1501hsz.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
* Device Microchip MEC1501-H-SZ
* @version V5.00
* @date 03. January 2019
* Copyright (c) 2019 Microchip Technology Inc.
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
* Copyright (c) 2019 Microchip Technology Incorporated. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MEC1501HSZ_H
#define MEC1501HSZ_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup MCHP
* @{
*/
/** @addtogroup MEC1501
* @{
*/
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
typedef enum IRQn {
/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* =========================================== MEC15xx Specific Interrupt Numbers ========================================= */
GIRQ08_IRQn = 0, /*!< GPIO 0140 - 0176 */
GIRQ09_IRQn = 1, /*!< GPIO 0100 - 0136 */
GIRQ10_IRQn = 2, /*!< GPIO 0040 - 0076 */
GIRQ11_IRQn = 3, /*!< GPIO 0000 - 0036 */
GIRQ12_IRQn = 4, /*!< GPIO 0200 - 0236 */
GIRQ13_IRQn = 5, /*!< SMBus Aggregated */
GIRQ14_IRQn = 6, /*!< DMA Aggregated */
GIRQ15_IRQn = 7,
GIRQ16_IRQn = 8,
GIRQ17_IRQn = 9,
GIRQ18_IRQn = 10,
GIRQ19_IRQn = 11,
GIRQ20_IRQn = 12,
GIRQ21_IRQn = 13,
/* GIRQ22 is not connected to EC. It's purpose is peripheral clock wake */
GIRQ23_IRQn = 14,
GIRQ24_IRQn = 15,
GIRQ25_IRQn = 16,
GIRQ26_IRQn = 17, /*!< GPIO 0240 - 0276 */
/* Reserved gap, 18-19 */
/* GIRQ's 8 - 12, 24 - 26 no direct connections */
SMB0_IRQn = 20, /* GIRQ13 b[0] */
SMB1_IRQn = 21, /* GIRQ13 b[1] */
SMB2_IRQn = 22, /* GIRQ13 b[2] */
SMB3_IRQn = 23, /* GIRQ13 b[3] */
DMA0_IRQn = 24, /* GIRQ14 b[0] */
DMA1_IRQn = 25, /* GIRQ14 b[1] */
DMA2_IRQn = 26, /* GIRQ14 b[2] */
DMA3_IRQn = 27, /* GIRQ14 b[3] */
DMA4_IRQn = 28, /* GIRQ14 b[4] */
DMA5_IRQn = 29, /* GIRQ14 b[5] */
DMA6_IRQn = 30, /* GIRQ14 b[6] */
DMA7_IRQn = 31, /* GIRQ14 b[7] */
DMA8_IRQn = 32, /* GIRQ14 b[8] */
DMA9_IRQn = 33, /* GIRQ14 b[9] */
DMA10_IRQn = 34, /* GIRQ14 b[10] */
DMA11_IRQn = 35, /* GIRQ14 b[11] */
/* Reserved gap, 36-37 */
/* Reserved gap, 38-39 */
UART0_IRQn = 40, /* GIRQ15 b[0] */
UART1_IRQn = 41, /* GIRQ15 b[1] */
EMI0_IRQn = 42, /* GIRQ15 b[2] */
EMI1_IRQn = 43, /* GIRQ15 b[3] */
UART2_IRQn = 44, /* GIRQ15 b[4] */
ACPI_EC0_IBF_IRQn = 45, /* GIRQ15 b[5] */
ACPI_EC0_OBE_IRQn = 46, /* GIRQ15 b[6] */
ACPI_EC1_IBF_IRQn = 47, /* GIRQ15 b[7] */
ACPI_EC1_OBE_IRQn = 48, /* GIRQ15 b[8] */
ACPI_EC2_IBF_IRQn = 49, /* GIRQ15 b[9] */
ACPI_EC2_OBE_IRQn = 50, /* GIRQ15 b[10] */
ACPI_EC3_IBF_IRQn = 51, /* GIRQ15 b[11] */
ACPI_EC3_OBE_IRQn = 52, /* GIRQ15 b[12] */
/* Reserved gap, 53-54 */
ACPI_PM1_CTL_IRQn = 55, /* GIRQ15 b[15] */
ACPI_PM1_EN_IRQn = 56, /* GIRQ15 b[16] */
ACPI_PM1_STS_IRQn = 57, /* GIRQ15 b[17] */
KBC_OBE_IRQn = 58, /* GIRQ15 b[18] */
KBC_IBF_IRQn = 59, /* GIRQ15 b[19] */
MBOX_IRQn = 60, /* GIRQ15 b[20] */
/* reserved gap 61 */
P80CAP0_IRQn = 62, /* GIRQ15 b[22] */
P80CAP1_IRQn = 63, /* GIRQ15 b[23] */
/* reserved gap 64 */
PKE_ERR_IRQn = 65, /* GIRQ16 b[0] */
PKE_DONE_IRQn = 66, /* GIRQ16 b[1] */
RNG_IRQn = 67, /* GIRQ16 b[2] */
AES_IRQn = 68, /* GIRQ16 b[3] */
HASH_IRQn = 69, /* GIRQ16 b[4] */
PECI_IRQn = 70, /* GIRQ17 b[0] */
TACH0_IRQn = 71, /* GIRQ17 b[1] */
TACH1_IRQn = 72, /* GIRQ17 b[2] */
TACH2_IRQn = 73, /* GIRQ17 b[3] */
/* reserved gap 74-77 */
ADC_SNGL_IRQn = 78, /* GIRQ17 b[8] */
ADC_RPT_IRQn = 79, /* GIRQ17 b[9] */
/* reserved gap 80-82 */
LED0_IRQn = 83, /* GIRQ17 b[13] */
LED1_IRQn = 84, /* GIRQ17 b[14] */
LED2_IRQn = 85, /* GIRQ17 b[15] */
/* reserved gap 86 */
PHOT_IRQn = 87, /* GIRQ17 b[17] */
/* reserved gap 88-89 */
SPISLV_IRQn = 90, /* GIRQ18 b[0] */
QMSPI_IRQn = 91, /* GIRQ18 b[1] */
/* reserved gap 92-99 */
PS2_0_ACT_IRQn = 100, /* GIRQ18 b[10] */
PS2_1_ACT_IRQn = 101, /* GIRQ18 b[11] */
/* reserved gap 102 */
ESPI_PC_IRQn = 103, /* GIRQ19 b[0] */
ESPI_BM1_IRQn = 104, /* GIRQ19 b[1] */
ESPI_BM2_IRQn = 105, /* GIRQ19 b[2] */
ESPI_LTR_IRQn = 106, /* GIRQ19 b[3] */
ESPI_OOB_UP_IRQn = 107, /* GIRQ19 b[4] */
ESPI_OOB_DN_IRQn = 108, /* GIRQ19 b[5] */
ESPI_FLASH_IRQn = 109, /* GIRQ19 b[6] */
ESPI_RESET_IRQn = 110, /* GIRQ19 b[7] */
RTMR_IRQn = 111, /* GIRQ23 b[10] */
HTMR0_IRQn = 112, /* GIRQ23 b[16] */
HTMR1_IRQn = 113, /* GIRQ23 b[17] */
WK_IRQn = 114, /* GIRQ21 b[3] */
WKSUB_IRQn = 115, /* GIRQ21 b[4] */
WKSEC_IRQn = 116, /* GIRQ21 b[5] */
WKSUBSEC_IRQn = 117, /* GIRQ21 b[6] */
SYSPWR_IRQn = 118, /* GIRQ21 b[7] */
RTC_IRQn = 119, /* GIRQ21 b[8] */
RTC_ALARM_IRQn = 120, /* GIRQ21 b[9] */
VCI_OVRD_IN_IRQn = 121, /* GIRQ21 b[10] */
VCI_IN0_IRQn = 122, /* GIRQ21 b[11] */
VCI_IN1_IRQn = 123, /* GIRQ21 b[12] */
VCI_IN2_IRQn = 124, /* GIRQ21 b[13] */
VCI_IN3_IRQn = 125, /* GIRQ21 b[14] */
/* reserved 126 - 128 */
PS2_0A_WAKE_IRQn = 129, /* GIRQ21 b[18] */
PS2_0B_WAKE_IRQn = 130, /* GIRQ21 b[19] */
/* reserved gap 131 */
PS2_1B_WAKE_IRQn = 132, /* GIRQ21 b[21] */
/* reserved gap 133 - 134 */
KEYSCAN_IRQn = 135, /* GIRQ21 b[25] */
B16TMR0_IRQn = 136, /* GIRQ23 b[0] */
B16TMR1_IRQn = 137, /* GIRQ23 b[1] */
/* reserved gap 138 - 139 */
B32TMR0_IRQn = 140, /* GIRQ23 b[4] */
B32TMR1_IRQn = 141, /* GIRQ23 b[5] */
/* reserved 142 - 145 */
CCT_IRQn = 146, /* GIRQ18 b[20] */
CCT_CAP0_IRQn = 147, /* GIRQ18 b[21] */
CCT_CAP1_IRQn = 148, /* GIRQ18 b[22] */
CCT_CAP2_IRQn = 149, /* GIRQ18 b[23] */
CCT_CAP3_IRQn = 150, /* GIRQ18 b[24] */
CCT_CAP4_IRQn = 151, /* GIRQ18 b[25] */
CCT_CAP5_IRQn = 152, /* GIRQ18 b[26] */
CCT_CMP0_IRQn = 153, /* GIRQ18 b[27] */
CCT_CMP1_IRQn = 154, /* GIRQ18 b[28] */
EEPROM_CTRL_IRQn = 155, /* GIRQ18 b[13] */
ESPI_VWIRE_IRQn = 156, /* GIRQ19 b[8] */
/* reserved gap 157 */
SMB4_IRQn = 158, /* GIRQ13 b[4] */
TACH3_IRQn = 159, /* GIRQ17 b[4] */
CEC_IRQn = 160, /* GIRQ17 b[5] */
SGPIOCtrl0_IRQn = 161, /* GIRQ18 b[14] */
SGPIOCtrl1_IRQn = 162, /* GIRQ18 b[15] */
SGPIOCtrl2_IRQn = 163, /* GIRQ18 b[16] */
SGPIOCtrl3_IRQn = 164, /* GIRQ18 b[17] */
/* reserved gap 165 */
SAF_DONE_IRQn = 166, /* GIRQ19 b[9] */
SAF_ERR_IRQn = 167, /* GIRQ19 b[10] */
I2C0_IRQn = 168, /* GIRQ13 b[5] */
I2C1_IRQn = 169, /* GIRQ13 b[6] */
I2C2_IRQn = 170, /* GIRQ13 b[7] */
WDT_IRQn = 171, /* GIRQ21 b[2] */
GLUE_IRQn = 172, /* GIRQ23 b[26] */
OTP_READY_IRQn = 173, /* GIRQ20 b[3] */
MAX_IRQn = 174
} IRQn_Type;
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
/* =========================== Configuration of the Arm Cortex-M4 Processor and Core Peripherals =========================== */
#define __CM4_REV 0x0201 /*!< Core Revision r2p1 */
#define __MPU_PRESENT 1 /*!< Set to 1 if MPU is present */
#define __VTOR_PRESENT 1 /*!< Set to 1 if VTOR is present */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 0 /*!< Set to 1 if FPU is present */
#define __FPU_DP 0 /*!< Set to 1 if FPU is double precision FPU (default is single precision FPU) */
#define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */
#define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */
#define __DTCM_PRESENT 0 /*!< Set to 1 if DTCM is present */
/** @} *//* End of group Configuration_of_CMSIS */
#include "core_cm4.h" /*!< Arm Cortex-M4 processor and core peripherals */
/* ======================================== Start of section using anonymous unions ======================================== */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* ======================================================================== */
/* ================ Device Specific Peripheral Section ================ */
/* ======================================================================== */
/** @addtogroup MEC1501_Peripheral_peripherals
* @{
*/
/*@}*//* end of group MEC15xx_Peripherals */
/* ========================================= End of section using anonymous unions ========================================= */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* =========================================================================*/
/* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================*/
/** @addtogroup Device_Peripheral_peripheralAddr
* @{
*/
/* Peripheral and SRAM base address */
#define CODE_SRAM_BASE (0x000E0000UL) /*!< (CODE SRAM ) Base Address */
#define DATA_SRAM_BASE (0x00118000UL) /*!< (DATA SRAM ) Base Address */
#define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
/* Peripheral memory map */
#define WDT_BASE (PERIPH_BASE + 0x0400ul) /*!< (WDT0 ) Base Address */
#define B16TMR0_BASE (PERIPH_BASE + 0x0C00ul) /*!< (B16TMR0 ) Base Address */
#define B16TMR1_BASE (PERIPH_BASE + 0x0C20ul) /*!< (B16TMR1 ) Base Address */
#define B32TMR0_BASE (PERIPH_BASE + 0x0C80ul) /*!< (B32TMR0 ) Base Address */
#define B32TMR1_BASE (PERIPH_BASE + 0x0CA0ul) /*!< (B32TMR1 ) Base Address */
#define CCT_BASE (PERIPH_BASE + 0x1000ul) /*!< (CCT0 ) Base Address */
#define DMA_BASE (PERIPH_BASE + 0x2400ul) /*!< (DMA ) Base Address */
#define DMA_CHAN_BASE(n) (DMA_BASE + (((n)+1)<<6))
#define DMA_CH0_BASE (DMA_BASE + 0x0040ul) /*!< (DMA Chan 00 ) Base Address */
#define DMA_CH1_BASE (DMA_BASE + 0x0080ul) /*!< (DMA Chan 01 ) Base Address */
#define DMA_CH2_BASE (DMA_BASE + 0x00C0ul) /*!< (DMA Chan 02 ) Base Address */
#define DMA_CH3_BASE (DMA_BASE + 0x0100ul) /*!< (DMA Chan 03 ) Base Address */
#define DMA_CH4_BASE (DMA_BASE + 0x0140ul) /*!< (DMA Chan 04 ) Base Address */
#define DMA_CH5_BASE (DMA_BASE + 0x0180ul) /*!< (DMA Chan 05 ) Base Address */
#define DMA_CH6_BASE (DMA_BASE + 0x01C0ul) /*!< (DMA Chan 06 ) Base Address */
#define DMA_CH7_BASE (DMA_BASE + 0x0200ul) /*!< (DMA Chan 07 ) Base Address */
#define DMA_CH8_BASE (DMA_BASE + 0x0240ul) /*!< (DMA Chan 08 ) Base Address */
#define DMA_CH9_BASE (DMA_BASE + 0x0280ul) /*!< (DMA Chan 09 ) Base Address */
#define DMA_CH10_BASE (DMA_BASE + 0x02C0ul) /*!< (DMA Chan 10 ) Base Address */
#define DMA_CH11_BASE (DMA_BASE + 0x0300ul) /*!< (DMA Chan 11 ) Base Address */
#define EEPROM_CTRL_BASE (PERIPH_BASE + 0x2C00ul) /*!< (EEPROM_CTRL ) Base Address */
#define PROCHOT_BASE (PERIPH_BASE + 0x3400ul) /*!< (PROCHOT ) Base Address */
#define SMB_BASE(n) (PERIPH_BASE + 0x4000ul + ((n)<<10))
#define SMB0_BASE (PERIPH_BASE + 0x4000ul) /*!< (SMB0 ) Base Address */
#define SMB1_BASE (PERIPH_BASE + 0x4400ul) /*!< (SMB1 ) Base Address */
#define SMB2_BASE (PERIPH_BASE + 0x4800ul) /*!< (SMB2 ) Base Address */
#define SMB3_BASE (PERIPH_BASE + 0x4C00ul) /*!< (SMB3 ) Base Address */
#define SMB4_BASE (PERIPH_BASE + 0x5000ul) /*!< (SMB4 ) Base Address */
#define I2C_BASE(n) (PERIPH_BASE + 0x5100ul + ((n)<<8))
#define I2C0_BASE (PERIPH_BASE + 0x5100ul) /*!< (I2C0 ) Base Address */
#define I2C1_BASE (PERIPH_BASE + 0x5200ul) /*!< (I2C1 ) Base Address */
#define I2C2_BASE (PERIPH_BASE + 0x5300ul) /*!< (I2C2 ) Base Address */
#define PWM_BASE(n) (PERIPH_BASE + 0x5800ul + ((n)<<4))
#define PWM0_BASE (PERIPH_BASE + 0x5800ul) /*!< (PWM0 ) Base Address */
#define PWM1_BASE (PERIPH_BASE + 0x5810ul) /*!< (PWM1 ) Base Address */
#define PWM2_BASE (PERIPH_BASE + 0x5820ul) /*!< (PWM2 ) Base Address */
#define PWM3_BASE (PERIPH_BASE + 0x5830ul) /*!< (PWM3 ) Base Address */
#define PWM4_BASE (PERIPH_BASE + 0x5840ul) /*!< (PWM4 ) Base Address */
#define PWM5_BASE (PERIPH_BASE + 0x5850ul) /*!< (PWM5 ) Base Address */
#define PWM6_BASE (PERIPH_BASE + 0x5860ul) /*!< (PWM6 ) Base Address */
#define PWM7_BASE (PERIPH_BASE + 0x5870ul) /*!< (PWM7 ) Base Address */
#define PWM8_BASE (PERIPH_BASE + 0x5880ul) /*!< (PWM8 ) Base Address */
#define TACH_BASE(n) (PERIPH_BASE + 0x6000ul + ((n)<<4))
#define TACH0_BASE (PERIPH_BASE + 0x6000ul) /*!< (TACH0 ) Base Address */
#define TACH1_BASE (PERIPH_BASE + 0x6010ul) /*!< (TACH1 ) Base Address */
#define TACH2_BASE (PERIPH_BASE + 0x6020ul) /*!< (TACH2 ) Base Address */
#define TACH3_BASE (PERIPH_BASE + 0x6030ul) /*!< (TACH3 ) Base Address */
#define PECI_BASE (PERIPH_BASE + 0x6400ul) /*!< (PECI ) Base Address */
#define HDMI_CEC_BASE (PERIPH_BASE + 0x6800ul) /*!< (HDMI_CEC ) Base Address */
#define SPISLV_BASE (PERIPH_BASE + 0x7000ul) /*!< (SPISLV ) Base Address */
#define RTMR_BASE (PERIPH_BASE + 0x7400ul) /*!< (RTMR ) Base Address */
#define ADC_BASE (PERIPH_BASE + 0x7C00ul) /*!< (ADC ) Base Address */
#define TFDP_BASE (PERIPH_BASE + 0x8C00ul) /*!< (TFDP ) Base Address */
#define PS2_0_BASE (PERIPH_BASE + 0x9000ul) /*!< (PS2 0 ) Base Address */
#define PS2_1_BASE (PERIPH_BASE + 0x9040ul) /*!< (PS2 1 ) Base Address */
#define HTMR0_BASE (PERIPH_BASE + 0x9800ul) /*!< (HTMR0 ) Base Address */
#define HTMR1_BASE (PERIPH_BASE + 0x9820ul) /*!< (HTMR1 ) Base Address */
#define KEYSCAN_BASE (PERIPH_BASE + 0x9C00ul) /*!< (KEYSCAN ) Base Address */
#define VBATR_BASE (PERIPH_BASE + 0xA400ul) /*!< (VBATR ) Base Address */
#define VBATM_BASE (PERIPH_BASE + 0xA800ul) /*!< (VBATM ) Base Address */
#define WKTMR_BASE (PERIPH_BASE + 0xAC80ul) /*!< (WKTMR ) Base Address */
#define VCI_BASE (PERIPH_BASE + 0xAE00ul) /*!< (VCI ) Base Address */
#define LED0_BASE (PERIPH_BASE + 0xB800ul) /*!< (BBLED0 ) Base Address */
#define LED1_BASE (PERIPH_BASE + 0xB900ul) /*!< (BBLED1 ) Base Address */
#define LED2_BASE (PERIPH_BASE + 0xBA00ul) /*!< (BBLED2 ) Base Address */
#define ECIA_BASE (PERIPH_BASE + 0xE000ul) /*!< (ECIA ) Base Address */
#define ECS_BASE (PERIPH_BASE + 0xFC00ul) /*!< (ECS ) Base Address */
#define QMSPI_BASE (PERIPH_BASE + 0x70000ul) /*!< (QMSPI0 ) Base Address */
#define PCR_BASE (PERIPH_BASE + 0x80100ul) /*!< (PCR ) Base Address */
#define GPIO_BASE (PERIPH_BASE + 0x81000ul) /*!< (GPIO ) Base Address */
#define GPIO_CTRL_BASE (GPIO_BASE) /*!< (GPIO ) Control Base Address */
#define GPIO_PARIN_BASE (GPIO_BASE + 0x0300ul) /*!< (GPIO Parallel I/O) Base Address */
#define GPIO_PAROUT_BASE (GPIO_BASE + 0x0380ul) /*!< (GPIO Parallel I/O) Base Address */
#define GPIO_LOCK_BASE (GPIO_BASE + 0x03E8ul) /*!< (GPIO Lock) Base Address */
#define GPIO_CTRL2_BASE (GPIO_BASE + 0x0500ul) /*!< (GPIO ) Control2 Base Address */
#define OTP_BASE (PERIPH_BASE + 0x82000ul) /*!< (OTP ) Base Address */
#define MBOX_BASE (PERIPH_BASE + 0xF0000ul) /*!< (MBOX ) Base Address */
#define KBC_BASE (PERIPH_BASE + 0xF0400ul) /*!< (KBC ) Base Address */
#define ACPI_EC_BASE(n) (PERIPH_BASE + 0xF0800ul + ((n)<<10))
#define ACPI_EC_0_BASE (PERIPH_BASE + 0xF0800ul) /*!< (ACPI EC0 ) Base Address */
#define ACPI_EC_1_BASE (PERIPH_BASE + 0xF0C00ul) /*!< (ACPI EC1 ) Base Address */
#define ACPI_EC_2_BASE (PERIPH_BASE + 0xF1000ul) /*!< (ACPI EC2 ) Base Address */
#define ACPI_EC_3_BASE (PERIPH_BASE + 0xF1400ul) /*!< (ACPI EC3 ) Base Address */
#define ACPI_PM1_BASE (PERIPH_BASE + 0xF1C00ul) /*!< (ACPI PM1 ) Base Address */
#define PORT92_BASE (PERIPH_BASE + 0xF2000ul) /*!< (PORT92 ) Base Address */
#define UART_BASE(n) (PERIPH_BASE + 0xF2400ul + ((n)<<10))
#define UART0_BASE (PERIPH_BASE + 0xF2400ul) /*!< (UART0 ) Base Address */
#define UART1_BASE (PERIPH_BASE + 0xF2800ul) /*!< (UART1 ) Base Address */
#define UART2_BASE (PERIPH_BASE + 0xF2C00ul) /*!< (UART2 ) Base Address */
#define ESPI_IO_BASE (PERIPH_BASE + 0xF3400ul) /*!< (ESPI IO Component) Base Address */
#define ESPI_IO_PC_BASE ((ESPI_IO_BASE) + 0x100ul) /*!< (ESPI IO Peripheral Channel) Base Address */
#define ESPI_IO_HOST_BAR_BASE ((ESPI_IO_BASE) + 0x120ul) /*!< (ESPI IO Host IO BAR) Base Address */
#define ESPI_IO_LTR_BASE ((ESPI_IO_BASE) + 0x220ul) /*!< (ESPI IO LTR) Base Address */
#define ESPI_IO_OOB_BASE ((ESPI_IO_BASE) + 0x240ul) /*!< (ESPI IO Out-of-Band Channel) Base Address */
#define ESPI_IO_FC_BASE ((ESPI_IO_BASE) + 0x280ul) /*!< (ESPI IO Flash Channel) Base Address */
#define ESPI_IO_CAP_BASE ((ESPI_IO_BASE) + 0x2B0ul) /*!< (ESPI IO Capabilities) Base Address */
#define ESPI_IO_EC_BAR_BASE ((ESPI_IO_BASE) + 0x330ul) /*!< (ESPI IO EC IO BAR) Base Address */
#define ESPI_IO_VW_BASE ((ESPI_IO_BASE) + 0x2B0ul) /*!< (ESPI IO EC IO VW registers) Base Address */
#define ESPI_IO_SIRQ_BASE ((ESPI_IO_BASE) + 0x3A0ul) /*!< (ESPI IO Seril IRQ registers) Base Address */
#define ESPI_MEM_BASE (PERIPH_BASE + 0xF3800ul) /*!< (ESPI Memory Component) Base Address */
#define ESPI_MEM_EC_BAR_BASE ((ESPI_MEM_BASE) + 0x0130ul) /*!< (ESPI Logical Device Memory BAR EC */
#define ESPI_MEM_HOST_BAR_BASE ((ESPI_MEM_BASE) + 0x0330ul) /*!< (ESPI Logical Device Memory BAR Host */
#define ESPI_MEM_SRAM_EC_BAR_BASE ((ESPI_MEM_BASE) + 0x01A0ul) /*!< (ESPI Memory SRAM BAR EC */
#define ESPI_MEM_SRAM_HOST_BAR_BASE ((ESPI_MEM_BASE) + 0x03A0ul) /*!< (ESPI Memory SRAM BAR Host */
#define ESPI_MEM_BM_BASE ((ESPI_MEM_BASE) + 0x0200ul) /*!< (ESPI Memory Component Bus Master) Base Address */
#define EMI0_BASE (PERIPH_BASE + 0xF4000ul) /*!< (EMI0 ) Base Address */
#define EMI1_BASE (PERIPH_BASE + 0xF4400ul) /*!< (EMI1 ) Base Address */
#define RTC_BASE (PERIPH_BASE + 0xF5000ul) /*!< (RTC ) Base Address */
#define P80CAP0_BASE (PERIPH_BASE + 0xF8000ul) /*!< (P80CAP0 ) Base Address */
#define P80CAP1_BASE (PERIPH_BASE + 0xF8400ul) /*!< (P80CAP1 ) Base Address */
#define ESPI_VW_BASE (PERIPH_BASE + 0xF9C00ul) /*!< (ESPI VW Component) Base Address */
#define ESPI_SMVW_BASE (ESPI_VW_BASE + 0x200ul) /*!< (ESPI VW Component Slave-to-Master) Base Address */
#define GCFG_BASE (PERIPH_BASE + 0xFFF00ul) /*!< (GCFG ) Base Address */
/** @} *//* End of group Device_Peripheral_peripheralAddr */
#include "component/acpi_ec.h"
#include "component/dma.h"
#include "component/ecia.h"
#include "component/ecs.h"
#include "component/gpio.h"
#include "component/emi.h"
#include "component/espi_io.h"
#include "component/espi_mem.h"
#include "component/espi_vw.h"
#include "component/i2c.h"
#include "component/kbc.h"
#include "component/keyscan.h"
#include "component/led.h"
#include "component/mailbox.h"
#include "component/pcr.h"
#include "component/port92.h"
#include "component/smb.h"
#include "component/timer.h"
#include "component/uart.h"
#include "component/vbat.h"
#include "component/wdt.h"
/* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_declaration
* @{
*/
#define WDT_REGS ((WDT_Type *) WDT_BASE)
#define B16TMR0_REGS ((BTMR_Type *) B16TMR0_BASE)
#define B16TMR1_REGS ((BTMR_Type *) B16TMR1_BASE)
#define B32TMR0_REGS ((BTMR_Type *) B32TMR0_BASE)
#define B32TMR1_REGS ((BTMR_Type *) B32TMR1_BASE)
#define CCT_REGS ((CCT_Type *) CCT_BASE)
#define DMAM_REGS ((DMAM_Type *) DMA_BASE)
/* Individual DMA channels */
#define DMA0_REGS ((DMA_CHAN_ALU_Type *)(DMA_CHAN_BASE(0)))
#define DMA1_REGS ((DMA_CHAN_ALU_Type *)(DMA_CHAN_BASE(1)))
#define DMA2_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(2)))
#define DMA3_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(3)))
#define DMA4_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(4)))
#define DMA5_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(5)))
#define DMA6_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(6)))
#define DMA7_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(7)))
#define DMA8_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(8)))
#define DMA9_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(9)))
#define DMA10_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(10)))
#define DMA11_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(11)))
#define SMB0_REGS ((I2C_SMB_Type *) SMB0_BASE)
#define SMB1_REGS ((I2C_SMB_Type *) SMB1_BASE)
#define SMB2_REGS ((I2C_SMB_Type *) SMB2_BASE)
#define SMB3_REGS ((I2C_SMB_Type *) SMB3_BASE)
#define SMB4_REGS ((I2C_SMB_Type *) SMB4_BASE)
#define RTMR_REGS ((RTMR_Type *) RTMR_BASE)
#define HTMR0_REGS ((HTMR_Type *) HTMR0_BASE)
#define HTMR1_REGS ((HTMR_Type *) HTMR1_BASE)
#define KSCAN_REGS ((KSCAN_Type *)(KEYSCAN_BASE))
#define VBATR_REGS ((VBATR_Type *) VBATR_BASE)
#define VBATM_REGS ((VBATM_Type *) VBATM_BASE)
#define WKTMR_REGS ((WKTMR_Type *) WKTMR_BASE)
#define LED0_REGS ((LED_Type *) LED0_BASE)
#define LED1_REGS ((LED_Type *) LED1_BASE)
#define LED2_REGS ((LED_Type *) LED2_BASE)
#define ECIA_REGS ((ECIA_Type *) ECIA_BASE)
#define GIRQ08_REGS ((GIRQ_Type *) ECIA_BASE)
#define GIRQ09_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0x14))
#define GIRQ10_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0x28))
#define GIRQ11_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0x3C))
#define GIRQ12_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0x50))
#define GIRQ13_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0x64))
#define GIRQ14_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0x78))
#define GIRQ15_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0x8C))
#define GIRQ16_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0xA0))
#define GIRQ17_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0xB4))
#define GIRQ18_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0xC8))
#define GIRQ19_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0xDC))
#define GIRQ20_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0xF0))
#define GIRQ21_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0x104))
#define GIRQ22_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0x118))
#define GIRQ23_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0x12C))
#define GIRQ24_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0x140))
#define GIRQ25_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0x154))
#define GIRQ26_REGS ((GIRQ_Type *) ((ECIA_BASE) + 0x168))
#define ECS_REGS ((ECS_Type *) ECS_BASE)
#define QMSPI_REGS ((QMSPI_Type *) QMSPI_BASE)
#define PCR_REGS ((PCR_Type *) PCR_BASE)
#define GPIO_CTRL_REGS ((GPIO_CTRL_Type *)(GPIO_CTRL_BASE))
#define GPIO_CTRL2_REGS ((GPIO_CTRL2_Type *)(GPIO_CTRL2_BASE))
#define GPIO_PARIN_REGS ((GPIO_PARIN_Type *)(GPIO_PARIN_BASE))
#define GPIO_PAROUT_REGS ((GPIO_PAROUT_Type *)(GPIO_PAROUT_BASE))
#define GPIO_LOCK_REGS ((GPIO_LOCK_Type *)(GPIO_LOCK_BASE))
#define MBOX_REGS ((MBOX_Type *)(MBOX_BASE))
#define KBC_REGS ((KBC_Type *)(KBC_BASE))
#define ACPI_EC_0_REGS ((ACPI_EC_Type *)(ACPI_EC_0_BASE))
#define ACPI_EC_1_REGS ((ACPI_EC_Type *)(ACPI_EC_1_BASE))
#define ACPI_EC_2_REGS ((ACPI_EC_Type *)(ACPI_EC_2_BASE))
#define ACPI_EC_3_REGS ((ACPI_EC_Type *)(ACPI_EC_3_BASE))
#define PORT92_REGS ((PORT92_Type *)(PORT92_BASE))
#define UART0_REGS ((UART_Type *) UART0_BASE)
#define UART1_REGS ((UART_Type *) UART1_BASE)
#define UART2_REGS ((UART_Type *) UART2_BASE)
#define ESPI_PC_REGS ((ESPI_IO_PC_Type *)(ESPI_IO_PC_BASE))
#define ESPI_HIO_BAR_REGS ((ESPI_IO_BAR_HOST_Type *)(ESPI_IO_HOST_BAR_BASE))
#define ESPI_LTR_REGS ((ESPI_IO_LTR_Type *)(ESPI_IO_LTR_BASE))
#define ESPI_OOB_REGS ((ESPI_IO_OOB_Type *)(ESPI_IO_OOB_BASE))
#define ESPI_FC_REGS ((ESPI_IO_FC_Type *)(ESPI_IO_FC_BASE))
#define ESPI_CAP_REGS ((ESPI_IO_CAP_Type *)(ESPI_IO_CAP_BASE))
#define ESPI_EIO_BAR_REGS ((ESPI_IO_BAR_EC_Type *)(ESPI_IO_EC_BAR_BASE))
#define ESPI_SIRQ_REGS ((ESPI_IO_SIRQ_Type *)(ESPI_IO_SIRQ_BASE))
#define ESPI_MEM_EBAR_REGS ((ESPI_MEM_BAR_EC_Type *)(ESPI_MEM_EC_BAR_BASE))
#define ESPI_MEM_HBAR_REGS ((ESPI_MEM_BAR_HOST_Type *)(ESPI_MEM_HOST_BAR_BASE))
#define ESPI_MEM_SRAM_EBAR_REGS ((ESPI_MEM_SRAM_BAR_EC_Type *)(ESPI_MEM_SRAM_EC_BAR_BASE))
#define ESPI_MEM_SRAM_HBAR_REGS ((ESPI_MEM_SRAM_BAR_HOST_Type *)(ESPI_MEM_SRAM_HOST_BAR_BASE))
#define ESPI_MEM_BM_REGS ((ESPI_MEM_BM_Type *)(ESPI_MEM_BM_BASE))
/* eSPI Virtual Wire registers in IO component */
#define ESPI_IO_VW_REGS ((ESPI_IO_VW_Type *) ESPI_IO_VW_BASE)
/* eSPI Virtual Wire registers for each group of 4 VWires */
#define ESPI_M2S_VW_REGS ((ESPI_M2S_VW_Type *) ESPI_VW_BASE)
#define ESPI_S2M_VW_REGS ((ESPI_S2M_VW_Type *) (ESPI_SMVW_BASE))
#define EMI0_REGS ((EMI_Type *)(EMI0_BASE))
#define EMI1_REGS ((EMI_Type *)(EMI0_BASE))
/** @} *//* End of group MEC1501 */
/** @} *//* End of group MCHP */
#ifdef __cplusplus
}
#endif
#endif /* MEC1501HSZ_H */

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file acpi_ec.h
*MEC1501 ACPI EC Registers
*/
/** @defgroup MEC1501 Peripherals ACPI_EC
*/
#ifndef _ACPI_EC_H
#define _ACPI_EC_H
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
/* =========================================================================*/
/* ================ ACPI_EC ================ */
/* =========================================================================*/
#define MCHP_ACPI_EC_BASE_ADDR 0x400F0800ul
#define MCHP_ACPI_EC_NUM_INSTANCES 4u
#define MCHP_ACPI_EC_SPACING 0x0400ul
#define MCHP_ACPI_EC_SPACING_PWROF2 10u
#define MCHP_ACPI_EC0_ADDR 0x400F0800ul
#define MCHP_ACPI_EC1_ADDR 0x400F0C00ul
#define MCHP_ACPI_EC2_ADDR 0x400F1000ul
#define MCHP_ACPI_EC3_ADDR 0x400F1400ul
/* 0 <= n < MCHP_ACPI_EC_NUM_INSTANCES */
#define MCHP_ACPI_EC_ADDR(n) (MCHP_ACPI_EC_BASE_ADDR +\
((uint32_t)(n) << MCHP_ACPI_EC_SPACING_PWROF2))
/*
* ACPI_EC interrupts
*/
#define MCHP_ACPI_EC_GIRQ 15u
#define MCHP_ACPI_EC_GIRQ_NVIC 7u
#define MCHP_ACPI_EC_0_IBF_NVIC 45u
#define MCHP_ACPI_EC_0_OBE_NVIC 46u
#define MCHP_ACPI_EC_0_IBF_GIRQ_POS 5u
#define MCHP_ACPI_EC_0_OBE_GIRQ_POS 6u
#define MCHP_ACPI_EC_0_IBF_GIRQ (1ul << 5)
#define MCHP_ACPI_EC_0_OBE_GIRQ (1ul << 6)
#define MCHP_ACPI_EC_1_IBF_NVIC 47u
#define MCHP_ACPI_EC_1_OBE_NVIC 48u
#define MCHP_ACPI_EC_1_IBF_GIRQ_POS 7u
#define MCHP_ACPI_EC_1_OBE_GIRQ_POS 8u
#define MCHP_ACPI_EC_1_IBF_GIRQ (1ul << 7)
#define MCHP_ACPI_EC_1_OBE_GIRQ (1ul << 8)
#define MCHP_ACPI_EC_2_IBF_NVIC 49u
#define MCHP_ACPI_EC_2_OBE_NVIC 50u
#define MCHP_ACPI_EC_2_IBF_GIRQ_POS 9u
#define MCHP_ACPI_EC_2_OBE_GIRQ_POS 10u
#define MCHP_ACPI_EC_2_IBF_GIRQ (1ul << 9)
#define MCHP_ACPI_EC_2_OBE_GIRQ (1ul << 10)
#define MCHP_ACPI_EC_3_IBF_NVIC 51u
#define MCHP_ACPI_EC_3_OBE_NVIC 52u
#define MCHP_ACPI_EC_3_IBF_GIRQ_POS 11u
#define MCHP_ACPI_EC_3_OBE_GIRQ_POS 12u
#define MCHP_ACPI_EC_3_IBF_GIRQ (1ul << 11)
#define MCHP_ACPI_EC_3_OBE_GIRQ (1ul << 12)
/* 0 <= n < MCHP_ACPI_EC_NUM_INSTANCES */
#define MCHP_ACPI_EC_IBF_NVIC(n) (45ul + ((uint32_t)(n) << 1))
#define MCHP_ACPI_EC_OBE_NVIC(n) (46ul + ((uint32_t)(n) << 1))
#define MCHP_ACPI_EC_IBF_GIRQ_POS(n) (5ul + ((uint32_t)(n) << 1))
#define MCHP_ACPI_EC_OBE_GIRQ_POS(n) (6ul + ((uint32_t)(n) << 1))
#define MCHP_ACPI_EC_IBF_GIRQ(n) (1ul << MCHP_ACPI_EC_IBF_GIRQ_POS(n))
#define MCHP_ACPI_EC_OBE_GIRQ(n) (1ul << MCHP_ACPI_EC_OBE_GIRQ_POS(n))
/*
* EC_STS and OS_CMD_STS(read) bit definitions
*/
#define MCHP_ACPI_EC_STS_OBF_POS 0u
#define MCHP_ACPI_EC_STS_OBF (1ul << (ACPI_EC_STS_OBF_POS))
#define MCHP_ACPI_EC_STS_IBF_POS 1u
#define MCHP_ACPI_EC_STS_IBF (1ul << (ACPI_EC_STS_IBF_POS))
#define MCHP_ACPI_EC_STS_UD1A_POS 2u
#define MCHP_ACPI_EC_STS_UD1A (1ul << (ACPI_EC_STS_UD1A_POS))
#define MCHP_ACPI_EC_STS_CMD_POS 3u
#define MCHP_ACPI_EC_STS_CMD (1ul << (ACPI_EC_STS_CMD_POS))
#define MCHP_ACPI_EC_STS_BURST_POS 4u
#define MCHP_ACPI_EC_STS_BURST (1ul << (ACPI_EC_STS_BURST_POS))
#define MCHP_ACPI_EC_STS_SCI_POS 5u
#define MCHP_ACPI_EC_STS_SCI (1ul << (ACPI_EC_STS_SCI_POS))
#define MCHP_ACPI_EC_STS_SMI_POS 6u
#define MCHP_ACPI_EC_STS_SMI (1ul << (ACPI_EC_STS_SMI_POS))
#define MCHP_ACPI_EC_STS_UD0A_POS 7u
#define MCHP_ACPI_EC_STS_UD0A (1ul << (ACPI_EC_STS_UD0A_POS))
/*
* EC_BYTE_CTRL and OS_BYTE_CTRL
*/
#define MCHP_ACPI_EC_BYTE_CTRL_4B_POS 0u
#define MCHP_ACPI_EC_BYTE_CTRL_4B_EN (1ul << (ACPI_EC_BYTE_CTRL_4B_POS))
/**
* @brief ACPI EC Registers (ACPI_EC)
*/
typedef struct acpi_ec_regs
{
__IOM uint32_t OS_DATA; /*!< (@ 0x0000) OS Data */
__IOM uint8_t OS_CMD_STS; /*!< (@ 0x0004) OS Command(WO), Status(RO) */
__IOM uint8_t OS_BYTE_CTRL; /*!< (@ 0x0005) OS Byte Control */
uint8_t RSVD1[0x100u - 0x06u];
__IOM uint32_t EC2OS_DATA; /*!< (@ 0x0100) EC to OS Data */
__IOM uint8_t EC_STS; /*!< (@ 0x0104) EC Status */
__IOM uint8_t EC_BYTE_CTRL; /*!< (@ 0x0105) EC Byte Control */
uint8_t RSVD2[2];
__IOM uint32_t OS2EC_DATA; /*!< (@ 0x0108) OS to EC Data */
} ACPI_EC_Type;
#endif /* #ifndef _ACPI_EC_H */
/* end acpi_ec.h */
/** @}
*/

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mec/mec1501/component/dma.h Normal file
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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file dma.h
*MEC1501 DMA controller definitions
*/
/** @defgroup MEC1501 Peripherals DMA
*/
#ifndef _DMA_H
#define _DMA_H
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include "regaccess.h"
#define MCHP_NUM_DMA_CHANNELS 12ul
#define MCHP_DMA_BLOCK_BASE_ADDR 0x40002400ul
#define MCHP_DMA_CHAN_OFFSET 0x40ul
#define MCHP_DMA_OFFSET_POF2 6u
#define MCHP_DMA_CHAN0_ADDR \
((MCHP_DMA_BLOCK_BASE_ADDR) + (MCHP_DMA_CHAN_OFFSET))
#define MCHP_DMA_CHAN_ADDR(n) ((uintptr_t)(MCHP_DMA_CHAN0_ADDR) +\
((uintptr_t)(n) << MCHP_DMA_OFFSET_POF2))
/*
* DMA block PCR register and bit
* Bit position applied to PCR Sleep Enable, Clock Req(RO), and Reset
* registers.
*/
#define MCHP_DMA_PCR_SLP_EN_ADDR 0x40080134ul
#define MCHP_DMA_PCR_CLK_REQ_ADDR 0x40080154ul
#define MCHP_DMA_PCR_RST_ADDR 0x40080174ul
#define MCHP_DMA_PCR_SCR_POS 6u
#define MCHP_DMA_PCR_SCR_VAL (1ul << 6u)
#define MCHP_DMA_GIRQ_ID 14u
#define MCHP_DMA_GIRQ_SRC_ADDR 0x4000E078ul
#define MCHP_DMA_GIRQ_EN_SET_ADDR 0x4000E07Cul
#define MCHP_DMA_GIRQ_RESULT_ADDR 0x4000E080ul
#define MCHP_DMA_GIRQ_EN_CLR_ADDR 0x4000E084ul
#define MCHP_DMA_GIRQ_NUM 14u
#define MCHP_DMA_GIRQ_IDX ((MCHP_DMA_GIRQ_NUM) - 8u)
/* Aggregated GIRQ14 NVIC input */
#define MCHP_DMA_AGGR_NVIC 6u
/*
* Value used for GIRQ Source, Set Enable,
* Result, and Clear Enable registers.
* 0 <= ch < MCHP_NUM_DMA_CHANNELS
*/
#define MCHP_DMA_GIRQ_VAL(ch) (1ul << (ch))
/*
* DMA channel direct NVIC external interrupt inputs
* 0 <= ch < 12
*/
#define MCHP_DMA_DIRECT_NVIC_NUM(ch) (24ul + (ch))
/*
* DMA channel direct NVIC external interrupt input from channel address.
* Channels are located starting at offset 0x40 from DMA block base address.
* Channels are spaced every 0x40 bytes.
* DMA block has 1KB total register space.
*/
#define MCHP_DMA_DIRECT_NVIC_NUM_BA(chba) \
(24ul + (((uintptr_t)(chba) - (uintptr_t)MCHP_DMA_CHAN_ADDR(0)) >> 6))
#define MCHP_DMA0_GIRQ_NVIC (24u + 0u)
#define MCHP_DMA1_GIRQ_NVIC (24u + 1u)
#define MCHP_DMA2_GIRQ_NVIC (24u + 2u)
#define MCHP_DMA3_GIRQ_NVIC (24u + 3u)
#define MCHP_DMA4_GIRQ_NVIC (24u + 4u)
#define MCHP_DMA5_GIRQ_NVIC (24u + 5u)
#define MCHP_DMA6_GIRQ_NVIC (24u + 6u)
#define MCHP_DMA7_GIRQ_NVIC (24u + 7u)
#define MCHP_DMA8_GIRQ_NVIC (24u + 8u)
#define MCHP_DMA9_GIRQ_NVIC (24u + 9u)
#define MCHP_DMA10_GIRQ_NVIC (24u + 10u)
#define MCHP_DMA11_GIRQ_NVIC (24u + 11u)
/*
* GIRQ bit position from channel base address
*/
#define MCHP_DMA_GIRQ_POS_BA(chba) \
(((uintptr_t)(chba) - (uintptr_t)MCHP_DMA_CHAN_ADDR(0)) >> 6)
#define MCHP_DMA_GIRQ_VAL_BA(chba) \
(1ul << MCHP_DMA_GIRQ_POS_BA(chba))
#define MCHP_DMA0_GIRQ_POS 0u
#define MCHP_DMA1_GIRQ_POS 1u
#define MCHP_DMA2_GIRQ_POS 2u
#define MCHP_DMA3_GIRQ_POS 3u
#define MCHP_DMA4_GIRQ_POS 4u
#define MCHP_DMA5_GIRQ_POS 5u
#define MCHP_DMA6_GIRQ_POS 6u
#define MCHP_DMA7_GIRQ_POS 7u
#define MCHP_DMA8_GIRQ_POS 8u
#define MCHP_DMA9_GIRQ_POS 9u
#define MCHP_DMA10_GIRQ_POS 10u
#define MCHP_DMA11_GIRQ_POS 11u
#define MCHP_DMA0_GIRQ_VAL (1ul << 0u)
#define MCHP_DMA1_GIRQ_VAL (1ul << 1u)
#define MCHP_DMA2_GIRQ_VAL (1ul << 2u)
#define MCHP_DMA3_GIRQ_VAL (1ul << 3u)
#define MCHP_DMA4_GIRQ_VAL (1ul << 4u)
#define MCHP_DMA5_GIRQ_VAL (1ul << 5u)
#define MCHP_DMA6_GIRQ_VAL (1ul << 6u)
#define MCHP_DMA7_GIRQ_VAL (1ul << 7u)
#define MCHP_DMA8_GIRQ_VAL (1ul << 8u)
#define MCHP_DMA9_GIRQ_VAL (1ul << 9u)
#define MCHP_DMA10_GIRQ_VAL (1ul << 10u)
#define MCHP_DMA11_GIRQ_VAL (1ul << 11u)
/*
* Device Numbers for Channel Control Reg Device Number Field
*/
#define MCHP_DMA_DEVNUM_SMB0_SLV 0ul
#define MCHP_DMA_DEVNUM_SMB0_MTR 1ul
#define MCHP_DMA_DEVNUM_SMB1_SLV 2ul
#define MCHP_DMA_DEVNUM_SMB1_MTR 3ul
#define MCHP_DMA_DEVNUM_SMB2_SLV 4ul
#define MCHP_DMA_DEVNUM_SMB2_MTR 5ul
#define MCHP_DMA_DEVNUM_SMB3_SLV 6ul
#define MCHP_DMA_DEVNUM_SMB3_MTR 7ul
#define MCHP_DMA_DEVNUM_SMB4_SLV 8ul
#define MCHP_DMA_DEVNUM_SMB4_RX 9ul
#define MCHP_DMA_DEVNUM_QMSPI_TX 10ul
#define MCHP_DMA_DEVNUM_QMSPI_RX 11ul
#define MCHP_DMA_DEVNUM_MAX 12ul
#define MCHP_DMA_CHAN_REG_BLEN 0x40ul
/* DMA Block Layout
* DMA Main registers start at block base
* Three registers located at word boundaries (0, 4, 8)
* Each channel starts at base + ((channel_number + 1) * DMA_CHAN_REG_BLEN)
* DMA Main @ base
* DMA Channel 0 @ base + DMA_CHAN_REG_BLEN
* DMA Channel 1 @ base + (2 * DMA_CHAN_REG_BLEN)
*
*/
/*
* DMA Main Registers
*/
#define MCHP_DMAM_CTRL_OFS 0x00ul
#define MCHP_DMAM_PKT_RO_OFS 0x04ul
#define MCHP_DMAM_FSM_RO_OFS 0x08ul
#define MCHP_DMAM_CTRL_OFFSET 0x00ul
#define MCHP_DMAM_CTRL_MASK 0x03UL
#define MCHP_DMAM_CTRL_ENABLE (1UL << 0)
#define MCHP_DMAM_CTRL_SOFT_RESET (1UL << 1)
/*
* DMA Main Register Access
*/
#define MCHP_DMAM_CTRL() \
REG8_OFS(MCHP_DMA_BLOCK_BASE_ADDR, MCHP_DMAM_CTRL_OFS)
#define MCHP_DMAM_PKT_RO() \
REG32_OFS(MCHP_DMA_BLOCK_BASE_ADDR, MCHP_DMAM_PKT_RO_OFS)
#define MCHP_DMAM_FSM_RO() \
REG32_OFS(MCHP_DMA_BLOCK_BASE_ADDR, MCHP_DMAM_FSM_RO_OFS)
/*
* DMA channel register offsets
*/
#define MCHP_DMA_ACTV_OFS 0x00ul
#define MCHP_DMA_MSTART_OFS 0x04ul
#define MCHP_DMA_MEND_OFS 0x08ul
#define MCHP_DMA_DSTART_OFS 0x0Cul
#define MCHP_DMA_CTRL_OFS 0x10ul
#define MCHP_DMA_ISTS_OFS 0x14ul
#define MCHP_DMA_IEN_OFS 0x18ul
#define MCHP_DMA_FSM_RO_OFS 0x1Cul
/* Channels 0 and 1 include optional ALU */
#define MCHP_DMA_ALU_CTRL_OFS 0x20ul
#define MCHP_DMA_ALU_DATA_OFS 0x24ul
#define MCHP_DMA_ALU_STS_RO_OFS 0x28ul
/*
* DMA Channel register addresses
*/
#define MCHP_DMA_ACTV_ADDR(ch) \
(uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_ACTV_OFS))
#define MCHP_DMA_MSTART_ADDR(ch) \
(uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_MSTART_OFS))
#define MCHP_DMA_MEND_ADDR(ch) \
(uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_MEND_OFS))
#define MCHP_DMA_DSTART_ADDR(ch) \
(uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_DSTART_OFS))
#define MCHP_DMA_CTRL_ADDR(ch) \
(uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_CTRL_OFS))
#define MCHP_DMA_ISTS_ADDR(ch) \
(uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_ISTS_OFS))
#define MCHP_DMA_IEND_ADDR(ch) \
(uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_IEN_OFS))
#define MCHP_DMA_FSM_ADDR(ch) \
(uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_FSM_RO_OFS))
/* Channels 0 and 1 include optional ALU */
#define MCHP_DMA_ALU_CTRL_ADDR(ch) \
(uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_ALU_CTRL_OFS))
#define MCHP_DMA_ALU_DATA_ADDR(ch) \
(uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_ALU_DATA_OFS))
#define MCHP_DMA_ALU_STS_RO_ADDR(ch) \
(uintptr_t)(MCHP_DMA_CHAN_ADDR(ch) + (MCHP_DMA_ALU_STS_RO_OFS))
/*
* DMA Channel Register Access
* ch = channel ID: 0 <= ch < MCHP_NUM_DMA_CHANNELS
*/
#define MCHP_DMA_ACTV(ch) \
REG8_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_ACTV_OFS)
#define MCHP_DMA_MSTART(ch) \
REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_MSTART_OFS)
#define MCHP_DMA_MEND(ch) \
REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_MEND_OFS)
#define MCHP_DMA_DSTART(ch) \
REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_DSTART_OFS)
#define MCHP_DMA_CTRL(ch) \
REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_CTRL_OFS)
#define MCHP_DMA_ISTS(ch) \
REG8_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_ISTS_OFS)
#define MCHP_DMA_IEN(ch) \
REG8_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_IEN_OFS)
#define MCHP_DMA_FSM(ch) \
REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_FSM_RO_OFS)
#define MCHP_DMA_ALU_EN(ch) \
REG8_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_ALU_CTRL_OFS)
#define MCHP_DMA_ALU_DATA(ch) \
REG32_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_ALU_DATA_OFS)
#define MCHP_DMA_ALU_STS_RO(ch) \
REG8_OFS(MCHP_DMA_CHAN_ADDR(ch), MCHP_DMA_ALU_STS_RO_OFS)
/*
* DMA Channel Register Access by base address
* chba = channel base address (start of channel registers)
*/
#define MCHP_DMA_ACTV_BA(chba) \
REG8_OFS(chba, MCHP_DMA_ACTV_OFS)
#define MCHP_DMA_MSTART_BA(chba) \
REG32_OFS(chba, MCHP_DMA_MSTART_OFS)
#define MCHP_DMA_MEND_BA(chba) \
REG32_OFS(chba, MCHP_DMA_MEND_OFS)
#define MCHP_DMA_DSTART_BA(chba) \
REG32_OFS(chba, MCHP_DMA_DSTART_OFS)
#define MCHP_DMA_CTRL_BA(chba) \
REG32_OFS(chba, MCHP_DMA_CTRL_OFS)
#define MCHP_DMA_ISTS_BA(chba) \
REG8_OFS(chba, MCHP_DMA_ISTS_OFS)
#define MCHP_DMA_IEN_BA(chba) \
REG8_OFS(chba, MCHP_DMA_IEN_OFS)
#define MCHP_DMA_FSM_BA(chba) \
REG32_OFS(chba, MCHP_DMA_FSM_RO_OFS)
#define MCHP_DMA_ALU_EN_BA(chba) \
REG8_OFS(chba, MCHP_DMA_ALU_CTRL_OFS)
#define MCHP_DMA_ALU_DATA_BA(chba) \
REG32_OFS(chba, MCHP_DMA_ALU_DATA_OFS)
#define MCHP_DMA_ALU_STS_RO_BA(chba) \
REG8_OFS(chba, MCHP_DMA_ALU_STS_RO_OFS)
/*
* Channel Activate, Offset 0x00, R/W
*/
#define MCHP_DMA_ACTV_REG_MASK 0x01ul
#define MCHP_DMA_ACTV_VAL (1UL << 0)
/*
* Target (destination) Start Memory Address, Offset 0x04
*/
#define MCHP_DMA_MSTART_REG_MASK 0xFFFFFFFFul
/*
* Target (destination) End Memory Address, Offset 0x08
*/
#define MCHP_DMA_MEND_REG_MASK 0xFFFFFFFFul
/*
* Source (device) Address, Offset 0x0C
*/
#define MCHP_DMA_DSTART_REG_MASK 0xFFFFFFFFul
/*
* Control, Offset 0x10
*/
#define MCHP_DMA_C_REG_MASK 0x037FFF3Ful
#define MCHP_DMA_C_RUN (1UL << 0)
#define MCHP_DMA_C_REQ_STS_RO (1UL << 1)
#define MCHP_DMA_C_DONE_STS_RO (1UL << 2)
#define MCHP_DMA_C_CHAN_STS_MASK (0x03UL << 3)
#define MCHP_DMA_C_BUSY_STS_POS 5u
#define MCHP_DMA_C_BUSY_STS (1UL << 5)
#define MCHP_DMA_C_DIR_POS 8u
#define MCHP_DMA_C_DEV2MEM (0UL << 8)
#define MCHP_DMA_C_MEM2DEV (1UL << 8)
#define MCHP_DMA_C_DEV_NUM_POS 9u
#define MCHP_DMA_C_DEV_NUM_MASK0 0x7Ful
#define MCHP_DMA_C_DEV_NUM_MASK (0x7F << 9)
#define MCHP_DMA_C_NO_INCR_MEM (0UL << 16)
#define MCHP_DMA_C_INCR_MEM (1UL << 16)
#define MCHP_DMA_C_NO_INCR_DEV (0UL << 17)
#define MCHP_DMA_C_INCR_DEV (1UL << 17)
#define MCHP_DMA_C_LOCK_CHAN (1UL << 18)
#define MCHP_DMA_C_DIS_HWFLC (1UL << 19)
#define MCHP_DMA_C_XFRU_POS 20u
#define MCHP_DMA_C_XFRU_MASK0 0x07ul
#define MCHP_DMA_C_XFRU_MASK (0x07ul << 20)
#define MCHP_DMA_C_XFRU_1B (1UL << MCHP_DMA_C_XFRU_POS)
#define MCHP_DMA_C_XFRU_2B (2UL << MCHP_DMA_C_XFRU_POS)
#define MCHP_DMA_C_XFRU_4B (4UL << MCHP_DMA_C_XFRU_POS)
#define MCHP_DMA_C_XFER_GO (1UL << 24)
#define MCHP_DMA_C_XFER_ABORT (1UL << 25)
/* combine direction and device number fields */
#define MCHP_DMA_C_DEVDIR_POS 8u
#define MCHP_DMA_C_DEVDIR_MASK0 0xFFul
#define MCHP_DMA_C_DEVDIR_MASK (0xFFul << 8)
/*
* Channel Interrupt Status, Offset 0x14
*/
#define MCHP_DMA_STS_REG_MASK 0x07ul
#define MCHP_DMA_STS_BUS_ERR (1UL << 0)
#define MCHP_DMA_STS_FLOW_CTRL_ERR (1UL << 1)
#define MCHP_DMA_STS_DONE (1UL << 2)
#define MCHP_DMA_STS_ALL 0x07ul
/*
* Channel Interrupt Enable, Offset 0x18
*/
#define MCHP_DMA_IEN_REG_MASK 0x07ul
#define MCHP_DMA_IEN_BUS_ERR (1UL << 0)
#define MCHP_DMA_IEN_FLOW_CTRL_ERR (1UL << 1)
#define MCHP_DMA_IEN_DONE (1UL << 2)
#define MCHP_DMA_IEN_ALL 0x07ul
/*
* Channel FSM (read-only), Offset 0x1C
*/
#define MCHP_DMA_FSM_REG_MASK 0x0FFFFul
/*
* DMA Block with optional ALU includes four extra registers.
* Channel's total register allocation is 0x40
*/
/*
* ALU Control, Offset 0x20
*/
#define MCHP_DMA_ALU_CTRL_MASK 0x03ul
#define MCHP_DMA_ALU_ENABLE_POS 0
#define MCHP_DMA_ALU_MASK (1ul << (MCHP_DMA_ALU_ENABLE_POS))
#define MCHP_DMA_ALU_DISABLE (0ul << (MCHP_DMA_ALU_ENABLE_POS))
#define MCHP_DMA_ALU_ENABLE (1ul << (MCHP_DMA_ALU_ENABLE_POS))
#define MCHP_DMA_ALU_POST_XFER_EN_POS 1u
#define MCHP_DMA_ALU_POST_XFER_EN_MASK (1ul << (MCHP_DMA_ALU_POST_XFER_EN_POS))
#define MCHP_DMA_ALU_POST_XFER_DIS (0ul << (MCHP_DMA_ALU_POST_XFER_EN_POS))
#define MCHP_DMA_ALU_POST_XFER_EN (1ul << (MCHP_DMA_ALU_POST_XFER_EN_POS))
/*
* ALU Data, Offset 0x24
*/
#define MCHP_DMA_ALU_DATA_MASK 0xFFFFFFFFul
/*
* ALU Status, Offset 0x28 Read-Only
*/
#define MCHP_DMA_ALU_STS_MASK 0x0Ful
#define MCHP_DMA_ALU_STS_DONE_POS 0u
#define MCHP_DMA_ALU_STS_RUN_POS 1u
#define MCHP_DMA_ALU_STS_XFR_DONE_POS 2u
#define MCHP_DMA_ALU_STS_DATA_RDY_POS 3u
#define MCHP_DMA_ALU_STS_DONE (1ul << (MCHP_DMA_ALU_STS_DONE_POS))
#define MCHP_DMA_ALU_STS_RUN (1ul << (MCHP_DMA_ALU_STS_RUN_POS))
#define MCHP_DMA_ALU_STS_XFR_DONE (1ul << (MCHP_DMA_ALU_STS_XFR_DONE_POS))
#define MCHP_DMA_ALU_STS_DATA_RDY (1ul << ((MCHP_DMA_ALU_STS_DATA_RDY_POS))
/*
* ALU Test, Offset 0x2C Reserved
*/
#define MCHP_DMA_ALU_TEST_MASK 0xFFFFFFFFul
/*
* Channel 0 has ALU for CRC32
* Channel 1 has ALU for memory fill
* Channels 2-11 do not implement an ALU
*/
#define MCHP_DMA_NUM_CHAN 12u
#define MCHP_DMA_CHAN_SPACING 0x40ul
#define MCHP_DMA_CHAN_SPACING_POF2 6u
#define MCHP_DMA_WCRC_CHAN_ID 0u
#define MCHP_DMA_WMF_CHAN_ID 1u
#define MCHP_MAX_DMA_CHAN 12u
#define MCHP_NUM_DMA_CHAN_NO_ALU ((MCHP_MAX_DMA_CHAN) - 2)
/**
* @brief DMA Main (DMAM)
*/
typedef struct dma_main_regs
{ /*!< (@ 0x40002400) DMA Structure */
__IOM uint8_t ACTRST; /*!< (@ 0x00000000) DMA block activate/reset */
uint8_t RSVDA[3];
__IM uint32_t DATA_PKT; /*!< (@ 0x00000004) DMA data packet (RO) */
__IM uint32_t ARB_FSM; /*!< (@ 0x00000008) DMA Arbiter FSM (RO) */
} DMAM_Type;
/*
* NOTE: structure size is 0x40 (64) bytes as each channel
* is spaced every 0x40 bytes from DMA block base address.
* Channel 0 starts at offset 0x40 from DMA Main base address.
* Channels 0 and 1 include an ALU for special operations on data
* they transfer.
* Channel 0 ALU is specialized for CRC-32 calculations.
* Channel 1 ALU is specialized for memory fill.
*/
/**
* @brief DMA Channels 0 and 1 with ALU
*/
typedef struct dma_chan_alu_regs
{
__IOM uint8_t ACTV; /*!< (@ 0x00000000) DMA channel activate */
uint8_t RSVD1[3];
__IOM uint32_t MSTART; /*!< (@ 0x00000004) DMA channel memory start address */
__IOM uint32_t MEND; /*!< (@ 0x00000008) DMA channel memory end address */
__IOM uint32_t DSTART; /*!< (@ 0x0000000C) DMA channel device start address */
__IOM uint32_t CTRL; /*!< (@ 0x00000010) DMA channel control */
__IOM uint8_t ISTS; /*!< (@ 0x00000014) DMA channel interrupt status */
uint8_t RSVD2[3];
__IOM uint8_t IEN; /*!< (@ 0x00000018) DMA channel interrupt enable */
uint8_t RSVD3[3];
__IM uint32_t FSM; /*!< (@ 0x0000001C) DMA channel FSM (RO) */
__IOM uint8_t ALU_EN; /*!< (@ 0x00000020) DMA channels [0-1] ALU Enable */
uint8_t RSVD4[3];
__IOM uint32_t ALU_DATA; /*!< (@ 0x00000024) DMA channels [0-1] ALU Data */
__IOM uint8_t ALU_STS; /*!< (@ 0x00000028) DMA channels [0-1] ALU post status (RO) */
uint8_t RSVD5[3];
__IM uint32_t ALU_FSM; /*!< (@ 0x0000002C) DMA channels [0-1] ALU FSM (RO) */
uint8_t RSVD6[16]; /* pad to 0x40(64) byte size */
} DMA_CHAN_ALU_Type;
/**
* @brief DMA Channels 2 through 11 no ALU
*/
typedef struct dma_chan_regs
{
__IOM uint8_t ACTV; /*!< (@ 0x00000000) DMA channel activate */
uint8_t RSVD1[3];
__IOM uint32_t MSTART; /*!< (@ 0x00000004) DMA channel memory start address */
__IOM uint32_t MEND; /*!< (@ 0x00000008) DMA channel memory end address */
__IOM uint32_t DSTART; /*!< (@ 0x0000000C) DMA channel device start address */
__IOM uint32_t CTRL; /*!< (@ 0x00000010) DMA channel control */
__IOM uint8_t ISTS; /*!< (@ 0x00000014) DMA channel interrupt status */
uint8_t RSVD2[3];
__IOM uint8_t IEN; /*!< (@ 0x00000018) DMA channel interrupt enable */
uint8_t RSVD3[3];
__IM uint32_t FSM; /*!< (@ 0x0000001C) DMA channel FSM (RO) */
uint8_t RSVD4[0x20]; /* pad to 0x40(64) byte size */
} DMA_CHAN_Type;
#endif // #ifndef _DMA_H
/* end dma.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file mec1501_ecia.h
*MEC1501 EC Interrupt Aggregator Subsystem definitions
*/
/** @defgroup MEC1501 Peripherals ECIA
*/
#ifndef _ECIA_H
#define _ECIA_H
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
#define MCHP_ECIA_ADDR 0x4000E000ul
#define MCHP_FIRST_GIRQ 8u
#define MCHP_LAST_GIRQ 26u
#define MCHP_ECIA_GIRQ_NO_NVIC 22u
#define MCHP_ECIA_AGGR_BITMAP ((1ul << 8) + (1ul << 9) + (1ul << 10) +\
(1ul << 11) + (1ul << 12) + (1ul << 24) +\
(1ul << 25) + (1ul << 26))
#define MCHP_ECIA_DIRECT_BITMAP ((1ul << 13) + (1ul << 14) +\
(1ul << 15) + (1ul << 16) +\
(1ul << 17) + (1ul << 18) +\
(1ul << 19) + (1ul << 20) +\
(1ul << 21) + (1ul << 23))
/*
* ARM Cortex-M4 NVIC registers
* External sources are grouped by 32-bit registers.
* MEC15xx has 173 external sources requiring 6 32-bit registers.
*/
#define MCHP_NUM_NVIC_REGS 6u
#define MCHP_NVIC_SET_EN_BASE 0xE000E100ul
#define MCHP_NVIC_CLR_EN_BASE 0xE000E180ul
#define MCHP_NVIC_SET_PEND_BASE 0xE000E200ul
#define MCHP_NVIC_CLR_PEND_BASE 0xE000E280ul
#define MCHP_NVIC_ACTIVE_BASE 0xE000E800ul
#define MCHP_NVIC_PRI_BASE 0xE000E400ul
/* 0 <= n < MCHP_NUM_NVIC_REGS */
#define MCHP_NVIC_SET_EN(n) \
REG32(MCHP_NVIC_SET_EN_BASE + ((uintptr_t)(n) << 2))
#define MCHP_NVIC_CLR_EN(n) \
REG32(MCHP_NVIC_CLR_EN_BASE + ((uintptr_t)(n) << 2))
#define MCHP_NVIC_SET_PEND(n) \
REG32(MCHP_NVIC_SET_PEND_BASE + ((uintptr_t)(n) << 2))
#define MCHP_NVIC_CLR_PEND(n) \
REG32(MCHP_NVIC_CLR_PEND_BASE + ((uintptr_t)(n) << 2))
/*
* ECIA registers
* Implements 19 GIRQ's. GIRQ's aggregated interrupts source into one
* set of registers.
* For historical reason GIRQ's are numbered starting at 8 in the documentation.
* This numbering only affects the ECIA BLOCK_EN_SET, BLOCK_EN_CLR, and
* BLOCK_ACTIVE registers: GIRQ8 is bit[8], ..., GIRQ26 is bit[26].
*
* Each GIRQ is composed of 5 32-bit registers.
* +00h = GIRQ08 Source containing RW/1C status bits
* +04h = Enable Set write 1 to bit(s) to enable the corresponding source(s)
* +08h = Read-Only Result = Source AND Enable-Set
* +0Ch = Enable Clear write 1 to bit(s) to disable the corresponding source(s)
* +14h = Reserved(unused).
* +18h = GIRQ09 Source
* ...
* There are three other registers at offset 0x200, 0x204, and 0x208
* 0x200: BLOCK_EN_SET bit == 1 allows bit-wise OR of all GIRQn source
* bits to be connected to NVIC GIRQn input.
* bit[8]=GIRQ8, bit[9]=GIRQ9, ..., bit[26]=GIRQ26
* 0x204: BLOCK_EN_CLR bit == 1 disconnects bit-wise OR of GIRQn source
* bits from NVIC GIRQn input.
* 0x208: BLOCK_ACTIVE (read-only)
* bit[8]=GIRQ8 has at least one source bit enabled and active.
* ...
* bit[26]=GIRQ26 has at least one source bit enabled and active.
*
*/
/* zero based logical numbering */
#define MCHP_GIRQ08_ZID 0u
#define MCHP_GIRQ09_ZID 1u
#define MCHP_GIRQ10_ZID 2u
#define MCHP_GIRQ11_ZID 3u
#define MCHP_GIRQ12_ZID 4u
#define MCHP_GIRQ13_ZID 5u
#define MCHP_GIRQ14_ZID 6u
#define MCHP_GIRQ15_ZID 7u
#define MCHP_GIRQ16_ZID 8u
#define MCHP_GIRQ17_ZID 9u
#define MCHP_GIRQ18_ZID 10u
#define MCHP_GIRQ19_ZID 11u
#define MCHP_GIRQ20_ZID 12u
#define MCHP_GIRQ21_ZID 13u
#define MCHP_GIRQ22_ZID 14u
#define MCHP_GIRQ23_ZID 15u
#define MCHP_GIRQ24_ZID 16u
#define MCHP_GIRQ25_ZID 17u
#define MCHP_GIRQ26_ZID 18u
#define MCHP_GIRQ_ZID_MAX 19u
#define MCHP_ECIA_BLK_ENSET_OFS 0x200ul
#define MCHP_ECIA_BLK_ENCLR_OFS 0x204ul
#define MCHP_ECIA_BLK_ACTIVE_OFS 0x208ul
#define MCHP_GIRQ_BLK_ENSET_ADDR \
(MCHP_ECIA_ADDR + MCHP_ECIA_BLK_ENSET_OFS)
#define MCHP_GIRQ_BLK_ENCLR_ADDR \
(MCHP_ECIA_ADDR + MCHP_ECIA_BLK_ENCLR_OFS)
#define MCHP_GIRQ_BLK_ACTIVE_ADDR \
(MCHP_ECIA_ADDR + MCHP_ECIA_BLK_ACTIVE_OFS)
/* 8 <= n <= 26 */
#define MCHP_GIRQ_SRC_ADDR(n) \
((MCHP_ECIA_ADDR + 0x00ul) + (((uint32_t)(n) - 8ul) * 0x14ul))
#define MCHP_GIRQ_ENSET_ADDR(n) \
((MCHP_ECIA_ADDR + 0x04ul) + (((uint32_t)(n) - 8ul) * 0x14ul))
#define MCHP_GIRQ_RESULT_ADDR(n) \
((MCHP_ECIA_ADDR + 0x08ul) + (((uint32_t)(n) - 8ul) * 0x14ul))
#define MCHP_GIRQ_ENCLR_ADDR(n) \
((MCHP_ECIA_ADDR + 0x0Cul) + (((uint32_t)(n) - 8ul) * 0x14ul))
#define MCHP_GIRQ08_SRC_ADDR MCHP_GIRQ_SRC_ADDR(8)
#define MCHP_GIRQ08_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(8)
#define MCHP_GIRQ08_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(8)
#define MCHP_GIRQ08_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(8)
#define MCHP_GIRQ09_SRC_ADDR MCHP_GIRQ_SRC_ADDR(9)
#define MCHP_GIRQ09_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(9)
#define MCHP_GIRQ09_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(9)
#define MCHP_GIRQ09_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(9)
#define MCHP_GIRQ10_SRC_ADDR MCHP_GIRQ_SRC_ADDR(10)
#define MCHP_GIRQ10_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(10)
#define MCHP_GIRQ10_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(10)
#define MCHP_GIRQ10_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(10)
#define MCHP_GIRQ11_SRC_ADDR MCHP_GIRQ_SRC_ADDR(11)
#define MCHP_GIRQ11_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(11)
#define MCHP_GIRQ11_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(11)
#define MCHP_GIRQ11_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(11)
#define MCHP_GIRQ12_SRC_ADDR MCHP_GIRQ_SRC_ADDR(12)
#define MCHP_GIRQ12_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(12)
#define MCHP_GIRQ12_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(12)
#define MCHP_GIRQ12_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(12)
#define MCHP_GIRQ13_SRC_ADDR MCHP_GIRQ_SRC_ADDR(13)
#define MCHP_GIRQ13_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(13)
#define MCHP_GIRQ13_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(13)
#define MCHP_GIRQ13_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(13)
#define MCHP_GIRQ14_SRC_ADDR MCHP_GIRQ_SRC_ADDR(14)
#define MCHP_GIRQ14_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(14)
#define MCHP_GIRQ14_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(14)
#define MCHP_GIRQ14_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(14)
#define MCHP_GIRQ15_SRC_ADDR MCHP_GIRQ_SRC_ADDR(15)
#define MCHP_GIRQ15_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(15)
#define MCHP_GIRQ15_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(15)
#define MCHP_GIRQ15_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(15)
#define MCHP_GIRQ16_SRC_ADDR MCHP_GIRQ_SRC_ADDR(16)
#define MCHP_GIRQ16_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(16)
#define MCHP_GIRQ16_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(16)
#define MCHP_GIRQ16_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(16)
#define MCHP_GIRQ17_SRC_ADDR MCHP_GIRQ_SRC_ADDR(17)
#define MCHP_GIRQ17_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(17)
#define MCHP_GIRQ17_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(17)
#define MCHP_GIRQ17_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(17)
#define MCHP_GIRQ18_SRC_ADDR MCHP_GIRQ_SRC_ADDR(18)
#define MCHP_GIRQ18_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(18)
#define MCHP_GIRQ18_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(18)
#define MCHP_GIRQ18_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(18)
#define MCHP_GIRQ19_SRC_ADDR MCHP_GIRQ_SRC_ADDR(19)
#define MCHP_GIRQ19_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(19)
#define MCHP_GIRQ19_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(19)
#define MCHP_GIRQ19_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(19)
#define MCHP_GIRQ20_SRC_ADDR MCHP_GIRQ_SRC_ADDR(20)
#define MCHP_GIRQ20_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(20)
#define MCHP_GIRQ20_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(20)
#define MCHP_GIRQ20_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(20)
#define MCHP_GIRQ21_SRC_ADDR MCHP_GIRQ_SRC_ADDR(21)
#define MCHP_GIRQ21_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(21)
#define MCHP_GIRQ21_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(21)
#define MCHP_GIRQ21_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(21)
#define MCHP_GIRQ22_SRC_ADDR MCHP_GIRQ_SRC_ADDR(22)
#define MCHP_GIRQ22_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(22)
#define MCHP_GIRQ22_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(22)
#define MCHP_GIRQ22_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(22)
#define MCHP_GIRQ23_SRC_ADDR MCHP_GIRQ_SRC_ADDR(23)
#define MCHP_GIRQ23_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(23)
#define MCHP_GIRQ23_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(23)
#define MCHP_GIRQ23_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(23)
#define MCHP_GIRQ24_SRC_ADDR MCHP_GIRQ_SRC_ADDR(24)
#define MCHP_GIRQ24_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(24)
#define MCHP_GIRQ24_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(24)
#define MCHP_GIRQ24_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(24)
#define MCHP_GIRQ25_SRC_ADDR MCHP_GIRQ_SRC_ADDR(25)
#define MCHP_GIRQ25_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(25)
#define MCHP_GIRQ25_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(25)
#define MCHP_GIRQ25_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(25)
#define MCHP_GIRQ26_SRC_ADDR MCHP_GIRQ_SRC_ADDR(26)
#define MCHP_GIRQ26_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(26)
#define MCHP_GIRQ26_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(26)
#define MCHP_GIRQ26_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(26)
/*
* Register access
*/
#define MCHP_GIRQ_BLK_ENSET() \
REG32(MCHP_GIRQ_BLK_ENSET_ADDR)
#define MCHP_GIRQ_BLK_ENCLR() \
REG32(MCHP_GIRQ_BLK_ENCLR_ADDR)
#define MCHP_GIRQ_BLK_ACTIVE() \
REG32(MCHP_GIRQ_BLK_ACTIVE_ADDR)
/*
* Set/clear GIRQ Block Enable
* Check if block is active
* 8 <= n <= 26 corresponding to GIRQ08, GIRQ09, ..., GIRQ26
*/
#define MCHP_GIRQ_BLK_SETEN(n) \
REG32(MCHP_GIRQ_BLK_ENSET_ADDR) = (1ul << (uint32_t)(n))
#define MCHP_GIRQ_BLK_CLREN(n) \
REG32(MCHP_GIRQ_BLK_ENCLR_ADDR) = (1ul << (uint32_t)(n))
#define MCHP_GIRQ_BLK_IS_ACTIVE(n) \
((REG32(MCHP_GIRQ_BLK_ACTIVE_ADDR) & (1ul << (uint32_t)(n))) != 0ul)
/* 8 <= n <= 26 corresponding to GIRQ08, GIRQ09, ..., GIRQ26 */
#define MCHP_GIRQ_SRC(n) REG32(MCHP_GIRQ_SRC_ADDR(n))
#define MCHP_GIRQ_ENSET(n) REG32(MCHP_GIRQ_ENSET_ADDR(n))
#define MCHP_GIRQ_RESULT(n) REG32(MCHP_GIRQ_RESULT_ADDR(n))
#define MCHP_GIRQ_ENCLR(n) REG32(MCHP_GIRQ_ENCLR_ADDR(n))
/*
* 8 <= n <= 26 corresponding to GIRQ08, GIRQ09, ..., GIRQ26
* 0 <= pos <= 31 the bit position of the peripheral interrupt source.
*/
#define MCHP_GIRQ_SRC_CLR(n, pos) \
REG32(MCHP_GIRQ_SRC_ADDR(n)) = (1ul << (uint32_t)(pos))
#define MCHP_GIRQ_SET_EN(n, pos) \
REG32(MCHP_GIRQ_ENSET_ADDR(n)) = (1ul << (uint32_t)(pos))
#define MCHP_GIRQ_CLR_EN(n, pos) \
REG32(MCHP_GIRQ_ENCLR_ADDR(n)) = (1ul << (uint32_t)(pos))
#define MCHP_GIRQ_IS_RESULT(n, pos) \
(REG32(MCHP_GIRQ_RESULT_ADDR(n)) & (1ul << (uint32_t)(pos)) != 0ul)
/* =========================================================================*/
/* ================ ECIA ================ */
/* =========================================================================*/
enum MCHP_GIRQ_IDS {
MCHP_GIRQ08_ID = 8,
MCHP_GIRQ09_ID,
MCHP_GIRQ10_ID,
MCHP_GIRQ11_ID,
MCHP_GIRQ12_ID,
MCHP_GIRQ13_ID,
MCHP_GIRQ14_ID,
MCHP_GIRQ15_ID,
MCHP_GIRQ16_ID,
MCHP_GIRQ17_ID,
MCHP_GIRQ18_ID,
MCHP_GIRQ19_ID,
MCHP_GIRQ20_ID,
MCHP_GIRQ21_ID,
MCHP_GIRQ22_ID,
MCHP_GIRQ23_ID,
MCHP_GIRQ24_ID,
MCHP_GIRQ25_ID,
MCHP_GIRQ26_ID,
MCHP_GIRQ_ID_MAX,
};
/**
* @brief EC Interrupt Aggregator (ECIA)
*/
#define MCHP_GIRQ_START_NUM 8u
#define MCHP_GIRQ_LAST_NUM 26u
#define MCHP_GIRQ_IDX(girq) ((uint32_t)(girq) - 8ul)
#define MCHP_GIRQ_IDX_FIRST 0u
#define MCHP_GIRQ_IDX_MAX 19u
#define MCHP_MAX_NVIC_IDX 6u
/* size = 0x14(20) bytes */
typedef struct girq_regs
{
__IOM uint32_t SRC;
__IOM uint32_t EN_SET;
__IOM uint32_t RESULT;
__IOM uint32_t EN_CLR;
uint8_t RSVD1[4];
} GIRQ_Type;
typedef struct ecia_regs
{ /*!< (@ 0x4000E000) ECIA Structure */
GIRQ_Type GIRQ08; /*!< (@ 0x0000) GIRQ08 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ09; /*!< (@ 0x0014) GIRQ09 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ10; /*!< (@ 0x0028) GIRQ10 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ11; /*!< (@ 0x003C) GIRQ11 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ12; /*!< (@ 0x0050) GIRQ12 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ13; /*!< (@ 0x0064) GIRQ13 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ14; /*!< (@ 0x0078) GIRQ14 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ15; /*!< (@ 0x008C) GIRQ15 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ16; /*!< (@ 0x00A0) GIRQ16 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ17; /*!< (@ 0x00B4) GIRQ17 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ18; /*!< (@ 0x00C8) GIRQ18 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ19; /*!< (@ 0x00DC) GIRQ19 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ20; /*!< (@ 0x00F0) GIRQ20 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ21; /*!< (@ 0x0104) GIRQ21 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ22; /*!< (@ 0x0118) GIRQ22 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ23; /*!< (@ 0x012C) GIRQ23 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ24; /*!< (@ 0x0140) GIRQ24 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ25; /*!< (@ 0x0154) GIRQ25 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ26; /*!< (@ 0x0168) GIRQ26 Source, Enable Set, Result, Enable Clear, Reserved */
uint8_t RSVD2[(0x0200ul - 0x017Cul)]; /* offsets 0x017C - 0x1FF */
__IOM uint32_t BLK_EN_SET; /*! (@ 0x00000200) Aggregated GIRQ output Enable Set */
__IOM uint32_t BLK_EN_CLR; /*! (@ 0x00000204) Aggregated GIRQ output Enable Clear */
__IM uint32_t BLK_ACTIVE; /*! (@ 0x00000204) GIRQ Active bitmap (RO) */
} ECIA_Type;
#endif // #ifndef _ECIA_H
/* end ecia.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file ecs.h
*MEC1501 EC Subsystem (ECS) registers
*/
/** @defgroup MEC1501 Peripherals ECS
*/
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
#ifndef _ECS_H
#define _ECS_H
/* =========================================================================*/
/* ================ ECS ================ */
/* =========================================================================*/
#define MCHP_ECS_BASE_ADDR 0x4000FC00ul
/* AHB Error Address, write any value to clear */
#define MCHP_ECS_AHB_ERR_ADDR_OFS 0x04ul
/* AHB Error Control */
#define MCHP_ECS_AHB_ERR_CTRL_OFS 0x14ul
#define MCHP_ECS_AHB_ERR_CTRL_DIS_POS (1ul << 0)
#define MCHP_ECS_AHB_ERR_CTRL_DIS (1ul << (MCHP_ECS_AHB_ERR_CTRL_DIS_POS))
/* Interrupt Control */
#define MCHP_ECS_ICTRL_OFS 0x18ul
#define MCHP_ECS_ICTRL_DIRECT_POS 0
#define MCHP_ECS_ICTRL_DIRECT_EN (1ul << (MCHP_ECS_ICTRL_DIRECT_POS))
/* ETM Control Register */
#define MCHP_ECS_ETM_CTRL_OFS 0x1Cul
#define MCHP_ECS_ETM_CTRL_EN_POS 0
#define MCHP_ECS_ETM_CTRL_EN (1ul << (MCHP_ECS_ETM_CTRL_EN_POS))
/* Debug Control Register */
#define MCHP_ECS_DCTRL_OFS 0x20ul
#define MCHP_ECS_DCTRL_MASK 0x1Ful
#define MCHP_ECS_DCTRL_DBG_EN_POS 0u
#define MCHP_ECS_DCTRL_DBG_EN (1ul << (MCHP_ECS_DCTRL_DBG_EN_POS))
#define MCHP_ECS_DCTRL_MODE_POS 1u
#define MCHP_ECS_DCTRL_MODE_MASK0 0x03ul
#define MCHP_ECS_DCTRL_MODE_MASK \
((MCHP_ECS_DCTRL_DBG_MODE_MASK0) << (MCHP_ECS_DCTRL_DBG_MODE_POS))
#define MCHP_ECS_DCTRL_MODE_JTAG (0x00 << (MCHP_ECS_DCTRL_DBG_MODE_POS))
#define MCHP_ECS_DCTRL_MODE_SWD (0x02 << (MCHP_ECS_DCTRL_DBG_MODE_POS))
#define MCHP_ECS_DCTRL_MODE_SWD_SWV (0x01 << (MCHP_ECS_DCTRL_DBG_MODE_POS))
#define MCHP_ECS_DCTRL_PUEN_POS 3u
#define MCHP_ECS_DCTRL_PUEN (1ul << (MCHP_ECS_DCTRL_PUEN_POS))
#define MCHP_ECS_DCTRL_BSCAN_POS 4u
#define MCHP_ECS_DCTRL_BSCAN_EN (1ul << (MCHP_ECS_DCTRL_BSCAN_POS))
/* AES Hash Byte Swap Control Register */
#define MCHP_ECS_AHSW_OFS 0x2Cul
#define MCHP_ECS_AHSW_MASK 0xFFul
#define MCHP_ECS_DW_SWAP_IN_POS 0u
#define MCHP_ECS_DW_SWAP_IN_EN (1ul << (MCHP_ECS_DW_SWAP_IN_POS))
#define MCHP_ECS_DW_SWAP_OUT_POS 1u
#define MCHP_ECS_DW_SWAP_OUT_EN (1ul << (MCHP_ECS_DW_SWAP_OUT_POS))
#define MCHP_ECS_BLK_SWAP_IN_POS 2u
#define MCHP_ECS_BLK_SWAP_IN_MASK (0x07ul << (MCHP_ECS_BLK_SWAP_IN_POS))
#define MCHP_ECS_BLK_SWAP_IN_DIS (0x00ul << (MCHP_ECS_BLK_SWAP_IN_POS))
#define MCHP_ECS_BLK_SWAP_IN_8B (0x01ul << (MCHP_ECS_BLK_SWAP_IN_POS))
#define MCHP_ECS_BLK_SWAP_IN_16B (0x02ul << (MCHP_ECS_BLK_SWAP_IN_POS))
#define MCHP_ECS_BLK_SWAP_IN_64B (0x03ul << (MCHP_ECS_BLK_SWAP_IN_POS))
#define MCHP_ECS_BLK_SWAP_IN_128B (0x04ul << (MCHP_ECS_BLK_SWAP_IN_POS))
#define MCHP_ECS_BLK_SWAP_OUT_POS 5u
#define MCHP_ECS_BLK_SWAP_OUT_MASK (0x07ul << (MCHP_ECS_BLK_SWAP_OUT_POS))
#define MCHP_ECS_BLK_SWAP_OUT_DIS (0x00ul << (MCHP_ECS_BLK_SWAP_OUT_POS))
#define MCHP_ECS_BLK_SWAP_OUT_8B (0x01ul << (MCHP_ECS_BLK_SWAP_OUT_POS))
#define MCHP_ECS_BLK_SWAP_OUT_16B (0x02ul << (MCHP_ECS_BLK_SWAP_OUT_POS))
#define MCHP_ECS_BLK_SWAP_OUT_64B (0x03ul << (MCHP_ECS_BLK_SWAP_OUT_POS))
#define MCHP_ECS_BLK_SWAP_OUT_128B (0x04ul << (MCHP_ECS_BLK_SWAP_OUT_POS))
/* EC Subystem GPIO Bank Power */
#define MCHP_ECS_GBPWR_OFS 0x64ul
#define MCHP_ECS_GBPWR_LOCK_POS 7u
#define MCHP_ECS_GBPWR_LOCK (1ul << (MCHP_ECS_GBPWR_LOCK_POS))
#define MCHP_ECS_VTR3_LVL_POS 2u
#define MCHP_ECS_VTR3_LVL_18 (1ul << (MCHP_ECS_VTR3_LVL_POS))
#define MCHP_ECS_VTR2_LVL_POS 1u
#define MCHP_ECS_VTR2_LVL_18 (1ul << (MCHP_ECS_VTR2_LVL_POS))
/*
* Register Access
*/
#define MCHP_ECS_AHB_ERR() \
REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_AHB_ERR_ADDR_OFS)
#define MCHP_ECS_AHB_ERR_CTRL() \
REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_AHB_ERR_CTRL_OFS)
#define MCHP_ECS_ICTRL() \
REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_ICTRL_OFS)
#define MCHP_ECS_ETM_CTRL() \
REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_ETM_CTRL_OFS)
#define MCHP_ECS_DCTRL() \
REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_DCTRL_OFS)
#define MCHP_ECS_AHSW_CTRL() \
REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_AHSW_OFS)
#define MCHP_ECS_GBPWR() \
REG32(MCHP_ECS_BASE_ADDR + MCHP_ECS_GBPWR_OFS)
/**
* @brief EC Subsystem (ECS)
*/
typedef struct ecs_regs
{ /*!< (@ 0x4000FC00) ECS Structure */
__IOM uint8_t RSVD1[4];
__IOM uint32_t AHB_ERR_ADDR; /*!< (@ 0x0004) ECS AHB Error Address */
__IOM uint32_t TEST08;
__IOM uint32_t TEST0C;
__IOM uint32_t TEST10;
__IOM uint32_t AHB_ERR_CTRL; /*!< (@ 0x0014) ECS AHB Error Control */
__IOM uint32_t INTR_CTRL; /*!< (@ 0x0018) ECS Interupt Control */
__IOM uint32_t ETM_CTRL; /*!< (@ 0x001C) ECS ETM Trace Control */
__IOM uint32_t DEBUG_CTRL; /*!< (@ 0x0020) ECS Debug Control */
__IOM uint32_t OTP_LOCK; /*!< (@ 0x0024) ECS OTP Lock Enable */
__IOM uint32_t WDT_CNT; /*!< (@ 0x0028) ECS WDT Event Count */
__IOM uint32_t AESH_BSWAP_CTRL; /*!< (@ 0x002C) ECS AES-Hash Byte Swap Control */
__IOM uint32_t TEST30;
__IOM uint32_t TEST34;
__IOM uint32_t ADC_VREF_PWRDN; /*!< (@ 0x0038) ECS ADC Vref Power Down */
__IOM uint32_t TEST3C;
__IOM uint32_t PECI_DIS; /*!< (@ 0x0040) ECS PECI Disable */
__IOM uint32_t GPIO_PAD_TST; /*!< (@ 0x0044) ECS GPIO Pad Test */
__IOM uint32_t SMBUS_SW_EN0; /*!< (@ 0x0048) ECS SMBus SW Enable 0 */
__IOM uint32_t STAP_TMIR; /*!< (@ 0x004C) ECS STAP Test Mirror */
__IOM uint32_t VCI_FW_OVR; /*!< (@ 0x0050) ECS VCI FW Override */
__IOM uint32_t BROM_STS; /*!< (@ 0x0054) ECS Boot-ROM Status */
uint8_t RSVD2[4];
__IOM uint32_t CRYPTO_SRST; /*!< (@ 0x005C) ECS Crypto HW Soft Reset */
__IOM uint32_t TEST60;
__IOM uint32_t GPIO_BANK_PWR; /*!< (@ 0x0064) ECS GPIO Bank Power Select */
__IOM uint32_t TEST68;
__IOM uint32_t TEST6C;
__IOM uint32_t JTAG_MCFG; /*!< (@ 0x0070) ECS JTAG Master Config */
__IOM uint32_t JTAG_MSTS; /*!< (@ 0x0074) ECS JTAG Master Status */
__IOM uint32_t JTAG_MTDO; /*!< (@ 0x0078) ECS JTAG Master TDO */
__IOM uint32_t JTAG_MTDI; /*!< (@ 0x007C) ECS JTAG Master TDI */
__IOM uint32_t JTAG_MTMS; /*!< (@ 0x0080) ECS JTAG Master TMS */
__IOM uint32_t JTAG_MCMD; /*!< (@ 0x0084) ECS JTAG Master Command */
uint8_t RSVD3[8];
__IOM uint32_t VW_FW_OVR; /*!< (@ 0x0090) ECS VWire FW Override */
__IOM uint32_t CMP_CTRL; /*!< (@ 0x0094) ECS Analog Comparator Control */
__IOM uint32_t CMP_SLP_CTRL; /*!< (@ 0x0098) ECS Analog Comparator Sleep Control */
uint8_t RSVD4[(0xF0 - 0x9C)];
__IOM uint32_t IP_TRIM; /*!< (@ 0x00F0) ECS IP Trim */
uint8_t RSVD5[12];
__IOM uint32_t TEST100;
uint8_t RSVD6[(0x180 - 0x94)];
__IOM uint32_t FW_SCR0; /*!< (@ 0x0180) ECS FW Scratch 0 */
__IOM uint32_t FW_SCR1; /*!< (@ 0x0180) ECS FW Scratch 1 */
__IOM uint32_t FW_SCR2; /*!< (@ 0x0180) ECS FW Scratch 2 */
__IOM uint32_t FW_SCR3; /*!< (@ 0x0180) ECS FW Scratch 3 */
} ECS_Type;
#endif // #ifndef _ECS_H
/* end ecs.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file emi.h
*MEC1501 EC Host Memory Interface Registers
*/
/** @defgroup MEC1501 Peripherals EMI
*/
#ifndef _EMI_H
#define _EMI_H
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
/* =========================================================================*/
/* ================ EMI ================ */
/* =========================================================================*/
#define MCHP_EMI_BASE_ADDR 0x400F4000ul
#define MCHP_EMI_NUM_INSTANCES 2u
#define MCHP_EMI_SPACING 0x0400ul
#define MCHP_EMI_SPACING_PWROF2 10u
#define MCHP_EMI0_ADDR 0x400F4000ul
#define MCHP_EMI1_ADDR 0x400F4400ul
/*
* EMI interrupts
*/
#define MCHP_EMI_GIRQ 15u
#define MCHP_EMI_GIRQ_NVIC 7u
/* Direct NVIC connections */
#define MCHP_EMI0_NVIC 42u
#define MCHP_EMI1_NVIC 43u
/* GIRQ Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_EMI0_GIRQ_POS 2u
#define MCHP_EMI1_GIRQ_POS 3u
#define MCHP_EMI0_GIRQ (1ul << 2)
#define MCHP_EMI1_GIRQ (1ul << 3)
/*
* OS_INT_SRC_LSB
*/
#define MCHP_EMI_OSIS_LSB_EC_WR_POS 0u
#define MCHP_EMI_OSIS_LSB_EC_WR (1ul << 0)
/* the following bits are also apply to OS_INT_MASK_LSB */
#define MCHP_EMI_OSIS_LSB_SWI_POS 1u
#define MCHP_EMI_OSIS_LSB_SWI_MASK0 0x7Ful
#define MCHP_EMI_OSIS_LSB_SWI_MASK 0xFEul
#define MCHP_EMI_OSIS_LSB_SWI1 (1u << 1)
#define MCHP_EMI_OSIS_LSB_SWI2 (1u << 2)
#define MCHP_EMI_OSIS_LSB_SWI3 (1u << 3)
#define MCHP_EMI_OSIS_LSB_SWI4 (1u << 4)
#define MCHP_EMI_OSIS_LSB_SWI5 (1u << 5)
#define MCHP_EMI_OSIS_LSB_SWI6 (1u << 6)
#define MCHP_EMI_OSIS_LSB_SWI7 (1u << 7)
/*
* OS_INT_SRC_MSB and OS_INT_MASK_MSB
*/
#define MCHP_EMI_OSIS_MSB_SWI_POS 0u
#define MCHP_EMI_OSIS_MSB_SWI_MASK0 0xFFul
#define MCHP_EMI_OSIS_MSB_SWI_MASK 0xFFul
#define MCHP_EMI_OSIS_MSB_SWI8 (1u << 0)
#define MCHP_EMI_OSIS_MSB_SWI9 (1u << 1)
#define MCHP_EMI_OSIS_MSB_SWI10 (1u << 2)
#define MCHP_EMI_OSIS_MSB_SWI11 (1u << 3)
#define MCHP_EMI_OSIS_MSB_SWI12 (1u << 4)
#define MCHP_EMI_OSIS_MSB_SWI13 (1u << 5)
#define MCHP_EMI_OSIS_MSB_SWI14 (1u << 6)
#define MCHP_EMI_OSIS_MSB_SWI15 (1u << 7)
/*
* OS_APP_ID
*/
#define MCHP_EMI_OS_APP_ID_MASK 0xFFul
/*
* MEM_BASE_0 and MEM_BASE_1 registers
* bits[1:0] = 00b read-only forcing EC SRAM location to
* be aligned >= 4 bytes.
*/
#define MCHP_EMI_MEM_BASE_MASK 0xFFFFFFFCul
/*
* MEM_LIMIT_0 and MEM_LIMIT_1 registers are split into two fields
* bits[15:0] = read limit
* bits[1:0]=00b read-only forcing >= 4 byte alignment
* bits[31:16] = write limit
* bits[17:16]=00b read-only forcing >= 4 byte alignment
*/
#define MEM_EMI_MEM_LIMIT_MASK 0xFFFCFFFCul
#define MEM_EMI_MEM_LIMIT_RD_POS 0u
#define MEM_EMI_MEM_LIMIT_RD_MASK0 0xFFFCul
#define MEM_EMI_MEM_LIMIT_RD_MASK 0xFFFCul
#define MEM_EMI_MEM_LIMIT_WR_POS 16u
#define MEM_EMI_MEM_LIMIT_WR_MASK0 0xFFFCul
#define MEM_EMI_MEM_LIMIT_WR_MASK (0xFFFCul << 16)
/*
* EC_SET_OS_INT and EC_OS_INT_CLR_EN
*/
#define MCHP_EMI_EC_OS_SWI_MASK 0xFFFEul
#define MCHP_EMI_EC_OS_SWI1 (1ul << 1)
#define MCHP_EMI_EC_OS_SWI2 (1ul << 2)
#define MCHP_EMI_EC_OS_SWI3 (1ul << 3)
#define MCHP_EMI_EC_OS_SWI4 (1ul << 4)
#define MCHP_EMI_EC_OS_SWI5 (1ul << 5)
#define MCHP_EMI_EC_OS_SWI6 (1ul << 6)
#define MCHP_EMI_EC_OS_SWI7 (1ul << 7)
#define MCHP_EMI_EC_OS_SWI8 (1ul << 8)
#define MCHP_EMI_EC_OS_SWI9 (1ul << 9)
#define MCHP_EMI_EC_OS_SWI10 (1ul << 10)
#define MCHP_EMI_EC_OS_SWI11 (1ul << 11)
#define MCHP_EMI_EC_OS_SWI12 (1ul << 12)
#define MCHP_EMI_EC_OS_SWI13 (1ul << 13)
#define MCHP_EMI_EC_OS_SWI14 (1ul << 14)
#define MCHP_EMI_EC_OS_SWI15 (1ul << 15)
/**
* @brief EMI Registers (EMI)
*/
typedef struct emi_regs
{
__IOM uint8_t OS_H2E_MBOX; /*!< (@ 0x0000) OS space Host to EC mailbox register */
__IOM uint8_t OS_E2H_MBOX; /*!< (@ 0x0001) OS space EC to Host mailbox register */
__IOM uint8_t OS_EC_ADDR_LSB; /*!< (@ 0x0002) OS space EC memory address LSB register */
__IOM uint8_t OS_EC_ADDR_MSB; /*!< (@ 0x0003) OS space EC memory address LSB register */
__IOM uint32_t OS_EC_DATA; /*!< (@ 0x0004) OS space EC Data register */
__IOM uint8_t OS_INT_SRC_LSB; /*!< (@ 0x0008) OS space Interrupt Source LSB register */
__IOM uint8_t OS_INT_SRC_MSB; /*!< (@ 0x0009) OS space Interrupt Source MSB register */
__IOM uint8_t OS_INT_MASK_LSB; /*!< (@ 0x000A) OS space Interrupt Mask LSB register */
__IOM uint8_t OS_INT_MASK_MSB; /*!< (@ 0x000B) OS space Interrupt Mask MSB register */
__IOM uint32_t OS_APP_ID; /*!< (@ 0x000C) OS space Application ID register */
uint8_t RSVD1[0x100u - 0x10u];
__IOM uint8_t H2E_MBOX; /*!< (@ 0x0100) Host to EC mailbox */
__IOM uint8_t E2H_MBOX; /*!< (@ 0x0101) EC Data */
uint8_t RSVD2[2];
__IOM uint32_t MEM_BASE_0; /*!< (@ 0x0104) EC memory region 0 base address */
__IOM uint32_t MEM_LIMIT_0; /*!< (@ 0x0108) EC memory region 0 read/write limits */
__IOM uint32_t MEM_BASE_1; /*!< (@ 0x010C) EC memory region 1 base address */
__IOM uint32_t MEM_LIMIT_1; /*!< (@ 0x0110) EC memory region 1 read/write limits */
__IOM uint16_t EC_OS_INT_SET; /*!< (@ 0x0114) Set OS interrupt source */
__IOM uint16_t EC_OS_INT_CLR_EN; /*!< (@ 0x0116) OS interrupt source clear enable */
} EMI_Type;
#endif /* #ifndef _EMI_H */
/* end emi.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file espi_io.h
*MEC1501 eSPI IO Component definitions
*/
/** @defgroup MEC1501 Peripherals eSPI IO Component
*/
#ifndef _ESPI_IO_H
#define _ESPI_IO_H
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
/*------------------------------------------------------------------*/
#define MCHP_ESPI_IO_BASE_ADDR 0x400F3400ul
/*
* ESPI IO Component interrupts
*/
#define MCHP_ESPI_IO_GIRQ 19u
#define MCHP_ESPI_IO_GIRQ_NVIC 11u
/* Direct mode NVIC inputs */
#define MCHP_ESPI_PC_NVIC 103u
#define MCHP_ESPI_BM1_NVIC 104u
#define MCHP_ESPI_BM2_NVIC 105u
#define MCHP_ESPI_LTR_NVIC 106u
#define MCHP_ESPI_OOB_UP_NVIC 107u
#define MCHP_ESPI_OOB_DN_NVIC 108u
#define MCHP_ESPI_FC_NVIC 109u
#define MCHP_ESPI_ESPI_RST_NVIC 110u
#define MCHP_ESPI_VW_EN_NVIC 156u
/* GIRQ Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_ESPI_PC_GIRQ_POS 0u
#define MCHP_ESPI_BM1_GIRQ_POS 1u
#define MCHP_ESPI_BM2_GIRQ_POS 2u
#define MCHP_ESPI_LTR_GIRQ_POS 3u
#define MCHP_ESPI_OOB_UP_GIRQ_POS 4u
#define MCHP_ESPI_OOB_DN_GIRQ_POS 5u
#define MCHP_ESPI_FC_GIRQ_POS 6u
#define MCHP_ESPI_ESPI_RST_GIRQ_POS 7u
#define MCHP_ESPI_VW_EN_GIRQ_POS 8u
/*
* !!!! NOTE !!!!
* eSPI SAF Done and Error interrupt signals do not
* have direct mode NVIC connections.
* GIRQ19 cannot be configured for direct mode unless
* SAF interrupt are not used.
*/
#define MCHP_ESPI_SAF_DONE_GIRQ_POS 9u /* No direct NVIC connection */
#define MCHP_ESPI_SAF_ERR_GIRQ_POS 10u /* No direct NVIC connection */
#define MCHP_ESPI_PC_GIRQ_VAL (1ul << 0)
#define MCHP_ESPI_BM1_GIRQ_VAL (1ul << 1)
#define MCHP_ESPI_BM2_GIRQ_VAL (1ul << 2)
#define MCHP_ESPI_LTR_GIRQ_VAL (1ul << 3)
#define MCHP_ESPI_OOB_UP_GIRQ_VAL (1ul << 4)
#define MCHP_ESPI_OOB_DN_GIRQ_VAL (1ul << 5)
#define MCHP_ESPI_FC_GIRQ_VAL (1ul << 6)
#define MCHP_ESPI_ESPI_RST_GIRQ_VAL (1ul << 7)
#define MCHP_ESPI_VW_EN_GIRQ_VAL (1ul << 8)
#define MCHP_ESPI_SAF_DONE_GIRQ_VAL (1ul << 9)
#define MCHP_ESPI_SAF_ERR_GIRQ_VAL (1ul << 10)
/* eSPI Global Capabilities 0 */
#define MCHP_ESPI_GBL_CAP0_MASK 0x0Fu
#define MCHP_ESPI_GBL_CAP0_PC_SUPP (1u << 0)
#define MCHP_ESPI_GBL_CAP0_VW_SUPP (1u << 1)
#define MCHP_ESPI_GBL_CAP0_OOB_SUPP (1u << 2)
#define MCHP_ESPI_GBL_CAP0_FC_SUPP (1u << 3)
/* eSPI Global Capabilities 1 */
#define MCHP_ESPI_GBL_CAP1_MASK 0xFFu
#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_POS 0u
#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_MASK 0x07u
#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_20M 0x00u
#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_25M 0x01u
#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_33M 0x02u
#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_50M 0x03u
#define MCHP_ESPI_GBL_CAP1_MAX_FREQ_66M 0x04u
#define MCHP_ESPI_GBL_CAP1_ALERT_POS 3u /* Read-Only */
#define MCHP_ESPI_GBL_CAP1_ALERT_DED_PIN \
(1u << (MCHP_ESPI_GBL_CAP1_ALERT_POS))
#define MCHP_ESPI_GBL_CAP1_ALERT_ON_IO1 \
(0u << (MCHP_ESPI_GBL_CAP1_ALERT_POS))
#define MCHP_ESPI_GBL_CAP1_IO_MODE_POS 4u
#define MCHP_ESPI_GBL_CAP1_IO_MODE_MASK0 0x03u
#define MCHP_ESPI_GBL_CAP1_IO_MODE_MASK \
((MCHP_ESPI_GBL_CAP1_IO_MODE_MASK0) << (MCHP_ESPI_GBL_CAP1_IO_MODE_POS))
#define MCHP_ESPI_GBL_CAP1_IO_MODE0_1 0u
#define MCHP_ESPI_GBL_CAP1_IO_MODE0_12 1u
#define MCHP_ESPI_GBL_CAP1_IO_MODE0_14 2u
#define MCHP_ESPI_GBL_CAP1_IO_MODE0_124 3u
#define MCHP_ESPI_GBL_CAP1_IO_MODE_1 \
((MCHP_ESPI_GBL_CAP1_IO_MODE0_1) << (MCHP_ESPI_GBL_CAP1_IO_MODE_POS))
#define MCHP_ESPI_GBL_CAP1_IO_MODE_12 \
((MCHP_ESPI_GBL_CAP1_IO_MODE0_12) << (MCHP_ESPI_GBL_CAP1_IO_MODE_POS))
#define MCHP_ESPI_GBL_CAP1_IO_MODE_14 \
((MCHP_ESPI_GBL_CAP1_IO_MODE0_14) << (MCHP_ESPI_GBL_CAP1_IO_MODE_POS))
#define MCHP_ESPI_GBL_CAP1_IO_MODE_124 \
((MCHP_ESPI_GBL_CAP1_IO_MODE0_124) << (MCHP_ESPI_GBL_CAP1_IO_MODE_POS))
/*
* Support Open Drain ALERT pin configuration
* EC sets this bit if it can support open-drain ESPI_ALERT#
*/
#define MCHP_ESPI_GBL_CAP1_ALERT_ODS_POS 6u
#define MCHP_ESPI_GBL_CAP1_ALERT_ODS \
(1u << (MCHP_ESPI_GBL_CAP1_ALERT_ODS_POS))
/*
* Read-Only ALERT Open Drain select.
* If EC has indicated it can support open-drain ESPI_ALERT# then
* the Host can enable open-drain ESPI_ALERT# by sending a configuraiton
* message. This read-only bit relects the configuration selection.
*/
#define MCHP_ESPI_GBL_CAP1_ALERT_ODS_SEL_POS 7u
#define MCHP_ESPI_GBL_CAP1_ALERT_SEL_ODS \
(1u << (MCHP_ESPI_GBL_CAP1_ALERT_ODS_SEL_POS))
/* Peripheral Channel(PC) Capabilites */
#define MCHP_ESPI_PC_CAP_MASK 0x07u
#define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_MASK 0x07u
#define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_64 0x01u
#define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_128 0x02u
#define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_256 0x03u
/* Virtual Wire(VW) Capabilities */
#define MCHP_ESPI_VW_CAP_MASK 0x3Fu
#define MCHP_ESPI_VW_CAP_MAX_VW_CNT_MASK 0x3Fu
/* Out-of-Band(OOB) Capabilities */
#define MCHP_ESPI_OOB_CAP_MASK 0x07u
#define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_MASK 0x07u
#define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_73 0x01u
#define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_137 0x02u
#define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_265 0x03u
/* Flash Channel(FC) Capabilities */
#define MCHP_ESPI_FC_CAP_MASK 0xFFu
#define MCHP_ESPI_FC_CAP_MAX_PLD_SZ_MASK 0x07u
#define MCHP_ESPI_FC_CAP_MAX_PLD_SZ_64 0x01u
#define MCHP_ESPI_FC_CAP_SHARE_POS 3u
#define MCHP_ESPI_FC_CAP_SHARE_MASK0 0x03u
#define MCHP_ESPI_FC_CAP_SHARE_MASK \
((MCHP_ESPI_FC_CAP_SHARE_MASK0) << (MCHP_ESPI_FC_CAP_SHARE_POS))
#define MCHP_ESPI_FC_CAP_SHARE_MAF_ONLY \
(0u << (MCHP_ESPI_FC_CAP_SHARE_POS))
#define MCHP_ESPI_FC_CAP_SHARE_MAF2_ONLY \
(1u << (MCHP_ESPI_FC_CAP_SHARE_POS))
#define MCHP_ESPI_FC_CAP_SHARE_SAF_ONLY \
(2u << (MCHP_ESPI_FC_CAP_SHARE_POS))
#define MCHP_ESPI_FC_CAP_SHARE_MAF_SAF \
(3u << (MCHP_ESPI_FC_CAP_SHARE_POS))
#define MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS 5u
#define MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK0 0x07u
#define MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK \
((MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK0) << (MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS))
#define MCHP_ESPI_FC_CAP_MAX_RD_SZ_64 \
((0x01u) << (MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS))
/* PC Ready */
#define MCHP_ESPI_PC_READY_MASK 0x01u;
#define MCHP_ESPI_PC_READY 0x01u;
/* OOB Ready */
#define MCHP_ESPI_OOB_READY_MASK 0x01u;
#define MCHP_ESPI_OOB_READY 0x01u;
/* FC Ready */
#define MCHP_ESPI_FC_READY_MASK 0x01u;
#define MCHP_ESPI_FC_READY 0x01u;
/* ESPI_RESET# Interrupt Status */
#define MCHP_ESPI_RST_ISTS_MASK 0x03u;
#define MCHP_ESPI_RST_ISTS_POS 0u
#define MCHP_ESPI_RST_ISTS (1u << (MCHP_ESPI_RST_ISTS_POS))
#define MCHP_ESPI_RST_ISTS_PIN_RO_POS 1ul
#define MCHP_ESPI_RST_ISTS_PIN_RO_HI (1u << (MCHP_ESPI_RST_ISTS_PIN_RO_POS))
/* ESPI_RESET# Interrupt Enable */
#define MCHP_ESPI_RST_IEN_MASK 0x01ul
#define MCHP_ESPI_RST_IEN 0x01ul
/* eSPI Platform Reset Source */
#define MCHP_ESPI_PLTRST_SRC_MASK 0x01ul
#define MCHP_ESPI_PLTRST_SRC_POS 0ul
#define MCHP_ESPI_PLTRST_SRC_IS_PIN 0x01ul
#define MCHP_ESPI_PLTRST_SRC_IS_VW 0x00ul
/* VW Ready */
#define MCHP_ESPI_VW_READY_MASK 0x01ul
#define MCHP_ESPI_VW_READY 0x01ul
/* VW Error Status */
#define MCHP_ESPI_VW_ERR_STS_MASK 0x33ul
#define MCHP_ESPI_VW_ERR_STS_FATAL_POS 0u
#define MCHP_ESPI_VW_ERR_STS_FATAL_RO \
(1u << (MCHP_ESPI_VW_ERR_STS_FATAL_POS))
#define MCHP_ESPI_VW_ERR_STS_FATAL_CLR_POS 1u
#define MCHP_ESPI_VW_ERR_STS_FATAL_CLR_WO \
(1u << (MCHP_ESPI_VW_ERR_STS_FATAL_CLR_POS))
#define MCHP_ESPI_VW_ERR_STS_NON_FATAL_POS 4u
#define MCHP_ESPI_VW_ERR_STS_NON_FATAL_RO \
(1u << (MCHP_ESPI_VW_ERR_STS_NON_FATAL_POS))
#define MCHP_ESPI_VW_ERR_STS_NON_FATAL_CLR_POS 5u
#define MCHP_ESPI_VW_ERR_STS_NON_FATAL_CLR_WO \
(1u << (MCHP_ESPI_VW_ERR_STS_NON_FATAL_CLR_POS))
/* VW Channel Enable Status */
#define MCHP_ESPI_VW_EN_STS_MASK 0x01ul
#define MCHP_ESPI_VW_EN_STS_RO 0x01ul
/* =========================================================================*/
/* ================ eSPI IO Component ================ */
/* =========================================================================*/
/**
* @brief ESPI Host interface IO Component (MCHP_ESPI_IO)
*/
/*
* ESPI_IO_CAP - eSPI IO capabilities, channel ready, activate,
* EC
* registers @ 0x400F36B0
*/
typedef struct espi_io_cap_regs {
__IOM uint32_t VW_EN_STS; /*! (@ 0x36B0) Virtual Wire Enable Status */
uint8_t RSVD1[0x36E0 - 0x36B4];
__IOM uint8_t CAP_ID; /*! (@ 0x36E0) Capabilities ID */
__IOM uint8_t GLB_CAP0; /*! (@ 0x36E1) Global Capabilities 0 */
__IOM uint8_t GLB_CAP1; /*! (@ 0x36E2) Global Capabilities 1 */
__IOM uint8_t PC_CAP; /*! (@ 0x3633) Periph Chan Capabilities */
__IOM uint8_t VW_CAP; /*! (@ 0x3634) Virtual Wire Chan Capabilities */
__IOM uint8_t OOB_CAP; /*! (@ 0x3635) OOB Chan Capabilities */
__IOM uint8_t FC_CAP; /*! (@ 0x3636) Flash Chan Capabilities */
__IOM uint8_t PC_RDY; /*! (@ 0x3637) PC ready */
__IOM uint8_t OOB_RDY; /*! (@ 0x3638) OOB ready */
__IOM uint8_t FC_RDY; /*! (@ 0x3639) OOB ready */
__IOM uint8_t ERST_STS; /*! (@ 0x363A) eSPI Reset interrupt status */
__IOM uint8_t ERST_IEN; /*! (@ 0x363B) eSPI Reset interrupt enable */
__IOM uint8_t PLTRST_SRC; /*! (@ 0x363C) Platform Reset Source */
__IOM uint8_t VW_RDY; /*! (@ 0x363D) VW ready */
uint8_t RSVD2[0x37F0u - 0x36EE];
__IOM uint32_t VW_ERR_STS; /*! (@ 0x37F0) IO Virtual Wire Error */
} ESPI_IO_CAP_Type;
/*
* MCHP_ESPI_IO_PC - eSPI IO Peripheral Channel registers @ 0x400F3500
*/
/*
* Peripheral Channel Last Cycle length, type, and tag.
*/
#define MCHP_ESPI_PC_LC_LEN_POS 0u
#define MCHP_ESPI_PC_LC_LEN_MASK0 0x0FFFul
#define MCHP_ESPI_PC_LC_LEN_MASK 0x0FFFul
#define MCHP_ESPI_PC_LC_TYPE_POS 12u
#define MCHP_ESPI_PC_LC_TYPE_MASK0 0xFFul
#define MCHP_ESPI_PC_LC_TYPE_MASK (0xFFul << 12)
#define MCHP_ESPI_PC_LC_TAG_POS 20u
#define MCHP_ESPI_PC_LC_TAG_MASK0 0x0Ful
#define MCHP_ESPI_PC_LC_TAG_MASK (0x0Ful << 20)
/*
* Peripheral Channel Status
* Bus error, Channel enable change, and Bus master enable change.
*/
#define MCHP_ESPI_PC_STS_BUS_ERR_POS 16u
#define MCHP_ESPI_PC_STS_BUS_ERR (1ul << 16) /* RW1C */
#define MCHP_ESPI_PC_STS_EN_POS 24u
#define MCHP_ESPI_PC_STS_EN (1ul << 24) /* RO */
#define MCHP_ESPI_PC_STS_EN_CHG_POS 25u
#define MCHP_ESPI_PC_STS_EN_CHG (1ul << 25) /* RW1C */
#define MCHP_ESPI_PC_STS_BM_EN_POS 27u
#define MCHP_ESPI_PC_STS_BM_EN (1ul << 27) /* RO */
#define MCHP_ESPI_PC_STS_BM_EN_CHG_POS 28u
#define MCHP_ESPI_PC_STS_BM_EN_CHG (1ul << 28) /* RW1C */
/*
* Peripheral Channel Interrupt Enables for
* Bus error, Channel enable change, and Bus master enable change.
*/
#define MCHP_ESPI_PC_IEN_BUS_ERR_POS 16u
#define MCHP_ESPI_PC_IEN_BUS_ERR (1ul << 16)
#define MCHP_ESPI_PC_IEN_EN_CHG_POS 25u
#define MCHP_ESPI_PC_IEN_EN_CHG (1ul << 25)
#define MCHP_ESPI_PC_IEN_BM_EN_CHG_POS 28u
#define MCHP_ESPI_PC_IEN_BM_EN_CHG (1ul << 28)
typedef struct espi_io_pc_regs
{
__IOM uint32_t PC_LC_ADDR_LSW; /*! (@ 0x0000) Periph Chan Last Cycle address LSW */
__IOM uint32_t PC_LC_ADDR_MSW; /*! (@ 0x0004) Periph Chan Last Cycle address MSW */
__IOM uint32_t PC_LC_LEN_TYPE_TAG; /*! (@ 0x0008) Periph Chan Last Cycle length/type/tag */
__IOM uint32_t PC_ERR_ADDR_LSW; /*! (@ 0x000C) Periph Chan Error Address LSW */
__IOM uint32_t PC_ERR_ADDR_MSW; /*! (@ 0x0010) Periph Chan Error Address MSW */
__IOM uint32_t PC_STATUS; /*! (@ 0x0014) Periph Chan Status */
__IOM uint32_t PC_IEN; /*! (@ 0x0018) Periph Chan IEN */
} ESPI_IO_PC_Type;
/*
* ESPI_IO_LTR - eSPI IO LTR registers @ 0x400F3620
*/
#define MCHP_ESPI_LTR_STS_TX_DONE_POS 0u
#define MCHP_ESPI_LTR_STS_TX_DONE (1ul << 0) /* RW1C */
#define MCHP_ESPI_LTR_STS_OVRUN_POS 3u
#define MCHP_ESPI_LTR_STS_OVRUN (1ul << 3) /* RW1C */
#define MCHP_ESPI_LTR_STS_HDIS_POS 4u
#define MCHP_ESPI_LTR_STS_HDIS (1ul << 4) /* RW1C */
#define MCHP_ESPI_LTR_STS_TX_BUSY_POS 8u
#define MCHP_ESPI_LTR_STS_TX_BUSY (1ul << 8) /* RO */
#define MCHP_ESPI_LTR_IEN_TX_DONE_POS 0u
#define MCHP_ESPI_LTR_IEN_TX_DONE (1ul << 0)
#define MCHP_ESPI_LTR_CTRL_START_POS 0u
#define MCHP_ESPI_LTR_CTRL_START (1ul << 0)
#define MCHP_ESPI_LTR_CTRL_TAG_POS 8u
#define MCHP_ESPI_LTR_CTRL_TAG_MASK0 0x0Ful
#define MCHP_ESPI_LTR_CTRL_TAG_MASK (0x0Ful << 8)
#define MCHP_ESPI_LTR_MSG_VAL_POS 0u
#define MCHP_ESPI_LTR_MSG_VAL_MASK0 0x3FFul
#define MCHP_ESPI_LTR_MSG_VAL_MASK (0x3FFul << 0)
#define MCHP_ESPI_LTR_MSG_SC_POS 10u
#define MCHP_ESPI_LTR_MSG_SC_MASK0 0x07ul
#define MCHP_ESPI_LTR_MSG_SC_MASK (0x07ul << 10)
#define MCHP_ESPI_LTR_MSG_RT_POS 13u
#define MCHP_ESPI_LTR_MSG_RT_MASK0 0x03ul
#define MCHP_ESPI_LTR_MSG_RT_MASK (0x03ul << 13)
/* eSPI specification indicates RT field must be 00b */
#define MCHP_ESPI_LTR_MSG_RT_VAL (0x00ul << 13)
#define MCHP_ESPI_LTR_MSG_REQ_POS 15u
/* inifinite latency(default) */
#define MCHP_ESPI_LTR_MSG_REQ_INF (0ul << 15)
/* latency computed from VAL and SC(scale) fields */
#define MCHP_ESPI_LTR_MSG_REQ_VAL (1ul << 15)
typedef struct espi_io_ltr_regs
{
__IOM uint32_t LTR_STS; /*! (@ 0x0000) LTR Periph Status */
__IOM uint32_t LTR_IEN; /*! (@ 0x0004) LTR Periph Interrupt Enable */
__IOM uint32_t LTR_CTRL; /*! (@ 0x0008) LTR Periph Control */
__IOM uint32_t LTR_MSG; /*! (@ 0x000C) LTR Periph Message */
} ESPI_IO_LTR_Type;
/*
* ESPI_IO_OOB - eSPI IO OOB registers @ 0x400F3640
*/
#define MCHP_ESPI_OOB_RX_ADDR_LSW_MASK 0xFFFFFFFCul
#define MCHP_ESPI_OOB_TX_ADDR_LSW_MASK 0xFFFFFFFCul
/* RX_LEN register */
/* Number of bytes received (RO) */
#define MCHP_ESPI_OOB_RX_LEN_POS 0u
#define MCHP_ESPI_OOB_RX_LEN_MASK 0x3FFFul
/* Recieve buffer length field (RW) */
#define MCHP_ESPI_OOB_RX_BUF_LEN_POS 16u
#define MCHP_ESPI_OOB_RX_BUF_LEN_MASK0 0x3FFFul
#define MCHP_ESPI_OOB_RX_BUF_LEN_MASK (0x3FFFul << 16)
/* TX_LEN register */
#define MCHP_ESPI_OOB_TX_MSG_LEN_POS 0u
#define MCHP_ESPI_OOB_TX_MSG_LEN_MASK 0x3FFFul
/* RX_CTRL */
/* Set AVAIL bit to indicate SRAM Buffer and size has been configured */
#define MCHP_ESPI_OOB_RX_CTRL_AVAIL_POS 0u
#define MCHP_ESPI_OOB_RX_CTRL_AVAIL (1ul << 0) /* WO */
#define MCHP_ESPI_OOB_RX_CTRL_CHEN_POS 9u
#define MCHP_ESPI_OOB_RX_CTRL_CHEN (1ul << 9) /* RO */
/* Copy of eSPI OOB Capabilities max. payload size */
#define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_POS 16u
#define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_MASK0 0x07u
#define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_MASK (0x07u << 16) /* RO */
/* RX_IEN */
#define MCHP_ESPI_OOB_RX_IEN_POS 0u
#define MCHP_ESPI_OOB_RX_IEN (1ul << 0)
/* RX_STS */
#define MCHP_ESPI_OOB_RX_STS_DONE_POS 0u
#define MCHP_ESPI_OOB_RX_STS_DONE (1ul << 0) /* RW1C */
#define MCHP_ESPI_OOB_RX_STS_IBERR_POS 1u
#define MCHP_ESPI_OOB_RX_STS_IBERR (1ul << 1) /* RW1C */
#define MCHP_ESPI_OOB_RX_STS_OVRUN_POS 2u
#define MCHP_ESPI_OOB_RX_STS_OVRUN (1ul << 2) /* RW1C */
#define MCHP_ESPI_OOB_RX_STS_RXEN_POS 3u
#define MCHP_ESPI_OOB_RX_STS_RXEN (1ul << 3) /* RO */
#define MCHP_ESPI_OOB_RX_STS_TAG_POS 8u
#define MCHP_ESPI_OOB_RX_STS_TAG_MASK0 0x0Ful
#define MCHP_ESPI_OOB_RX_STS_TAG_MASK (0x0Ful << 8) /* RO */
#define MCHP_ESPI_OOB_RX_STS_ALL_RW1C 0x0Ful
/* TX_CTRL */
#define MCHP_ESPI_OOB_TX_CTRL_START_POS 0u
#define MCHP_ESPI_OOB_TX_CTRL_START (1ul << 0) /* WO */
#define MCHP_ESPI_OOB_TX_CTRL_TAG_POS 8u
#define MCHP_ESPI_OOB_TX_CTRL_TAG_MASK0 0x0Ful
#define MCHP_ESPI_OOB_TX_CTRL_TAG_MASK (0x0Ful << 8) /* RW */
/* TX_IEN */
#define MCHP_ESPI_OOB_TX_IEN_DONE_POS 0u
#define MCHP_ESPI_OOB_TX_IEN_DONE (1ul << 0)
#define MCHP_ESPI_OOB_TX_IEN_CHG_EN_POS 1u
#define MCHP_ESPI_OOB_TX_IEN_CHG_EN (1ul << 1)
#define MCHP_ESPI_OOB_TX_IEN_ALL 0x03ul
/* TX_STS */
#define MCHP_ESPI_OOB_TX_STS_DONE_POS 0u
#define MCHP_ESPI_OOB_TX_STS_DONE (1ul << 0) /* RW1C */
#define MCHP_ESPI_OOB_TX_STS_CHG_EN_POS 1u
#define MCHP_ESPI_OOB_TX_STS_CHG_EN (1ul << 1) /* RW1C */
#define MCHP_ESPI_OOB_TX_STS_IBERR_POS 2u
#define MCHP_ESPI_OOB_TX_STS_IBERR (1ul << 2) /* RW1C */
#define MCHP_ESPI_OOB_TX_STS_OVRUN_POS 3u
#define MCHP_ESPI_OOB_TX_STS_OVRUN (1ul << 3) /* RW1C */
#define MCHP_ESPI_OOB_TX_STS_BADREQ_POS 5u
#define MCHP_ESPI_OOB_TX_STS_BADREQ (1ul << 5) /* RW1C */
#define MCHP_ESPI_OOB_TX_STS_BUSY_POS 8u
#define MCHP_ESPI_OOB_TX_STS_BUSY (1ul << 8) /* RO */
/* Read-only copy of OOB Channel Enabled bit */
#define MCHP_ESPI_OOB_TX_STS_CHEN_POS 9u
#define MCHP_ESPI_OOB_TX_STS_CHEN (1ul << 9) /* RO */
#define MCHP_ESPI_OOB_TX_STS_ALL_RW1C 0x2Ful
typedef struct espi_io_oob_regs
{
__IOM uint32_t RX_ADDR_LSW; /*! (@ 0x0000) OOB Receive Address bits[31:0] */
__IOM uint32_t RX_ADDR_MSW; /*! (@ 0x0004) OOB Receive Address bits[63:32] */
__IOM uint32_t TX_ADDR_LSW; /*! (@ 0x0008) OOB Transmit Address bits[31:0] */
__IOM uint32_t TX_ADDR_MSW; /*! (@ 0x000C) OOB Transmit Address bits[63:32] */
__IOM uint32_t RX_LEN; /*! (@ 0x0010) OOB Receive length */
__IOM uint32_t TX_LEN; /*! (@ 0x0014) OOB Transmit length */
__IOM uint32_t RX_CTRL; /*! (@ 0x0018) OOB Receive control */
__IOM uint32_t RX_IEN; /*! (@ 0x001C) OOB Receive interrupt enable */
__IOM uint32_t RX_STS; /*! (@ 0x0020) OOB Receive interrupt status */
__IOM uint32_t TX_CTRL; /*! (@ 0x0024) OOB Transmit control */
__IOM uint32_t TX_IEN; /*! (@ 0x0028) OOB Transmit interrupt enable */
__IOM uint32_t TX_STS; /*! (@ 0x002C) OOB Transmit interrupt status */
} ESPI_IO_OOB_Type;
/*
* MCHP_ESPI_IO_FC - eSPI IO Flash channel registers @ 0x40003680
*/
/* MEM_ADDR_LSW */
#define MCHP_ESPI_FC_MEM_ADDR_LSW_MASK 0xFFFFFFFCul
/* CTRL */
#define MCHP_ESPI_FC_CTRL_START_POS 0u
#define MCHP_ESPI_FC_CTRL_START (1ul << 0) /* WO */
#define MCHP_ESPI_FC_CTRL_FUNC_POS 2u
#define MCHP_ESPI_FC_CTRL_FUNC_MASK0 0x03ul
#define MCHP_ESPI_FC_CTRL_FUNC_MASK (0x03ul << 2) /* RW */
#define MCHP_ESPI_FC_CTRL_RD0 0x00ul
#define MCHP_ESPI_FC_CTRL_WR0 0x01ul
#define MCHP_ESPI_FC_CTRL_ERS0 0x02ul
#define MCHP_ESPI_FC_CTRL_ERL0 0x03ul
#define MCHP_ESPI_FC_CTRL_FUNC(f) \
(((uint32_t)(f) & MCHP_ESPI_FC_CTRL_FUNC_MASK0) << MCHP_ESPI_FC_CTRL_FUNC_POS)
#define MCHP_ESPI_FC_CTRL_TAG_POS 4u
#define MCHP_ESPI_FC_CTRL_TAG_MASK0 0x0Ful
#define MCHP_ESPI_FC_CTRL_TAG_MASK (0x0Ful << 4)
#define MCHP_ESPI_FC_CTRL_TAG(t) \
(((uint32_t)(t) & MCHP_ESPI_FC_CTRL_TAG_MASK0) << MCHP_ESPI_FC_CTRL_TAG_POS)
#define MCHP_ESPI_FC_CTRL_ABORT_POS 16u
#define MCHP_ESPI_FC_CTRL_ABORT (1ul << 16) /* WO */
/* IEN */
#define MCHP_ESPI_FC_IEN_DONE_POS 0u
#define MCHP_ESPI_FC_IEN_DONE (1ul << 0)
#define MCHP_ESPI_FC_IEN_CHG_EN_POS 1u
#define MCHP_ESPI_FC_IEN_CHG_EN (1ul << 1)
/* CFG */
#define MCHP_ESPI_FC_CFG_BUSY_POS 0u
#define MCHP_ESPI_FC_CFG_BUSY (1ul << 0) /* RO */
#define MCHP_ESPI_FC_CFG_ERBSZ_POS 2u
#define MCHP_ESPI_FC_CFG_ERBSZ_MASK0 0x07ul
#define MCHP_ESPI_FC_CFG_ERBSZ_MASK (0x07ul << 2) /* RO */
#define MCHP_ESPI_FC_CFG_ERBSZ_4K (0x01ul << 2)
#define MCHP_ESPI_FC_CFG_ERBSZ_64K (0x02ul << 2)
#define MCHP_ESPI_FC_CFG_ERBSZ_4K_64K (0x03ul << 2)
#define MCHP_ESPI_FC_CFG_ERBSZ_128K (0x04ul << 2)
#define MCHP_ESPI_FC_CFG_ERBSZ_256K (0x05ul << 2)
#define MCHP_ESPI_FC_CFG_MAXPLD_POS 8u
#define MCHP_ESPI_FC_CFG_MAXPLD_MASK0 0x07ul
#define MCHP_ESPI_FC_CFG_MAXPLD_MASK (0x07ul << 8) /* RO */
#define MCHP_ESPI_FC_CFG_MAXPLD_64B (0x01ul << 8)
#define MCHP_ESPI_FC_CFG_MAXPLD_128B (0x02ul << 8)
#define MCHP_ESPI_FC_CFG_MAXPLD_256B (0x03ul << 8)
#define MCHP_ESPI_FC_CFG_SAFS_SEL_POS 11u
#define MCHP_ESPI_FC_CFG_SAFS_SEL (1ul << 11)
#define MCHP_ESPI_FC_CFG_MAXRD_POS 12u
#define MCHP_ESPI_FC_CFG_MAXRD_MASK0 0x07ul
#define MCHP_ESPI_FC_CFG_MAXRD_MASK (0x07ul << 12) /* RO */
#define MCHP_ESPI_FC_CFG_MAXRD_64B (0x01ul << 12)
#define MCHP_ESPI_FC_CFG_MAXRD_128B (0x02ul << 12)
#define MCHP_ESPI_FC_CFG_MAXRD_256B (0x03ul << 12)
#define MCHP_ESPI_FC_CFG_MAXRD_512B (0x04ul << 12)
#define MCHP_ESPI_FC_CFG_MAXRD_1K (0x05ul << 12)
#define MCHP_ESPI_FC_CFG_MAXRD_2K (0x06ul << 12)
#define MCHP_ESPI_FC_CFG_MAXRD_4K (0x07ul << 12)
#define MCHP_ESPI_FC_CFG_FORCE_MS_POS 28u
#define MCHP_ESPI_FC_CFG_FORCE_MS_MASK0 0x03ul
#define MCHP_ESPI_FC_CFG_FORCE_MS_MASK (0x03ul << 28) /* RW */
/* Host (eSPI Master) can select MAFS or SAFS */
#define MCHP_ESPI_FC_CFG_FORCE_NONE (0x00ul << 28)
/* EC forces eSPI slave HW to only allow MAFS */
#define MCHP_ESPI_FC_CFG_FORCE_MAFS (0x02ul << 28)
/* EC forces eSPI slave HW to only allow SAFS */
#define MCHP_ESPI_FC_CFG_FORCE_SAFS (0x03ul << 28)
/* STS */
#define MCHP_ESPI_FC_STS_CHAN_EN_POS 0u
#define MCHP_ESPI_FC_STS_CHAN_EN (1ul << 0) /* RO */
#define MCHP_ESPI_FC_STS_CHAN_EN_CHG_POS 1u
#define MCHP_ESPI_FC_STS_CHAN_EN_CHG (1ul << 1) /* RW1C */
#define MCHP_ESPI_FC_STS_DONE_POS 2u
#define MCHP_ESPI_FC_STS_DONE (1ul << 2) /* RW1C */
#define MCHP_ESPI_FC_STS_MDIS_POS 3u
#define MCHP_ESPI_FC_STS_MDIS (1ul << 3) /* RW1C */
#define MCHP_ESPI_FC_STS_IBERR_POS 4u
#define MCHP_ESPI_FC_STS_IBERR (1ul << 4) /* RW1C */
#define MCHP_ESPI_FC_STS_ABS_POS 5u
#define MCHP_ESPI_FC_STS_ABS (1ul << 5) /* RW1C */
#define MCHP_ESPI_FC_STS_OVRUN_POS 6u
#define MCHP_ESPI_FC_STS_OVRUN (1ul << 6) /* RW1C */
#define MCHP_ESPI_FC_STS_INC_POS 7u
#define MCHP_ESPI_FC_STS_INC (1ul << 7) /* RW1C */
#define MCHP_ESPI_FC_STS_FAIL_POS 8u
#define MCHP_ESPI_FC_STS_FAIL (1ul << 8) /* RW1C */
#define MCHP_ESPI_FC_STS_OVFL_POS 9u
#define MCHP_ESPI_FC_STS_OVFL (1ul << 9) /* RW1C */
#define MCHP_ESPI_FC_STS_BADREQ_POS 11u
#define MCHP_ESPI_FC_STS_BADREQ (1ul << 11) /* RW1C */
#define MCHP_ESPI_FC_STS_ALL_RW1C 0x0BFEul
typedef struct espi_io_fc_regs {
__IOM uint32_t FL_ADDR_LSW; /*! (@ 0x0000) FC flash address bits[31:0] */
__IOM uint32_t FL_ADDR_MSW; /*! (@ 0x0004) FC flash address bits[63:32] */
__IOM uint32_t MEM_ADDR_LSW; /*! (@ 0x0008) FC EC Memory address bits[31:0] */
__IOM uint32_t MEM_ADDR_MSW; /*! (@ 0x000C) FC EC Memory address bits[63:32] */
__IOM uint32_t XFR_LEN; /*! (@ 0x0010) FC transfer length */
__IOM uint32_t CTRL; /*! (@ 0x0014) FC Control */
__IOM uint32_t IEN; /*! (@ 0x0018) FC interrupt enable */
__IOM uint32_t CFG; /*! (@ 0x001C) FC configuration */
__IOM uint32_t STS; /*! (@ 0x0020) FC status */
} ESPI_IO_FC_Type;
/*
* MCHP_ESPI_IO_BAR_HOST - eSPI IO Host visible BAR registers @ 0x400F3520
*/
/*
* IOBAR_INH_LSW/MSW 64-bit register: each bit = 1 inhibits an I/O BAR
* independent of the BAR's Valid bit.
* Logical Device Number = bit position.
*/
#define MCHP_ESPI_IOBAR_LDN_MBOX 0x00u
#define MCHP_ESPI_IOBAR_LDN_KBC 0x01u
#define MCHP_ESPI_IOBAR_LDN_ACPI_EC_0 0x02u
#define MCHP_ESPI_IOBAR_LDN_ACPI_EC_1 0x03u
#define MCHP_ESPI_IOBAR_LDN_ACPI_EC_2 0x04u
#define MCHP_ESPI_IOBAR_LDN_ACPI_EC_3 0x05u
#define MCHP_ESPI_IOBAR_LDN_ACPI_PM1 0x07u
#define MCHP_ESPI_IOBAR_LDN_PORT92 0x08u
#define MCHP_ESPI_IOBAR_LDN_UART_0 0x09u
#define MCHP_ESPI_IOBAR_LDN_UART_1 0x0Au
#define MCHP_ESPI_IOBAR_LDN_UART_2 0x0Bu
#define MCHP_ESPI_IOBAR_LDN_IOC 0x0Du
#define MCHP_ESPI_IOBAR_LDN_MEM 0x0Eu
#define MCHP_ESPI_IOBAR_LDN_GLUE_LOG 0x0Fu
#define MCHP_ESPI_IOBAR_LDN_EMI_0 0x10u
#define MCHP_ESPI_IOBAR_LDN_EMI_1 0x11u
#define MCHP_ESPI_IOBAR_LDN_RTC 0x14u
#define MCHP_ESPI_IOBAR_LDN_P80CAP_0 0x20u
#define MCHP_ESPI_IOBAR_LDN_P80CAP_1 0x21u
#define MCHP_ESPI_IOBAR_LDN_T32B 0x2Fu
/*
* IOBAR_INIT: Default address of I/O Plug and Play Super-IO index/data
* configuration registers. (Defaults to 0x2E/0x2F)
*/
#define MCHP_ESPI_IOBAR_INIT_DFLT 0x2Eul
/*
* EC_IRQ: A write to bit[0] triggers EC SERIRQ. The actual
* SERIRQ slot is configured in MCHP_ESPI_IO_SIRQ.EC_SIRQ
*/
#define MCHP_ESPI_EC_IRQ_GEN (1ul << 0)
/*
* 32-bit Host IO BAR
*/
#define MCHP_ESPI_IO_BAR_HOST_VALID_POS 0u
#define MCHP_ESPI_IO_BAR_HOST_VALID (1ul << 0)
#define MCHP_ESPI_IO_BAR_HOST_ADDR_POS 16u
#define MCHP_ESPI_IO_BAR_HOST_ADDR_MASK0 0xFFFFul
#define MCHP_ESPI_IO_BAR_HOST_ADDR_MASK (0xFFFFul << 16)
typedef struct espi_io_bar_host_regs
{
__IOM uint32_t IOBAR_INH_LSW; /*! (@ 0x0000) BAR Inhibit LSW */
__IOM uint32_t IOBAR_INH_MSW; /*! (@ 0x0004) BAR Inhibit MSW */
__IOM uint32_t IOBAR_INIT; /*! (@ 0x0008) BAR Init */
__IOM uint32_t EC_IRQ; /*! (@ 0x000C) EC IRQ */
uint8_t RSVD1[4];
__IOM uint32_t HOST_BAR_IOC; /*! (@ 0x0014) Host IO Component BAR */
__IOM uint32_t HOST_BAR_MEM; /*! (@ 0x0018) Host IO Compoent Mem BAR */
__IOM uint32_t HOST_BAR_MBOX; /*! (@ 0x001C) Host IO Mailbox BAR */
__IOM uint32_t HOST_BAR_KBC; /*! (@ 0x0020) Host IO KBC BAR */
__IOM uint32_t HOST_BAR_ACPI_EC_0; /*! (@ 0x0024) Host IO ACPI_EC 0 BAR */
__IOM uint32_t HOST_BAR_ACPI_EC_1; /*! (@ 0x0028) Host IO ACPI_EC 1 BAR */
__IOM uint32_t HOST_BAR_ACPI_EC_2; /*! (@ 0x002C) Host IO ACPI_EC 2 BAR */
__IOM uint32_t HOST_BAR_ACPI_EC_3; /*! (@ 0x0030) Host IO ACPI_EC 3 BAR */
uint8_t RSVD2[4];
__IOM uint32_t HOST_BAR_ACPI_PM1; /*! (@ 0x0038) Host IO ACPI_PM1 BAR */
__IOM uint32_t HOST_BAR_PORT92; /*! (@ 0x003C) Host IO PORT92 BAR */
__IOM uint32_t HOST_BAR_UART_0; /*! (@ 0x0040) Host IO UART 0 BAR */
__IOM uint32_t HOST_BAR_UART_1; /*! (@ 0x0044) Host IO UART 1 BAR */
__IOM uint32_t HOST_BAR_EMI_0; /*! (@ 0x0048) Host IO EMI 0 BAR */
__IOM uint32_t HOST_BAR_EMI_1; /*! (@ 0x004C) Host IO EMI 1 BAR */
uint8_t RSVD3[4];
__IOM uint32_t HOST_BAR_P80CAP_0; /*! (@ 0x0054) Host IO Port80 Capture 0 BAR */
__IOM uint32_t HOST_BAR_P80CAP_1; /*! (@ 0x0058) Host IO Port80 Capture 1 BAR */
__IOM uint32_t HOST_BAR_RTC; /*! (@ 0x005C) Host IO RTC BAR */
uint8_t RSVD4[4];
__IOM uint32_t HOST_BAR_T32B; /*! (@ 0x0064) Host IO Test 32 byte BAR */
__IOM uint32_t HOST_BAR_UART_2; /*! (@ 0x0068) Host IO UART 2 BAR */
__IOM uint32_t HOST_BAR_GLUE_LOG; /*! (@ 0x006C) Host IO Glue Logic BAR */
} ESPI_IO_BAR_HOST_Type;
/*
* ESPI_IO_BAR_EC - eSPI IO EC-only component of IO BAR @ 0x400F3730
* All fields are Read-Only
* Address mask in bits[7:0]
* Logical device number in bits[13:8]
*/
typedef struct espi_io_bar_ec_regs
{
__IOM uint32_t IO_ACTV; /*! (@ 0x0000) ESPI IO Component Activate */
__IOM uint32_t EC_BAR_IOC; /*! (@ 0x0004) Host IO Component BAR */
__IOM uint32_t EC_BAR_MEM; /*! (@ 0x0008) Host IO Compoent Mem BAR */
__IOM uint32_t EC_BAR_MBOX; /*! (@ 0x000C) Host IO Mailbox BAR */
__IOM uint32_t EC_BAR_KBC; /*! (@ 0x0010) Host IO KBC BAR */
__IOM uint32_t EC_BAR_ACPI_EC_0; /*! (@ 0x0014) Host IO ACPI_EC 0 BAR */
__IOM uint32_t EC_BAR_ACPI_EC_1; /*! (@ 0x0018) Host IO ACPI_EC 1 BAR */
__IOM uint32_t EC_BAR_ACPI_EC_2; /*! (@ 0x001C) Host IO ACPI_EC 2 BAR */
__IOM uint32_t EC_BAR_ACPI_EC_3; /*! (@ 0x0020) Host IO ACPI_EC 3 BAR */
uint8_t RSVD2[4];
__IOM uint32_t EC_BAR_ACPI_PM1; /*! (@ 0x0028) Host IO ACPI_PM1 BAR */
__IOM uint32_t EC_BAR_PORT92; /*! (@ 0x002C) Host IO PORT92 BAR */
__IOM uint32_t EC_BAR_UART_0; /*! (@ 0x0030) Host IO UART 0 BAR */
__IOM uint32_t EC_BAR_UART_1; /*! (@ 0x0034) Host IO UART 1 BAR */
__IOM uint32_t EC_BAR_EMI_0; /*! (@ 0x0038) Host IO EMI 0 BAR */
__IOM uint32_t EC_BAR_EMI_1; /*! (@ 0x003C) Host IO EMI 1 BAR */
uint8_t RSVD3[4];
__IOM uint32_t EC_BAR_P80CAP_0; /*! (@ 0x0044) Host IO Port80 Capture 0 BAR */
__IOM uint32_t EC_BAR_P80CAP_1; /*! (@ 0x0048) Host IO Port80 Capture 1 BAR */
__IOM uint32_t EC_BAR_RTC; /*! (@ 0x004C) Host IO RTC BAR */
uint8_t RSVD4[4];
__IOM uint32_t EC_BAR_T32B; /*! (@ 0x0054) Host IO Test 32 byte BAR */
__IOM uint32_t EC_BAR_UART_2; /*! (@ 0x0058) Host IO UART 2 BAR */
__IOM uint32_t EC_BAR_GLUE_LOG; /*! (@ 0x005C) Host IO Glue Logic BAR */
} ESPI_IO_BAR_EC_Type;
/* Offsets from first SIRQ */
#define MCHP_ESPI_SIRQ_MBOX_SIRQ 0ul
#define MCHP_ESPI_SIRQ_MBOX_SMI 1ul
#define MCHP_ESPI_SIRQ_KBC_KIRQ 2ul
#define MCHP_ESPI_SIRQ_KBC_MIRQ 3ul
#define MCHP_ESPI_SIRQ_ACPI_EC0 4ul
#define MCHP_ESPI_SIRQ_ACPI_EC1 5ul
#define MCHP_ESPI_SIRQ_ACPI_EC2 6ul
#define MCHP_ESPI_SIRQ_ACPI_EC3 7ul
#define MCHP_ESPI_SIRQ_RSVD8 8ul
#define MCHP_ESPI_SIRQ_UART0 9ul
#define MCHP_ESPI_SIRQ_UART1 10ul
#define MCHP_ESPI_SIRQ_EMI0_HOST 11ul
#define MCHP_ESPI_SIRQ_EMI0_E2H 12ul
#define MCHP_ESPI_SIRQ_EMI1_HOST 13ul
#define MCHP_ESPI_SIRQ_EMI1_E2H 14ul
#define MCHP_ESPI_SIRQ_RSVD15 15ul
#define MCHP_ESPI_SIRQ_RSVD16 16ul
#define MCHP_ESPI_SIRQ_RTC 17ul
#define MCHP_ESPI_SIRQ_EC 18ul
#define MCHP_ESPI_SIRQ_UART2 19ul
#define MCHP_ESPI_SIRQ_MAX 20ul
/*
* MCHP_ESPI_IO_SIRQ - eSPI IO Component Logical Device Serial IRQ configuration
* @ 0x400F37A0
*/
/*
* Values for Logical Device SIRQ registers.
* Unless disabled each logical device must have a unique value
* programmed to its SIRQ register.
* Values 0x00u through 0x7Fu are sent using VWire host index 0x00
* Values 0x80h through 0xFEh are sent using VWire host index 0x01
* All registers reset default is 0xFFu (disabled).
*/
#define MCHP_ESPI_IO_SIRQ_DIS 0xFFu
typedef struct espi_io_sirq_regs
{
uint8_t RSVD1[12];
__IOM uint8_t MBOX_SIRQ_0; /*! (@ 0x000C) Mailbox SIRQ 0 config */
__IOM uint8_t MBOX_SIRQ_1; /*! (@ 0x000D) Mailbox SIRQ 1 config */
__IOM uint8_t KBC_SIRQ_0; /*! (@ 0x000E) KBC SIRQ 0 config */
__IOM uint8_t KBC_SIRQ_1; /*! (@ 0x000F) KBC SIRQ 1 config */
__IOM uint8_t ACPI_EC_0_SIRQ; /*! (@ 0x0010) ACPI EC 0 SIRQ config */
__IOM uint8_t ACPI_EC_1_SIRQ; /*! (@ 0x0011) ACPI EC 1 SIRQ config */
__IOM uint8_t ACPI_EC_2_SIRQ; /*! (@ 0x0012) ACPI EC 2 SIRQ config */
__IOM uint8_t ACPI_EC_3_SIRQ; /*! (@ 0x0013) ACPI EC 3 SIRQ config */
uint8_t RSVD2[1];
__IOM uint8_t UART_0_SIRQ; /*! (@ 0x0015) UART 0 SIRQ config */
__IOM uint8_t UART_1_SIRQ; /*! (@ 0x0016) UART 1 SIRQ config */
__IOM uint8_t EMI_0_SIRQ_0; /*! (@ 0x0017) EMI 0 SIRQ 0 config */
__IOM uint8_t EMI_0_SIRQ_1; /*! (@ 0x0018) EMI 0 SIRQ 1 config */
__IOM uint8_t EMI_1_SIRQ_0; /*! (@ 0x0019) EMI 1 SIRQ 0 config */
__IOM uint8_t EMI_1_SIRQ_1; /*! (@ 0x001A) EMI 1 SIRQ 1 config */
uint8_t RSVD3[2];
__IOM uint8_t RTC_SIRQ; /*! (@ 0x001D) RTC SIRQ config */
__IOM uint8_t EC_SIRQ; /*! (@ 0x001E) EC SIRQ config */
__IOM uint8_t UART_2_SIRQ; /*! (@ 0x001F) UART 2 SIRQ config */
} ESPI_IO_SIRQ_Type;
#endif /* #ifndef _ESPI_IO_H */
/* end espi_io.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file espi_mem.h
*MEC1501 eSPI Memory Component definitions
*/
/** @defgroup MEC1501 Peripherals eSPI MEM
*/
#ifndef _ESPI_MEM_H
#define _ESPI_MEM_H
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
/*------------------------------------------------------------------*/
/* =========================================================================*/
/* ================ eSPI Memory Component ================ */
/* =========================================================================*/
/*
* eSPI Memory Component Bus Master registers @ 0x400F3A00
*/
/* BM_STS */
#define MCHP_ESPI_BM_STS_DONE_1_POS 0u
#define MCHP_ESPI_BM_STS_DONE_1 (1ul << 0) /* RW1C */
#define MCHP_ESPI_BM_STS_BUSY_1_POS 1u
#define MCHP_ESPI_BM_STS_BUSY_1 (1ul << 1) /* RO */
#define MCHP_ESPI_BM_STS_AB_EC_1_POS 2u
#define MCHP_ESPI_BM_STS_AB_EC_1 (1ul << 2) /* RW1C */
#define MCHP_ESPI_BM_STS_AB_HOST_1_POS 3u
#define MCHP_ESPI_BM_STS_AB_HOST_1 (1ul << 3) /* RW1C */
#define MCHP_ESPI_BM_STS_AB_CH2_1_POS 4u
#define MCHP_ESPI_BM_STS_CH2_AB_1 (1ul << 4) /* RW1C */
#define MCHP_ESPI_BM_STS_OVFL_1_POS 5u
#define MCHP_ESPI_BM_STS_OVFL_1_CH2 (1ul << 5) /* RW1C */
#define MCHP_ESPI_BM_STS_OVRUN_1_POS 6u
#define MCHP_ESPI_BM_STS_OVRUN_1_CH2 (1ul << 6) /* RW1C */
#define MCHP_ESPI_BM_STS_INC_1_POS 7u
#define MCHP_ESPI_BM_STS_INC_1 (1ul << 7) /* RW1C */
#define MCHP_ESPI_BM_STS_FAIL_1_POS 8u
#define MCHP_ESPI_BM_STS_FAIL_1 (1ul << 8) /* RW1C */
#define MCHP_ESPI_BM_STS_IBERR_1_POS 9u
#define MCHP_ESPI_BM_STS_IBERR_1 (1ul << 9) /* RW1C */
#define MCHP_ESPI_BM_STS_BADREQ_1_POS 11u
#define MCHP_ESPI_BM_STS_BADREQ_1 (1ul << 11) /* RW1C */
#define MCHP_ESPI_BM_STS_DONE_2_POS 16u
#define MCHP_ESPI_BM_STS_DONE_2 (1ul << 16) /* RW1C */
#define MCHP_ESPI_BM_STS_BUSY_2_POS 17u
#define MCHP_ESPI_BM_STS_BUSY_2 (1ul << 17) /* RO */
#define MCHP_ESPI_BM_STS_AB_EC_2_POS 18u
#define MCHP_ESPI_BM_STS_AB_EC_2 (1ul << 18) /* RW1C */
#define MCHP_ESPI_BM_STS_AB_HOST_2_POS 19u
#define MCHP_ESPI_BM_STS_AB_HOST_2 (1ul << 19) /* RW1C */
#define MCHP_ESPI_BM_STS_AB_CH1_2_POS 20u
#define MCHP_ESPI_BM_STS_AB_CH1_2 (1ul << 20) /* RW1C */
#define MCHP_ESPI_BM_STS_OVFL_2_POS 21u
#define MCHP_ESPI_BM_STS_OVFL_2_CH2 (1ul << 21) /* RW1C */
#define MCHP_ESPI_BM_STS_OVRUN_2_POS 22u
#define MCHP_ESPI_BM_STS_OVRUN_CH2_2 (1ul << 22) /* RW1C */
#define MCHP_ESPI_BM_STS_INC_2_POS 23u
#define MCHP_ESPI_BM_STS_INC_2 (1ul << 23) /* RW1C */
#define MCHP_ESPI_BM_STS_FAIL_2_POS 24u
#define MCHP_ESPI_BM_STS_FAIL_2 (1ul << 24) /* RW1C */
#define MCHP_ESPI_BM_STS_IBERR_2_POS 25u
#define MCHP_ESPI_BM_STS_IBERR_2 (1ul << 25) /* RW1C */
#define MCHP_ESPI_BM_STS_BADREQ_2_POS 27u
#define MCHP_ESPI_BM_STS_BADREQ_2 (1ul << 27) /* RW1C */
#define MCHP_ESPI_BM_STS_ALL_RW1C_1 0x0BFDul
#define MCHP_ESPI_BM_STS_ALL_RW1C_2 (0x0BFDul << 16)
/* BM_IEN */
#define MCHP_ESPI_BM1_IEN_DONE_POS 0u
#define MCHP_ESPI_BM1_IEN_DONE (1ul << 0)
#define MCHP_ESPI_BM2_IEN_DONE_POS 16u
#define MCHP_ESPI_BM2_IEN_DONE (1ul << 16)
/* BM_CFG */
#define MCHP_ESPI_BM1_CFG_TAG_POS 0u
#define MCHP_ESPI_BM1_CFG_TAG_MASK0 0x0Ful
#define MCHP_ESPI_BM1_CFG_TAG_MASK (0x0Ful << 0)
#define MCHP_ESPI_BM2_CFG_TAG_POS 16u
#define MCHP_ESPI_BM2_CFG_TAG_MASK0 0x0Ful
#define MCHP_ESPI_BM2_CFG_TAG_MASK (0x0Ful << 16)
/* BM1_CTRL */
#define MCHP_ESPI_BM1_CTRL_START_POS 0u
#define MCHP_ESPI_BM1_CTRL_START (1ul << 0) /* WO */
#define MCHP_ESPI_BM1_CTRL_ABORT_POS 1u
#define MCHP_ESPI_BM1_CTRL_ABORT (1ul << 1) /* WO */
#define MCHP_ESPI_BM1_CTRL_EN_INC_POS 2u
#define MCHP_ESPI_BM1_CTRL_EN_INC (1ul << 2) /* RW */
#define MCHP_ESPI_BM1_CTRL_WAIT_NB2_POS 3u
#define MCHP_ESPI_BM1_CTRL_WAIT_NB2 (1ul << 3) /* RW */
#define MCHP_ESPI_BM1_CTRL_CTYPE_POS 8u
#define MCHP_ESPI_BM1_CTRL_CTYPE_MASK0 0x03ul
#define MCHP_ESPI_BM1_CTRL_CTYPE_MASK (0x03ul << 8)
#define MCHP_ESPI_BM1_CTRL_CTYPE_RD_ADDR32 (0x00ul << 8)
#define MCHP_ESPI_BM1_CTRL_CTYPE_WR_ADDR32 (0x01ul << 8)
#define MCHP_ESPI_BM1_CTRL_CTYPE_RD_ADDR64 (0x02ul << 8)
#define MCHP_ESPI_BM1_CTRL_CTYPE_WR_ADDR64 (0x03ul << 8)
#define MCHP_ESPI_BM1_CTRL_LEN_POS 16u
#define MCHP_ESPI_BM1_CTRL_LEN_MASK0 0x1FFFul
#define MCHP_ESPI_BM1_CTRL_LEN_MASK (0x1FFFul << 16)
/* BM1_EC_ADDR_LSW */
#define MCHP_ESPI_BM1_EC_ADDR_LSW_MASK 0xFFFFFFFCul
/* BM2_CTRL */
#define MCHP_ESPI_BM2_CTRL_START_POS 0u
#define MCHP_ESPI_BM2_CTRL_START (1ul << 0) /* WO */
#define MCHP_ESPI_BM2_CTRL_ABORT_POS 1u
#define MCHP_ESPI_BM2_CTRL_ABORT (1ul << 1) /* WO */
#define MCHP_ESPI_BM2_CTRL_EN_INC_POS 2u
#define MCHP_ESPI_BM2_CTRL_EN_INC (1ul << 2) /* RW */
#define MCHP_ESPI_BM2_CTRL_WAIT_NB2_POS 3u
#define MCHP_ESPI_BM2_CTRL_WAIT_NB2 (1ul << 3) /* RW */
#define MCHP_ESPI_BM2_CTRL_CTYPE_POS 8u
#define MCHP_ESPI_BM2_CTRL_CTYPE_MASK0 0x03ul
#define MCHP_ESPI_BM2_CTRL_CTYPE_MASK (0x03ul << 8)
#define MCHP_ESPI_BM2_CTRL_CTYPE_RD_ADDR32 (0x00ul << 8)
#define MCHP_ESPI_BM2_CTRL_CTYPE_WR_ADDR32 (0x01ul << 8)
#define MCHP_ESPI_BM2_CTRL_CTYPE_RD_ADDR64 (0x02ul << 8)
#define MCHP_ESPI_BM2_CTRL_CTYPE_WR_ADDR64 (0x03ul << 8)
#define MCHP_ESPI_BM2_CTRL_LEN_POS 16u
#define MCHP_ESPI_BM2_CTRL_LEN_MASK0 0x1FFFul
#define MCHP_ESPI_BM2_CTRL_LEN_MASK (0x1FFFul << 16)
/* BM2_EC_ADDR_LSW */
#define MCHP_ESPI_BM2_EC_ADDR_LSW_MASK 0xFFFFFFFCul
typedef struct espi_mem_bm_regs
{
__IOM uint32_t BM_STS; /*! (@ 0x0000) Bus Master Status */
__IOM uint32_t BM_IEN; /*! (@ 0x0004) Bus Master interrupt enable */
__IOM uint32_t BM_CFG; /*! (@ 0x0008) Bus Master configuration */
uint8_t RSVD1[4];
__IOM uint32_t BM1_CTRL; /*! (@ 0x0010) Bus Master 1 control */
__IOM uint32_t BM1_HOST_ADDR_LSW; /*! (@ 0x0014) Bus Master 1 host address bits[31:0] */
__IOM uint32_t BM1_HOST_ADDR_MSW; /*! (@ 0x0018) Bus Master 1 host address bits[63:32] */
__IOM uint32_t BM1_EC_ADDR_LSW; /*! (@ 0x001C) Bus Master 1 EC address bits[31:0] */
__IOM uint32_t BM1_EC_ADDR_MSW; /*! (@ 0x0020) Bus Master 1 EC address bits[63:32] */
__IOM uint32_t BM2_CTRL; /*! (@ 0x0024) Bus Master 2 control */
__IOM uint32_t BM2_HOST_ADDR_LSW; /*! (@ 0x0028) Bus Master 2 host address bits[31:0] */
__IOM uint32_t BM2_HOST_ADDR_MSW; /*! (@ 0x002C) Bus Master 2 host address bits[63:32] */
__IOM uint32_t BM2_EC_ADDR_LSW; /*! (@ 0x0030) Bus Master 2 EC address bits[31:0] */
__IOM uint32_t BM2_EC_ADDR_MSW; /*! (@ 0x0034) Bus Master 2 EC address bits[63:32] */
} ESPI_MEM_BM_Type;
/*
* MCHP_ESPI_MEM_BAR_EC @ 0x400F3930
*
* Half-word H0 of each EC Memory BAR contains
* Memory BAR memory address mask bits in bits[7:0]
* Logical Device Number in bits[13:8]
*/
#define MCHP_ESPI_EBAR_H0_MEM_MASK_POS 0u
#define MCHP_ESPI_EBAR_H0_MEM_MASK_MASK 0xFFul
#define MCHP_ESPI_EBAR_H0_LDN_POS 8u
#define MCHP_ESPI_EBAR_H0_LDN_MASK0 0x3Ful
#define MCHP_ESPI_EBAR_H0_LDN_MASK (0x3Ful << 8u)
typedef struct espi_mem_bar_ec_regs
{
__IOM uint16_t EBAR_MBX_H0; /*! (@ 0x0000) Mailbox Logical Device BAR Internal b[15:0] */
__IOM uint16_t EBAR_MBX_H1; /*! (@ 0x0002) Mailbox Logical Device BAR Internal b[31:16] */
__IOM uint16_t EBAR_MBX_H2; /*! (@ 0x0004) Mailbox Logical Device BAR Internal b[47:32] */
__IOM uint16_t EBAR_MBX_H3; /*! (@ 0x0006) Mailbox Logical Device BAR Internal b[63:48] */
__IOM uint16_t EBAR_MBX_H4; /*! (@ 0x0008) Mailbox Logical Device BAR Internal b[79:64] */
__IOM uint16_t EBAR_ACPI_EC_0_H0; /*! (@ 0x000A) ACPI EC0 Logical Device BAR Internal b[15:0] */
__IOM uint16_t EBAR_ACPI_EC_0_H1; /*! (@ 0x000C) ACPI EC0 Logical Device BAR Internal b[31:16] */
__IOM uint16_t EBAR_ACPI_EC_0_H2; /*! (@ 0x000E) ACPI EC0 Logical Device BAR Internal b[47:32] */
__IOM uint16_t EBAR_ACPI_EC_0_H3; /*! (@ 0x0010) ACPI EC0 Logical Device BAR Internal b[63:48] */
__IOM uint16_t EBAR_ACPI_EC_0_H4; /*! (@ 0x0012) ACPI EC0 Logical Device BAR Internal b[79:64] */
__IOM uint16_t EBAR_ACPI_EC_1_H0; /*! (@ 0x0014) ACPI EC1 Logical Device BAR Internal b[15:0] */
__IOM uint16_t EBAR_ACPI_EC_1_H1; /*! (@ 0x0016) ACPI EC1 Logical Device BAR Internal b[31:16] */
__IOM uint16_t EBAR_ACPI_EC_1_H2; /*! (@ 0x0018) ACPI EC1 Logical Device BAR Internal b[47:32] */
__IOM uint16_t EBAR_ACPI_EC_1_H3; /*! (@ 0x001A) ACPI EC1 Logical Device BAR Internal b[63:48] */
__IOM uint16_t EBAR_ACPI_EC_1_H4; /*! (@ 0x001C) ACPI EC1 Logical Device BAR Internal b[79:64] */
__IOM uint16_t EBAR_ACPI_EC_2_H0; /*! (@ 0x001E) ACPI EC2 Logical Device BAR Internal b[15:0] */
__IOM uint16_t EBAR_ACPI_EC_2_H1; /*! (@ 0x0020) ACPI EC2 Logical Device BAR Internal b[31:16] */
__IOM uint16_t EBAR_ACPI_EC_2_H2; /*! (@ 0x0022) ACPI EC2 Logical Device BAR Internal b[47:32] */
__IOM uint16_t EBAR_ACPI_EC_2_H3; /*! (@ 0x0024) ACPI EC2 Logical Device BAR Internal b[63:48] */
__IOM uint16_t EBAR_ACPI_EC_2_H4; /*! (@ 0x0026) ACPI EC2 Logical Device BAR Internal b[79:64] */
__IOM uint16_t EBAR_ACPI_EC_3_H0; /*! (@ 0x0028) ACPI EC3 Logical Device BAR Internal b[15:0] */
__IOM uint16_t EBAR_ACPI_EC_3_H1; /*! (@ 0x002A) ACPI EC3 Logical Device BAR Internal b[31:16] */
__IOM uint16_t EBAR_ACPI_EC_3_H2; /*! (@ 0x002C) ACPI EC3 Logical Device BAR Internal b[47:32] */
__IOM uint16_t EBAR_ACPI_EC_3_H3; /*! (@ 0x002E) ACPI EC3 Logical Device BAR Internal b[63:48] */
__IOM uint16_t EBAR_ACPI_EC_3_H4; /*! (@ 0x0030) ACPI EC3 Logical Device BAR Internal b[79:64] */
uint8_t RSVD1[10];
__IOM uint16_t EBAR_EMI_0_H0; /*! (@ 0x003C) EMI0 Logical Device BAR Internal b[15:0] */
__IOM uint16_t EBAR_EMI_0_H1; /*! (@ 0x003E) EMI0 Logical Device BAR Internal b[31:16] */
__IOM uint16_t EBAR_EMI_0_H2; /*! (@ 0x0040) EMI0 Logical Device BAR Internal b[47:32] */
__IOM uint16_t EBAR_EMI_0_H3; /*! (@ 0x0042) EMI0 Logical Device BAR Internal b[63:48] */
__IOM uint16_t EBAR_EMI_0_H4; /*! (@ 0x0044) EMI0 Logical Device BAR Internal b[79:64] */
__IOM uint16_t EBAR_EMI_1_H0; /*! (@ 0x0046) EMI1 Logical Device BAR Internal b[15:0] */
__IOM uint16_t EBAR_EMI_1_H1; /*! (@ 0x0048) EMI1 Logical Device BAR Internal b[31:16] */
__IOM uint16_t EBAR_EMI_1_H2; /*! (@ 0x004A) EMI1 Logical Device BAR Internal b[47:32] */
__IOM uint16_t EBAR_EMI_1_H3; /*! (@ 0x004C) EMI1 Logical Device BAR Internal b[63:48] */
__IOM uint16_t EBAR_EMI_1_H4; /*! (@ 0x004E) EMI1 Logical Device BAR Internal b[79:64] */
} ESPI_MEM_BAR_EC_Type;
/*
* MCHP_ESPI_MEM_BAR_HOST @ 0x400F3B30
*
* Each Host BAR contains:
* bit[0] (RW) = Valid bit
* bits[15:1] = Reserved, read-only 0
* bits[47:16] (RW) = bits[31:0] of the Host Memory address.
*/
/* Memory BAR Host address valid */
#define MCHP_ESPI_HBAR_VALID_POS 0u
#define MCHP_ESPI_HBAR_VALID_MASK 0x01ul
/*
* Host address is in bits[47:16] of the HBAR
* HBAR's are spaced every 10 bytes (80 bits) but
* only implement bits[47:0]
*/
#define MCHP_ESPI_HBAR_VALID_OFS 0x00u /* byte 0 */
/* 32-bit Host Address */
#define MCHP_ESPI_HBAR_ADDR_B0_OFS 0x02u /* byte 2 */
#define MCHP_ESPI_HBAR_ADDR_B1_OFS 0x03u /* byte 3 */
#define MCHP_ESPI_HBAR_ADDR_B2_OFS 0x04u /* byte 4 */
#define MCHP_ESPI_HBAR_ADDR_B3_OFS 0x05u /* byte 5 */
typedef struct espi_mem_bar_host_regs
{
__IOM uint16_t HBAR_MBX_H0; /*! (@ 0x0000) Mailbox Logical Device BAR Host b[15:0] */
__IOM uint16_t HBAR_MBX_H1; /*! (@ 0x0002) Mailbox Logical Device BAR Host b[31:16] */
__IOM uint16_t HBAR_MBX_H2; /*! (@ 0x0004) Mailbox Logical Device BAR Host b[47:32] */
__IOM uint16_t HBAR_MBX_H3; /*! (@ 0x0006) Mailbox Logical Device BAR Host b[63:48] */
__IOM uint16_t HBAR_MBX_H4; /*! (@ 0x0008) Mailbox Logical Device BAR Host b[79:64] */
__IOM uint16_t HBAR_ACPI_EC_0_H0; /*! (@ 0x000A) ACPI EC0 Logical Device BAR Host b[15:0] */
__IOM uint16_t HBAR_ACPI_EC_0_H1; /*! (@ 0x000C) ACPI EC0 Logical Device BAR Host b[31:16] */
__IOM uint16_t HBAR_ACPI_EC_0_H2; /*! (@ 0x000E) ACPI EC0 Logical Device BAR Host b[47:32] */
__IOM uint16_t HBAR_ACPI_EC_0_H3; /*! (@ 0x0010) ACPI EC0 Logical Device BAR Host b[63:48] */
__IOM uint16_t HBAR_ACPI_EC_0_H4; /*! (@ 0x0012) ACPI EC0 Logical Device BAR Host b[79:64] */
__IOM uint16_t HBAR_ACPI_EC_1_H0; /*! (@ 0x0014) ACPI EC1 Logical Device BAR Host b[15:0] */
__IOM uint16_t HBAR_ACPI_EC_1_H1; /*! (@ 0x0016) ACPI EC1 Logical Device BAR Host b[31:16] */
__IOM uint16_t HBAR_ACPI_EC_1_H2; /*! (@ 0x0018) ACPI EC1 Logical Device BAR Host b[47:32] */
__IOM uint16_t HBAR_ACPI_EC_1_H3; /*! (@ 0x001A) ACPI EC1 Logical Device BAR Host b[63:48] */
__IOM uint16_t HBAR_ACPI_EC_1_H4; /*! (@ 0x001C) ACPI EC1 Logical Device BAR Host b[79:64] */
__IOM uint16_t HBAR_ACPI_EC_2_H0; /*! (@ 0x001E) ACPI EC2 Logical Device BAR Host b[15:0] */
__IOM uint16_t HBAR_ACPI_EC_2_H1; /*! (@ 0x0020) ACPI EC2 Logical Device BAR Host b[31:16] */
__IOM uint16_t HBAR_ACPI_EC_2_H2; /*! (@ 0x0022) ACPI EC2 Logical Device BAR Host b[47:32] */
__IOM uint16_t HBAR_ACPI_EC_2_H3; /*! (@ 0x0024) ACPI EC2 Logical Device BAR Host b[63:48] */
__IOM uint16_t HBAR_ACPI_EC_2_H4; /*! (@ 0x0026) ACPI EC2 Logical Device BAR Host b[79:64] */
__IOM uint16_t HBAR_ACPI_EC_3_H0; /*! (@ 0x0028) ACPI EC3 Logical Device BAR Host b[15:0] */
__IOM uint16_t HBAR_ACPI_EC_3_H1; /*! (@ 0x002A) ACPI EC3 Logical Device BAR Host b[31:16] */
__IOM uint16_t HBAR_ACPI_EC_3_H2; /*! (@ 0x002C) ACPI EC3 Logical Device BAR Host b[47:32] */
__IOM uint16_t HBAR_ACPI_EC_3_H3; /*! (@ 0x002E) ACPI EC3 Logical Device BAR Host b[63:48] */
__IOM uint16_t HBAR_ACPI_EC_3_H4; /*! (@ 0x0030) ACPI EC3 Logical Device BAR Host b[79:64] */
uint8_t RSVD1[10];
__IOM uint16_t HBAR_EMI_0_H0; /*! (@ 0x003C) EMI0 Logical Device BAR Internal b[15:0] */
__IOM uint16_t HBAR_EMI_0_H1; /*! (@ 0x003E) EMI0 Logical Device BAR Internal b[31:16] */
__IOM uint16_t HBAR_EMI_0_H2; /*! (@ 0x0040) EMI0 Logical Device BAR Internal b[47:32] */
__IOM uint16_t HBAR_EMI_0_H3; /*! (@ 0x0042) EMI0 Logical Device BAR Internal b[63:48] */
__IOM uint16_t HBAR_EMI_0_H4; /*! (@ 0x0044) EMI0 Logical Device BAR Internal b[79:64] */
__IOM uint16_t HBAR_EMI_1_H0; /*! (@ 0x0046) EMI1 Logical Device BAR Internal b[15:0] */
__IOM uint16_t HBAR_EMI_1_H1; /*! (@ 0x0048) EMI1 Logical Device BAR Internal b[31:16] */
__IOM uint16_t HBAR_EMI_1_H2; /*! (@ 0x004A) EMI1 Logical Device BAR Internal b[47:32] */
__IOM uint16_t HBAR_EMI_1_H3; /*! (@ 0x004C) EMI1 Logical Device BAR Internal b[63:48] */
__IOM uint16_t HBAR_EMI_1_H4; /*! (@ 0x004E) EMI1 Logical Device BAR Internal b[79:64] */
} ESPI_MEM_BAR_HOST_Type;
/*
* eSPI Memory Component SRAM 0 and 1 EC BAR's @ 0x400F39A0
* bit[0] = Valid
* bits[2:1] = Access
* bit[3] = reserved, read-only 0
* bits[7:4] = Size as power of 2
* bits[15:8] = reserved, read-only 0
* bits[47:16] = Base address of EC SRAM mapped to this BAR must be
* aligned on Size boundary.
*/
#define MCHP_EC_SRAM_BAR_H0_VALID_POS 0u
#define MCHP_EC_SRAM_BAR_H0_VALID_MASK0 0x01ul
#define MCHP_EC_SRAM_BAR_H0_VALID_MASK 0x01ul
#define MCHP_EC_SRAM_BAR_H0_VALID 0x01ul
#define MCHP_EC_SRAM_BAR_H0_ACCESS_POS 1u
#define MCHP_EC_SRAM_BAR_H0_ACCESS_MASK0 0x03ul
#define MCHP_EC_SRAM_BAR_H0_ACCESS_MASK (0x03ul << 1u)
#define MCHP_EC_SRAM_BAR_H0_ACCESS_NONE (0x00ul << 1u)
#define MCHP_EC_SRAM_BAR_H0_ACCESS_RO (0x01ul << 1u)
#define MCHP_EC_SRAM_BAR_H0_ACCESS_WO (0x02ul << 1u)
#define MCHP_EC_SRAM_BAR_H0_ACCESS_RW (0x03ul << 1u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_POS 4u
#define MCHP_EC_SRAM_BAR_H0_SIZE_MASK0 0x0Ful
#define MCHP_EC_SRAM_BAR_H0_SIZE_MASK (0x0Ful << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_1B (0x00ul << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_2B (0x01ul << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_4B (0x02ul << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_8B (0x03ul << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_16B (0x04ul << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_32B (0x05ul << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_64B (0x06ul << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_128B (0x07ul << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_256B (0x08ul << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_512B (0x09ul << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_1KB (0x0Aul << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_2KB (0x0Bul << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_4KB (0x0Cul << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_8KB (0x0Dul << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_16KB (0x0Eul << 4u)
#define MCHP_EC_SRAM_BAR_H0_SIZE_32KB (0x0Ful << 4u)
/* EC and Host SRAM BAR start offset of EC or Host memory address */
#define MCHP_EC_SRAM_BAR_MADDR_OFS1 2ul
#define MCHP_EC_SRAM_BAR_MADDR_OFS2 4ul
typedef struct espi_mem_sram_bar_ec_regs {
uint8_t RSVD1[12];
__IOM uint16_t EC_SRAM_0_H0; /*! (@ 0x000C) SRAM0 BAR Internal b[15:0] */
__IOM uint16_t EC_SRAM_0_H1; /*! (@ 0x000E) SRAM0 BAR Internal b[31:16] */
__IOM uint16_t EC_SRAM_0_H2; /*! (@ 0x0010) SRAM0 BAR Internal b[47:32] */
__IOM uint16_t EC_SRAM_0_H3; /*! (@ 0x0012) SRAM0 BAR Internal b[63:48] */
__IOM uint16_t EC_SRAM_0_H4; /*! (@ 0x0014) SRAM0 BAR Internal b[79:64] */
__IOM uint16_t EC_SRAM_1_H0; /*! (@ 0x0016) SRAM1 BAR Internal b[15:0] */
__IOM uint16_t EC_SRAM_1_H1; /*! (@ 0x0018) SRAM1 BAR Internal b[31:16] */
__IOM uint16_t EC_SRAM_1_H2; /*! (@ 0x001A) SRAM1 BAR Internal b[47:32] */
__IOM uint16_t EC_SRAM_1_H3; /*! (@ 0x001C) SRAM1 BAR Internal b[63:48] */
__IOM uint16_t EC_SRAM_1_H4; /*! (@ 0x001E) SRAM1 BAR Internal b[79:64] */
} ESPI_MEM_SRAM_BAR_EC_Type;
/*
* eSPI Memory Component SRAM 0 and 1 Host BAR's @ 0x400F3BA0
* bit[0] = Read-Only copy of EC BAR Valid bit
* bits[2:1] = Read-Only copy of EC BAR Access field
* bit[3] = reserved, read-only 0
* bits[7:4] = Read-Only copy of EC Size field
* bits[15:8] = reserved, read-only 0
* bits[47:16] = R/W. Base address in Host memory space for this BAR.
*/
typedef struct espi_mem_sram_bar_host_regs {
uint8_t RSVD1[12];
__IOM uint16_t HOST_SRAM_0_H0; /*! (@ 0x03AC) SRAM0 BAR Host b[15:0] */
__IOM uint16_t HOST_SRAM_0_H1; /*! (@ 0x03AE) SRAM0 BAR Host b[31:16] */
__IOM uint16_t HOST_SRAM_0_H2; /*! (@ 0x03B0) SRAM0 BAR Host b[47:32] */
__IOM uint16_t HOST_SRAM_0_H3; /*! (@ 0x03B2) SRAM0 BAR Host b[63:48] */
__IOM uint16_t HOST_SRAM_0_H4; /*! (@ 0x03B4) SRAM0 BAR Host b[79:64] */
__IOM uint16_t HOST_SRAM_1_H0; /*! (@ 0x03B6) SRAM1 BAR Host b[15:0] */
__IOM uint16_t HOST_SRAM_1_H1; /*! (@ 0x03B8) SRAM1 BAR Host b[31:16] */
__IOM uint16_t HOST_SRAM_1_H2; /*! (@ 0x03BA) SRAM1 BAR Host b[47:32] */
__IOM uint16_t HOST_SRAM_1_H3; /*! (@ 0x03BC) SRAM1 BAR Host b[63:48] */
__IOM uint16_t HOST_SRAM_1_H4; /*! (@ 0x03BE) SRAM1 BAR Host b[79:64] */
} ESPI_MEM_SRAM_BAR_HOST;
enum mec_espi_sram_bar_size {
MCHP_ESPI_SRAM_SZ_1B = 0,
MCHP_ESPI_SRAM_SZ_2B,
MCHP_ESPI_SRAM_SZ_4B,
MCHP_ESPI_SRAM_SZ_8B,
MCHP_ESPI_SRAM_SZ_16B,
MCHP_ESPI_SRAM_SZ_32B,
MCHP_ESPI_SRAM_SZ_64B,
MCHP_ESPI_SRAM_SZ_128B,
MCHP_ESPI_SRAM_SZ_256B,
MCHP_ESPI_SRAM_SZ_512B,
MCHP_ESPI_SRAM_SZ_1KB,
MCHP_ESPI_SRAM_SZ_2KB,
MCHP_ESPI_SRAM_SZ_4KB,
MCHP_ESPI_SRAM_SZ_8KB,
MCHP_ESPI_SRAM_SZ_16KB,
MCHP_ESPI_SRAM_SZ_32KB
};
enum mec_espi_sram_bar_access {
MCHP_ESPI_SRAM_ACCESS_NONE = 0,
MCHP_ESPI_SRAM_ACCESS_RO,
MCHP_ESPI_SRAM_ACCESS_WO,
MCHP_ESPI_SRAM_ACCESS_RW
};
enum mec_espi_sram_bar_valid {
MCHP_ESPI_SRAM_BAR_NOT_VALID = 0,
MCHP_ESPI_SRAM_BAR_VALID
};
static __attribute__ ((always_inline)) inline uint32_t
mchp_espi_sram_bar_valid_get(uintptr_t bar_addr)
{
return (REG16(bar_addr) >> MCHP_EC_SRAM_BAR_H0_VALID_POS)
& MCHP_EC_SRAM_BAR_H0_VALID_MASK0;
}
static __attribute__ ((always_inline)) inline void
mchp_espi_sram_bar_valid_set(uintptr_t bar_addr,
enum mec_espi_sram_bar_valid valid)
{
REG16(bar_addr) =
(REG16(bar_addr) & ~(MCHP_EC_SRAM_BAR_H0_VALID_MASK))
| (((uint32_t) valid << MCHP_EC_SRAM_BAR_H0_VALID_POS)
& MCHP_EC_SRAM_BAR_H0_VALID_MASK);
}
static __attribute__ ((always_inline)) inline uint32_t
mchp_espi_sram_bar_access_get(uintptr_t bar_addr)
{
return (REG16(bar_addr) >> MCHP_EC_SRAM_BAR_H0_ACCESS_POS)
& MCHP_EC_SRAM_BAR_H0_ACCESS_MASK0;
}
static __attribute__ ((always_inline)) inline void
mchp_espi_sram_bar_access_set(uintptr_t bar_addr, enum mec_espi_sram_bar_size sz)
{
REG16(bar_addr) =
(REG16(bar_addr) & ~(MCHP_EC_SRAM_BAR_H0_ACCESS_MASK))
| (((uint32_t) sz << MCHP_EC_SRAM_BAR_H0_ACCESS_POS)
& MCHP_EC_SRAM_BAR_H0_ACCESS_MASK);
}
static __attribute__ ((always_inline)) inline uint32_t
mchp_espi_sram_bar_size_get(uintptr_t bar_addr)
{
return (REG16(bar_addr) >> MCHP_EC_SRAM_BAR_H0_SIZE_POS)
& MCHP_EC_SRAM_BAR_H0_SIZE_MASK0;
}
static __attribute__ ((always_inline)) inline void
mchp_espi_sram_bar_size_set(uintptr_t bar_addr, enum mec_espi_sram_bar_size sz)
{
REG16(bar_addr) =
(REG16(bar_addr) & ~(MCHP_EC_SRAM_BAR_H0_SIZE_MASK))
| (((uint32_t) sz << MCHP_EC_SRAM_BAR_H0_SIZE_POS)
& MCHP_EC_SRAM_BAR_H0_SIZE_MASK);
}
/*
* 32-bit EC or Host memory space address is in bits[47:16] of BAR
*/
static __attribute__ ((always_inline)) inline uint32_t
mchp_espi_sram_bar_maddr_get(uintptr_t bar_addr)
{
uint32_t maddr;
maddr = (uint32_t) REG16(bar_addr + 4ul);
maddr <<= 16u;
maddr += (uint32_t) REG16(bar_addr + 2ul);
return maddr;
}
static __attribute__ ((always_inline)) inline void
mchp_espi_sram_bar_maddr_set(uintptr_t bar_addr, uint32_t maddr)
{
REG16(bar_addr + 2ul) = (uint16_t) maddr;
REG16(bar_addr + 4ul) = (uint16_t) (maddr >> 16u);
}
#endif /* #ifndef _ESPI_MEM_H */
/* end espi_mem.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file espi_vw.h
*MEC1501 eSPI Virtual Wire definitions
*/
/** @defgroup MEC1501 Peripherals eSPI VW
*/
#include <stdint.h>
#include <stddef.h>
#ifndef _ESPI_VW_H
#define _ESPI_VW_H
/*------------------------------------------------------------------*/
/* Master to Slave VW register: 96-bit (3 32 bit registers) */
/* 32-bit word 0 (bits[31:0]) */
#define ESPI_M2SW0_OFS 0ul
#define ESPI_M2SW0_IDX_POS 0
#define ESPI_M2SW0_IDX_MASK 0xFFu
#define ESPI_M2SW0_MTOS_SRC_POS 8u
#define ESPI_M2SW0_MTOS_SRC_MASK0 0x03u
#define ESPI_M2SW0_MTOS_SRC_MASK ((ESPI_VW_M2S_MTOS_SRC_MASK0) << (ESPI_VW_M2S_MTOS_SRC_POS))
#define ESPI_M2SW0_MTOS_SRC_ESPI_RST ((0ul) << (ESPI_VW_M2S_MTOS_SRC_POS))
#define ESPI_M2SW0_MTOS_SRC_SYS_RST ((1ul) << (ESPI_VW_M2S_MTOS_SRC_POS))
#define ESPI_M2SW0_MTOS_SRC_SIO_RST ((2ul) << (ESPI_VW_M2S_MTOS_SRC_POS))
#define ESPI_M2SW0_MTOS_SRC_PLTRST ((3ul) << (ESPI_VW_M2S_MTOS_SRC_POS))
#define ESPI_M2SW0_MTOS_STATE_POS 12u
#define ESPI_M2SW0_MTOS_STATE_MASK0 0x0Ful
#define ESPI_M2SW0_MTOS_STATE_MASK ((ESPI_VW_M2S_MTOS_STATE_MASK0) << (ESPI_VW_M2S_MTOS_STATE_POS))
/* 32-bit word 1 (bits[63:32]) */
#define ESPI_M2SW1_OFS 4ul
#define ESPI_M2SW1_SRC0_SEL_POS 0
#define ESPI_M2SW1_SRC_SEL_MASK0 0x0Ful
#define ESPI_M2SW1_SRC0_SEL_MASK ((ESPI_M2SW1_SRC_SEL_MASK0) << (ESPI_M2SW1_SRC0_SEL_POS))
#define ESPI_M2SW1_SRC1_SEL_POS 8
#define ESPI_M2SW1_SRC1_SEL_MASK ((ESPI_M2SW1_SRC_SEL_MASK0) << (ESPI_M2SW1_SRC1_SEL_POS))
#define ESPI_M2SW1_SRC2_SEL_POS 16
#define ESPI_M2SW1_SRC2_SEL_MASK ((ESPI_M2SW1_SRC_SEL_MASK0) << (ESPI_M2SW1_SRC2_SEL_POS))
#define ESPI_M2SW1_SRC3_SEL_POS 24
#define ESPI_M2SW1_SRC3_SEL_MASK ((ESPI_M2SW1_SRC_SEL_MASK0) << (ESPI_M2SW1_SRC3_SEL_POS))
/* 0 <= n < 4 */
#define ESPI_M2SW1_SRC_SEL_POS(n) ((n) << 3)
#define ESPI_M2SW1_SRC_SEL_MASK(n) ((0x0Ful) << (ESPI_M2SW1_SRC_SEL_POS(n)))
#define ESPI_M2SW1_SRC_SEL_VAL(n, v) (((uint32_t)(v) & 0x0Ful) << (ESPI_M2SW1_SRC_SEL_POS(n)))
/* 32-bit word 2 (bits[95:64]) */
#define ESPI_M2SW2_OFS 8ul
#define ESPI_M2SW2_SRC_MASK0 0x0Ful
#define ESPI_M2SW2_SRC0_POS 0
#define ESPI_M2SW2_SRC0_MASK ((ESPI_M2SW1_SRC_MASK0) << (ESPI_M2SW1_SRC0_POS))
#define ESPI_M2SW2_SRC1_POS 8u
#define ESPI_M2SW2_SRC1_MASK ((ESPI_M2SW1_SRC_MASK0) << (ESPI_M2SW1_SRC1_POS))
#define ESPI_M2SW2_SRC2_POS 16u
#define ESPI_M2SW2_SRC2_MASK ((ESPI_M2SW1_SRC_MASK0) << (ESPI_M2SW2_SRC1_POS))
#define ESPI_M2SW2_SRC3_POS 24u
#define ESPI_M2SW2_SRC3_MASK ((ESPI_M2SW1_SRC_MASK0) << (ESPI_M2SW2_SRC3_POS))
/* 0 <= n < 4 */
#define ESPI_M2SW2_SRC_POS(n) ((n) << 3)
#define ESPI_M2SW2_SRC_MASK(n) ((ESPI_M2SW2_SRC_MASK0) << (ESPI_M2SW2_SRC_POS(n)))
#define ESPI_M2SW2_SRC_VAL(n, v) (((uint32_t)(v) & 0x0Ful) << (ESPI_M2SW2_SRC_POS(n)))
/*
* Zero based values used for above SRC_SEL fields.
* These values select the interrupt sensitivity for the VWire.
* Example: Set SRC1 to Level High
*
* r = read MSVW1 register
* r &= ESPI_M2SW1_SRC_SEL_MASK(1)
* r |= ESPI_MSVW1_SRC_SEL_VAL(1, ESPI_IRQ_SEL_LVL_HI)
* write r to MSVW1 register
*/
#define ESPI_IRQ_SEL_LVL_LO 0
#define ESPI_IRQ_SEL_LVL_HI 1
#define ESPI_IRQ_SEL_DIS 4
/* NOTE: Edge trigger modes allow VWires to wake MEC1501 from deep sleep */
#define ESPI_IRQ_SEL_REDGE 0x0D
#define ESPI_IRQ_SEL_FEDGE 0x0E
#define ESPI_IRQ_SEL_BEDGE 0x0F
/* Slave to Master VW register: 64-bit (2 32 bit registers) */
/* 32-bit word 0 (bits[31:0]) */
#define ESPI_S2MW0_OFS 0
#define ESPI_S2MW0_IDX_POS 0
#define ESPI_S2MW0_IDX_MASK 0xFFu
#define ESPI_S2MW0_STOM_POS 8u
#define ESPI_S2MW0_STOM_SRC_POS 8u
#define ESPI_S2MW0_STOM_MASK0 0xF3u
#define ESPI_S2MW0_STOM_MASK ((ESPI_S2MW0_STOM_MASK0) << (ESPI_S2MW0_STOM_SRC_POS))
#define ESPI_S2MW0_STOM_SRC_MASK0 0x03ul
#define ESPI_S2MW0_STOM_SRC_MASK ((ESPI_S2MW0_STOM_SRC_MASK0) << (ESPI_S2MW0_STOM_SRC_POS))
#define ESPI_S2MW0_STOM_SRC_ESPI_RST ((0ul) << (ESPI_S2MW0_STOM_SRC_POS))
#define ESPI_S2MW0_STOM_SRC_SYS_RST ((1ul) << (ESPI_S2MW0_STOM_SRC_POS))
#define ESPI_S2MW0_STOM_SRC_SIO_RST ((2ul) << (ESPI_S2MW0_STOM_SRC_POS))
#define ESPI_S2MW0_STOM_SRC_PLTRST ((3ul) << (ESPI_S2MW0_STOM_SRC_POS))
#define ESPI_S2MW0_STOM_STATE_POS 12u
#define ESPI_S2MW0_STOM_STATE_MASK0 0x0Ful
#define ESPI_S2MW0_STOM_STATE_MASK ((ESPI_S2MW0_STOM_STATE_MASK0) << (ESPI_S2MW0_STOM_STATE_POS))
#define ESPI_S2MW0_CHG0_POS 16u
#define ESPI_S2MW0_CHG0 (1ul << (ESPI_S2MW0_CHG0_POS))
#define ESPI_S2MW0_CHG1_POS 17u
#define ESPI_S2MW0_CHG1 (1ul << (ESPI_S2MW0_CHG1_POS))
#define ESPI_S2MW0_CHG2_POS 18u
#define ESPI_S2MW0_CHG2 (1ul << (ESPI_S2MW0_CHG2_POS))
#define ESPI_S2MW0_CHG3_POS 19u
#define ESPI_S2MW0_CHG3 (1ul << (ESPI_S2MW0_CHG3_POS))
#define ESPI_S2MW0_CHG_ALL_POS 16u
#define ESPI_S2MW0_CHG_ALL_MASK0 0x0Ful
#define ESPI_S2MW0_CHG_ALL_MASK ((ESPI_S2MW0_CHG_ALL_MASK0) << (ESPI_S2MW0_CHG0_POS))
/* 0 <= n < 4 */
#define ESPI_S2MW1_CHG_POS(n) ((n) + 16u)
#define ESPI_S2MW1_CHG(v, n) (((uint32_t)(v) >> ESPI_S2MW1_CHG_POS(n)) & 0x01)
/* 32-bit word 1 (bits[63:32]) */
#define ESPI_S2MW1_OFS 4ul
#define ESPI_S2MW1_SRC0_POS 0u
#define ESPI_S2MW1_SRC0 (1ul << (ESPI_S2MW1_SRC0_POS))
#define ESPI_S2MW1_SRC1_POS 8u
#define ESPI_S2MW1_SRC1 (1ul << (ESPI_S2MW1_SRC1_POS))
#define ESPI_S2MW1_SRC2_POS 16u
#define ESPI_S2MW1_SRC2 (1ul << (ESPI_S2MW1_SRC2_POS))
#define ESPI_S2MW1_SRC3_POS 24u
#define ESPI_S2MW1_SRC3 (1ul << (ESPI_S2MW1_SRC3_POS))
/* 0 <= n < 4 */
#define ESPI_S2MW1_SRC_POS(n) ((n) << 3)
#define ESPI_S2MW1_SRC(v, n) (((uint32_t)(v) & 0x01) << (ESPI_S2MW1_SRC_POS(n)))
/* =========================================================================*/
/* ================ ESPI_VW ================ */
/* =========================================================================*/
/**
* @brief eSPI Virtual Wires (ESPI_VW)
*/
#define ESPI_MSVW_IDX_MAX 10u
#define ESPI_SMVW_IDX_MAX 10u
#define ESPI_NUM_MSVW 11u
#define ESPI_NUM_SMVW 11u
/*
* ESPI MSVW interrupts
*/
#define MEC_ESPI_MSVW_00_06_GIRQ 24u
#define MEC_ESPI_MSVW_00_06_NVIC 15u
#define MEC_ESPI_MSVW00_SRC0_POS 0u
#define MEC_ESPI_MSVW00_SRC1_POS 1u
#define MEC_ESPI_MSVW00_SRC2_POS 2u
#define MEC_ESPI_MSVW00_SRC3_POS 3u
#define MEC_ESPI_MSVW01_SRC0_POS 4u
#define MEC_ESPI_MSVW01_SRC1_POS 5u
#define MEC_ESPI_MSVW01_SRC2_POS 6u
#define MEC_ESPI_MSVW01_SRC3_POS 7u
#define MEC_ESPI_MSVW02_SRC0_POS 8u
#define MEC_ESPI_MSVW02_SRC1_POS 9u
#define MEC_ESPI_MSVW02_SRC2_POS 10u
#define MEC_ESPI_MSVW02_SRC3_POS 11u
#define MEC_ESPI_MSVW03_SRC0_POS 12u
#define MEC_ESPI_MSVW03_SRC1_POS 13u
#define MEC_ESPI_MSVW03_SRC2_POS 14u
#define MEC_ESPI_MSVW03_SRC3_POS 15u
#define MEC_ESPI_MSVW04_SRC0_POS 16u
#define MEC_ESPI_MSVW04_SRC1_POS 17u
#define MEC_ESPI_MSVW04_SRC2_POS 16u
#define MEC_ESPI_MSVW04_SRC3_POS 19u
#define MEC_ESPI_MSVW05_SRC0_POS 20u
#define MEC_ESPI_MSVW05_SRC1_POS 21u
#define MEC_ESPI_MSVW05_SRC2_POS 22u
#define MEC_ESPI_MSVW05_SRC3_POS 23u
#define MEC_ESPI_MSVW06_SRC0_POS 24u
#define MEC_ESPI_MSVW06_SRC1_POS 25u
#define MEC_ESPI_MSVW06_SRC2_POS 26u
#define MEC_ESPI_MSVW06_SRC3_POS 27u
/*
* 0 <= v <= 6
* 0 <= s <= 3
*/
#define MEC_ESPI_MSVW_00_06_GIRQ_POS(v, s) (((uint32_t)(v) << 2) + (uint32_t)(s))
#define MEC_ESPI_VSVW_07_10_GIRQ 25u
#define MEC_ESPI_VSVW_07_10_NVIC 16u
#define MEC_ESPI_MSVW07_SRC0_POS 0u
#define MEC_ESPI_MSVW07_SRC1_POS 1u
#define MEC_ESPI_MSVW07_SRC2_POS 2u
#define MEC_ESPI_MSVW07_SRC3_POS 3u
#define MEC_ESPI_MSVW08_SRC0_POS 4u
#define MEC_ESPI_MSVW08_SRC1_POS 5u
#define MEC_ESPI_MSVW08_SRC2_POS 6u
#define MEC_ESPI_MSVW08_SRC3_POS 7u
#define MEC_ESPI_MSVW09_SRC0_POS 8u
#define MEC_ESPI_MSVW09_SRC1_POS 9u
#define MEC_ESPI_MSVW09_SRC2_POS 10u
#define MEC_ESPI_MSVW09_SRC3_POS 11u
#define MEC_ESPI_MSVW10_SRC0_POS 12u
#define MEC_ESPI_MSVW10_SRC1_POS 13u
#define MEC_ESPI_MSVW10_SRC2_POS 14u
#define MEC_ESPI_MSVW10_SRC3_POS 15u
/*
* 7 <= v <= 10
* 0 <= s <= 3
*/
#define MEC_ESPI_MSVW_07_10_GIRQ_POS(v, s) ((((uint32_t)(v) - 7ul) << 2) + (uint32_t)(s))
/* Master-to-Slave VW byte indices(offsets) */
#define MSVW_INDEX_OFS 0u
#define MSVW_MTOS_OFS 1u
#define MSVW_SRC0_ISEL_OFS 4u
#define MSVW_SRC1_ISEL_OFS 5u
#define MSVW_SRC2_ISEL_OFS 6u
#define MSVW_SRC3_ISEL_OFS 7u
#define MSVW_SRC0_OFS 8u
#define MSVW_SRC1_OFS 9u
#define MSVW_SRC2_OFS 10u
#define MSVW_SRC3_OFS 11u
/* Slave-to-Master VW byte indices(offsets) */
#define SMVW_INDEX_OFS 0u
#define SMVW_STOM_OFS 1u
#define SMVW_CHANGED_OFS 2u
#define SMVW_SRC0_OFS 4u
#define SMVW_SRC1_OFS 5u
#define SMVW_SRC2_OFS 6u
#define SMVW_SRC3_OFS 7u
/*
* ESPI_IO_VW - eSPI IO component registers related to VW channel @ 0x400F36B0
*/
typedef struct {
__IOM uint32_t VW_EN_STS; /*! (@ 0x0000) Virtual Wire Enable Status */
uint8_t RSVD1[0x30];
__IOM uint8_t VW_CAP; /*! (@ 0x0034) Virtual Wire Chan Capabilities */
uint8_t RSVD2[8];
__IOM uint8_t VW_RDY; /*! (@ 0x003D) VW ready */
uint8_t RSVD3[0x102];
__IOM uint32_t VW_ERR_STS; /*! (@ 0x0140) IO Virtual Wire Error */
} ESPI_IO_VW;
/* Master-to-Slave Virtual Wire 96-bit register */
#define MEC_MSVW_SRC0_IRQ_SEL_POS 0u
#define MEC_MSVW_SRC1_IRQ_SEL_POS 8u
#define MEC_MSVW_SRC2_IRQ_SEL_POS 16u
#define MEC_MSVW_SRC3_IRQ_SEL_POS 24u
#define MEC_MSVW_SRC_IRQ_SEL_MASK0 0x0Ful
#define MEC_MSVW_SRC0_IRQ_SEL_MASK (0x0Ful << 8)
#define MEC_MSVW_SRC1_IRQ_SEL_MASK (0x0Ful << 16)
#define MEC_MSVW_SRC2_IRQ_SEL_MASK (0x0Ful << 16)
#define MEC_MSVW_SRC3_IRQ_SEL_MASK (0x0Ful << 24)
#define MEC_MSVW_SRC_IRQ_SEL_LVL_LO 0x00ul
#define MEC_MSVW_SRC_IRQ_SEL_LVL_HI 0x01ul
#define MEC_MSVW_SRC_IRQ_SEL_DIS 0x04ul
#define MEC_MSVW_SRC_IRQ_SEL_EDGE_FALL 0x0Dul
#define MEC_MSVW_SRC_IRQ_SEL_EDGE_RISE 0x0Eul
#define MEC_MSVW_SRC_IRQ_SEL_EDGE_BOTH 0x0Ful
/*
* 0 <= src <= 3
* isel = MEC_MSVW_SRC_IRQ_SEL_LVL_LO, ...
*/
#define MEC_MSVW_SRC_IRQ_SEL_VAL(src, isel) ((uint32_t)(isel) << ((src) << 3))
#define MEC_MSVW_SRC0_POS 0ul
#define MEC_MSVW_SRC1_POS 8ul
#define MEC_MSVW_SRC2_POS 16ul
#define MEC_MSVW_SRC3_POS 24ul
#define MEC_MSVW_SRC_MASK0 0x01ul
#define MEC_MSVW_SRC0_MASK (0x01ul << 0)
#define MEC_MSVW_SRC1_MASK (0x01ul << 8)
#define MEC_MSVW_SRC2_MASK (0x01ul << 16)
#define MEC_MSVW_SRC3_MASK (0x01ul << 24)
/*
* 0 <= src <= 3
* val = 0 or 1
*/
#define MEC_MSVW_SRC_VAL(src, val) ((uint32_t)(val & 0x01u) << ((src) << 3))
typedef struct espi_msvw_reg {
__IOM uint8_t INDEX;
__IOM uint8_t MTOS;
uint8_t RSVD1[2];
__IOM uint32_t SRC_IRQ_SEL;
__IOM uint32_t SRC;
} ESPI_MSVW_REG;
typedef struct {
ESPI_MSVW_REG MSVW00;
ESPI_MSVW_REG MSVW01;
ESPI_MSVW_REG MSVW02;
ESPI_MSVW_REG MSVW03;
ESPI_MSVW_REG MSVW04;
ESPI_MSVW_REG MSVW05;
ESPI_MSVW_REG MSVW06;
ESPI_MSVW_REG MSVW07;
ESPI_MSVW_REG MSVW08;
ESPI_MSVW_REG MSVW09;
ESPI_MSVW_REG MSVW10;
} ESPI_M2S_VW;
/* Slave-to-Master Virtual Wire 64-bit register */
typedef struct espi_smvw_reg {
__IOM uint8_t INDEX;
__IOM uint8_t STOM;
__IM uint8_t SRC_CHG;
uint8_t RSVD1[1];
__IOM uint32_t SRC;
} ESPI_SMVW_REG;
typedef struct {
ESPI_SMVW_REG SMVW00;
ESPI_SMVW_REG SMVW01;
ESPI_SMVW_REG SMVW02;
ESPI_SMVW_REG SMVW03;
ESPI_SMVW_REG SMVW04;
ESPI_SMVW_REG SMVW05;
ESPI_SMVW_REG SMVW06;
ESPI_SMVW_REG SMVW07;
ESPI_SMVW_REG SMVW08;
ESPI_SMVW_REG SMVW09;
ESPI_SMVW_REG SMVW10;
} ESPI_S2M_VW;
/* MSVW helper inline functions */
enum espi_msvw_src {
MSVW_SRC0 = 0u,
MSVW_SRC1,
MSVW_SRC2,
MSVW_SRC3
};
enum espi_smvw_src {
SMVW_SRC0 = 0u,
SMVW_SRC1,
SMVW_SRC2,
SMVW_SRC3
};
enum espi_msvw_irq_sel {
MSVW_IRQ_SEL_LVL_LO = 0x00ul,
MSVW_IRQ_SEL_LVL_HI = 0x01ul,
MSVW_IRQ_SEL_DIS = 0x04ul,
MSVW_IRQ_SEL_EDGE_FALL = 0x0Dul,
MSVW_IRQ_SEL_EDGE_RISE = 0x0Eul,
MSVW_IRQ_SEL_EDGE_BOTH = 0x0Ful
};
/* Used for both MSVW MTOS and SMVW STOM fields */
enum espi_vw_rst_src {
VW_RST_SRC_ESPI_RESET = 0ul,
VW_RST_SRC_SYS_RESET,
VW_RST_SRC_SIO_RESET,
VW_RST_SRC_PLTRST,
};
/*
* Set the Host VWire index this MSVW implements.
*/
static __attribute__ ((always_inline))
inline void mec_espi_msvw_index_set(ESPI_MSVW_REG * p, uint8_t host_vw_index)
{
p->INDEX = host_vw_index;
}
static __attribute__ ((always_inline))
inline uint8_t mec_espi_msvw_index_get(ESPI_MSVW_REG * p)
{
return p->INDEX;
}
/*
* This functions sets the two MTOS fields in a MSVW
* Reset source
* Reset value of SRC[3:0]
*/
static __attribute__ ((always_inline))
inline void
mec_espi_msvw_mtos_set(ESPI_MSVW_REG * p, enum espi_vw_rst_src rst_src,
uint8_t rst_val)
{
p->MTOS = (rst_src & 0x03u) | ((rst_val & 0x0Fu) << 4);
}
static __attribute__ ((always_inline))
inline void
mec_espi_msvw_irq_sel_set(ESPI_MSVW_REG * p, enum espi_msvw_src src,
enum espi_msvw_irq_sel isel)
{
volatile uint8_t *psrc = (volatile uint8_t *)p->SRC_IRQ_SEL;
*(psrc + (uintptr_t) src) = isel;
}
/*
* Set all IRQ_SEL fields in a MSVW.
* Parameter isel_all must have IRQ_SEL fields at
* b[3:0], b[11:8], b[19:16], b[27:24].
*/
static __attribute__ ((always_inline))
inline void mec_espi_msvw_irq_sel_set_all(ESPI_MSVW_REG * p, uint32_t isel_all)
{
p->SRC_IRQ_SEL = isel_all;
}
static __attribute__ ((always_inline))
inline void
mec_espi_msvw_set(ESPI_MSVW_REG * p, enum espi_msvw_src src, uint8_t src_val)
{
volatile uint8_t *psrc = (volatile uint8_t *)p->SRC;
*(psrc + (uintptr_t) src) = src_val;
}
static __attribute__ ((always_inline))
inline uint8_t mec_espi_msvw_get(ESPI_MSVW_REG * p, enum espi_msvw_src src)
{
return (uint8_t) ((p->SRC >> (src << 3)) & 0x01ul);
}
/*
* Return 32-bit unsigned word containing all 4 MSVW SRC bits in
* bit positions 0, 8, 16, and 24.
*/
static __attribute__ ((always_inline))
inline uint32_t mec_espi_msvw_get_all(ESPI_MSVW_REG * p)
{
return p->SRC;
}
/*
* Write 32-bit unsigned word containing all 4 MSVW SRC bits in
* bit positions 0, 8, 16, and 24.
* NOTE: eSPI master will only see changes to Master-to-Slave VWires
* if it requests reading them.
*/
static __attribute__ ((always_inline))
inline void mec_espi_msvw_set_all(ESPI_MSVW_REG * p, uint32_t val)
{
p->SRC = val;
}
/* SMVW helper inline functions */
/*
* Set the Host VWire index this SMVW implements.
*/
static __attribute__ ((always_inline))
inline void mec_espi_smvw_index_set(ESPI_SMVW_REG * p, uint8_t host_vw_index)
{
p->INDEX = host_vw_index;
}
/*
* Set the Host VWire index this SMVW implements.
*/
static __attribute__ ((always_inline))
inline uint8_t mec_espi_smvw_index_get(ESPI_SMVW_REG * p)
{
return p->INDEX;
}
/*
* This functions sets the two STOM fields in a SMVW
* Reset source
* Reset value of SRC[3:0]
*/
static __attribute__ ((always_inline))
inline void
mec_espi_msvw_stom_set(ESPI_SMVW_REG * p, enum espi_vw_rst_src rst_src,
uint8_t rst_bitmap)
{
p->STOM = (rst_src & 0x03u) | ((rst_bitmap & 0x0Fu) << 4);
}
/*
* Return SMVW source change bitmap
* b[3:0] = SRC[3:0] change where 1=change, 0=no change
* A SRC change bit == 1 indicates the EC has updated the corresponding
* SRC bit with a new value. HW will transmit all 4 SMVW bits when the
* eSPI bus becomes available. Once transmitted HW will clear SRC CHG bit(s).
*/
static __attribute__ ((always_inline))
inline uint8_t mec_espi_smvw_get_chg(ESPI_SMVW_REG * p)
{
return p->SRC_CHG;
}
/*
* Return 32-bit unsigned word containing all 4 SMVW SRC bits in
* bit positions 0, 8, 16, and 24.
*/
static __attribute__ ((always_inline))
inline uint32_t mec_espi_smvw_get_all(ESPI_SMVW_REG * p)
{
return p->SRC;
}
/*
* Write 32-bit unsigned word containing all 4 SMVW SRC bits in
* bit positions 0, 8, 16, and 24.
*/
static __attribute__ ((always_inline))
inline void mec_espi_smvw_set_all(ESPI_SMVW_REG * p, uint32_t new_srcs)
{
p->SRC = new_srcs;
}
/*
* Write 32-bit unsigned word containing all 4 SMVW SRC bits in
* bit positions 0, 8, 16, and 24 from bitmap where
* bitmap[0] -> SRC bit[0]
* bitmap[1] -> SRC bit[8]
* bitmap[2] -> SRC bit[16]
* bitmap[3] -> SRC bit[24]
*/
static __attribute__ ((always_inline))
inline void mec_espi_smvw_set_all_bitmap(ESPI_SMVW_REG * p, uint8_t src_bitmap)
{
uint32_t i, srcs;
srcs = 0ul;
for (i = 0; i < 4ul; i++) {
if (src_bitmap & (1ul << i)) {
srcs |= (1ul << (i << 3));
}
}
p->SRC = srcs;
}
static __attribute__ ((always_inline))
inline uint8_t mec_espi_smvw_get(ESPI_SMVW_REG * p, enum espi_smvw_src src)
{
return (uint8_t) ((p->SRC >> (src << 3)) & 0x01ul);
}
static __attribute__ ((always_inline))
inline void
mec_espi_smvw_set(ESPI_SMVW_REG * p, enum espi_smvw_src src, uint8_t new_val)
{
volatile uint8_t *p8 = (volatile uint8_t *)&p->SRC;
*(p8 + (uintptr_t) src) = new_val;
}
#endif /* #ifndef _ESPI_VW_H */
/* end espi_vw.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file i2c.h
*MEC1501 I2C register definitions
*/
/** @defgroup MEC1501 Peripherals I2C
*/
#ifndef _I2C_H
#define _I2C_H
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
#define MCHP_I2C_MAX_INSTANCES 3u
#define MCHP_I2C_INST_SPACING 0x100ul
#define MCHP_I2C_INST_SPACING_P2 8u
#define MCHP_I2C0_BASE_ADDR 0x40005100ul
#define MCHP_I2C1_BASE_ADDR 0x40005200ul
#define MCHP_I2C2_BASE_ADDR 0x40005300ul
/* 0 <= n < MCHP_I2C_MAX_INSTANCES */
#define MCHP_I2C_BASE_ADDR(n) \
((MCHP_I2C0_BASE_ADDR) + (n) << (MCHP_I2C_INST_SPACING_P2))
/*
* Offset 0x00
* Control and Status register
* Write to Control
* Read from Status
* Size 8-bit
*/
#define MCHP_I2C_CTRL_OFS 0x00ul
#define MCHP_I2C_CTRL_MASK 0xCFu
#define MCHP_I2C_CTRL_ACK (1u << 0)
#define MCHP_I2C_CTRL_STO (1u << 1)
#define MCHP_I2C_CTRL_STA (1u << 2)
#define MCHP_I2C_CTRL_ENI (1u << 3)
/* bits [5:4] reserved */
#define MCHP_I2C_CTRL_ESO (1u << 6)
#define MCHP_I2C_CTRL_PIN (1u << 7)
/* Status Read-only */
#define MCHP_I2C_STS_OFS 0x00ul
#define MCHP_I2C_STS_NBB (1u << 0)
#define MCHP_I2C_STS_LAB (1u << 1)
#define MCHP_I2C_STS_AAS (1u << 2)
#define MCHP_I2C_STS_LRB_AD0 (1u << 3)
#define MCHP_I2C_STS_BER (1u << 4)
#define MCHP_I2C_STS_EXT_STOP (1u << 5)
#define MCHP_I2C_STS_PIN (1u << 7)
/*
* Offset 0x04
* Own Address b[7:0] = Slave address 1
* b[14:8] = Slave address 2
*/
#define MCHP_I2C_OWN_ADDR_OFS 0x04ul
#define MCHP_I2C_OWN_ADDR2_OFS 0x05ul
#define MCHP_I2C_OWN_ADDR_MASK 0x7F7Ful
/*
* Offset 0x08
* Data register, 8-bit
* Data to be shifted out or shifted in.
*/
#define MCHP_I2C_DATA_OFS 0x08ul
/*
* Offset 0x18
* Repeated Start Hold Time register, 8-bit read-write
*/
#define MCHP_I2C_RSHT_OFS 0x18ul
/*
* Offset 0x20
* Complettion register, 32-bit
*/
#define MCHP_I2C_CMPL_OFS 0x20ul
#define MCHP_I2C_CMPL_MASK 0xE33B7F7Cul
#define MCHP_I2C_CMPL_RW1C_MASK 0xE1397F00ul
#define MCHP_I2C_CMPL_DTEN (1ul << 2)
#define MCHP_I2C_CMPL_MCEN (1ul << 3)
#define MCHP_I2C_CMPL_SCEN (1ul << 4)
#define MCHP_I2C_CMPL_BIDEN (1ul << 5)
#define MCHP_I2C_CMPL_TIMERR (1ul << 6)
#define MCHP_I2C_CMPL_DTO_RWC (1ul << 8)
#define MCHP_I2C_CMPL_MCTO_RWC (1ul << 9)
#define MCHP_I2C_CMPL_SCTO_RWC (1ul << 10)
#define MCHP_I2C_CMPL_CHDL_RWC (1ul << 11)
#define MCHP_I2C_CMPL_CHDH_RWC (1ul << 12)
#define MCHP_I2C_CMPL_BER_RWC (1ul << 13)
#define MCHP_I2C_CMPL_LAB_RWC (1ul << 14)
#define MCHP_I2C_CMPL_SNAKR_RWC (1ul << 16)
#define MCHP_I2C_CMPL_STR_RO (1ul << 17)
#define MCHP_I2C_CMPL_RPT_RD_RWC (1ul << 20)
#define MCHP_I2C_CMPL_RPT_WR_RWC (1ul << 21)
#define MCHP_I2C_CMPL_MNAKX_RWC (1ul << 24)
#define MCHP_I2C_CMPL_MTR_RO (1ul << 25)
#define MCHP_I2C_CMPL_IDLE_RWC (1ul << 29)
#define MCHP_I2C_CMPL_MDONE_RWC (1ul << 30)
#define MCHP_I2C_CMPL_SDONE_RWC (1ul << 31)
/*
* Offset 0x28
* Configuration register
*/
#define MCHP_I2C_CFG_OFS 0x28ul
#define MCHP_I2C_CFG_MASK 0x0000C73Ful
#define MCHP_I2C_CFG_PORT_SEL_MASK 0x0Ful
#define MCHP_I2C_CFG_TCEN (1ul << 4)
#define MCHP_I2C_CFG_SLOW_CLK (1ul << 5)
#define MCHP_I2C_CFG_FEN (1ul << 8)
#define MCHP_I2C_CFG_RESET (1ul << 9)
#define MCHP_I2C_CFG_ENAB (1ul << 10)
#define MCHP_I2C_CFG_GC_EN (1ul << 14)
#define MCHP_I2C_CFG_PROM_EN (1ul << 15)
/*
* Offset 0x2C
* Bus Clock register
*/
#define MCHP_I2C_BUS_CLK_OFS 0x2Cul
#define MCHP_I2C_BUS_CLK_MASK 0x0000FFFFul
#define MCHP_I2C_BUS_CLK_LO_POS 0u
#define MCHP_I2C_BUS_CLK_HI_POS 8u
/*
* Offset 0x30
* Block ID register, 8-bit read-only
*/
#define MCHP_I2C_BLOCK_ID_OFS 0x30ul
#define MCHP_I2C_BLOCK_ID_MASK 0xFFul
/*
* Offset 0x34
* Block Revision register, 8-bit read-only
*/
#define MCHP_I2C_BLOCK_REV_OFS 0x34ul
#define MCHP_I2C_BLOCK_REV_MASK 0xFFul
/*
* Offset 0x38
* Bit-Bang Control register, 8-bit read-write
*/
#define MCHP_I2C_BB_OFS 0x38ul
#define MCHP_I2C_BB_MASK 0x7Fu
#define MCHP_I2C_BB_EN (1ul << 0)
#define MCHP_I2C_BB_SCL_DIR_IN (0ul << 1)
#define MCHP_I2C_BB_SCL_DIR_OUT (1ul << 1)
#define MCHP_I2C_BB_SDA_DIR_IN (0ul << 2)
#define MCHP_I2C_BB_SDA_DIR_OUT (1ul << 2)
#define MCHP_I2C_BB_CL (1ul << 3)
#define MCHP_I2C_BB_DAT (1ul << 4)
#define MCHP_I2C_BB_IN_POS 5u
#define MCHP_I2C_BB_IN_MASK0 0x03ul
#define MCHP_I2C_BB_IN_MASK (0x03ul << 5)
#define MCHP_I2C_BB_CLKI_RO (1ul << 5)
#define MCHP_I2C_BB_DATI_RO (1ul << 6)
/*
* Offset 0x40
* Data Timing register
*/
#define MCHP_I2C_DATA_TM_OFS 0x40ul
#define MCHP_I2C_DATA_TM_MASK 0xFFFFFFFFul
#define MCHP_I2C_DATA_TM_DATA_HOLD_POS 0u
#define MCHP_I2C_DATA_TM_DATA_HOLD_MASK 0xFFul
#define MCHP_I2C_DATA_TM_DATA_HOLD_MASK0 0xFFul
#define MCHP_I2C_DATA_TM_RESTART_POS 8u
#define MCHP_I2C_DATA_TM_RESTART_MASK 0xFF00ul
#define MCHP_I2C_DATA_TM_RESTART_MASK0 0xFFul
#define MCHP_I2C_DATA_TM_STOP_POS 16u
#define MCHP_I2C_DATA_TM_STOP_MASK 0xFF0000ul
#define MCHP_I2C_DATA_TM_STOP_MASK0 0xFFul
#define MCHP_I2C_DATA_TM_FSTART_POS 24u
#define MCHP_I2C_DATA_TM_FSTART_MASK 0xFF000000ul
#define MCHP_I2C_DATA_TM_FSTART_MASK0 0xFFul
/*
* Offset 0x44
* Time-out Scaling register
*/
#define MCHP_I2C_TMTSC_OFS 0x44ul
#define MCHP_I2C_TMTSC_MASK 0xFFFFFFFFul
#define MCHP_I2C_TMTSC_CLK_HI_POS 0u
#define MCHP_I2C_TMTSC_CLK_HI_MASK 0xFFul
#define MCHP_I2C_TMTSC_CLK_HI_MASK0 0xFFul
#define MCHP_I2C_TMTSC_SLV_POS 8u
#define MCHP_I2C_TMTSC_SLV_MASK 0xFF00ul
#define MCHP_I2C_TMTSC_SLV_MASK0 0xFFul
#define MCHP_I2C_TMTSC_MSTR_POS 16u
#define MCHP_I2C_TMTSC_MSTR_MASK 0xFF0000ul
#define MCHP_I2C_TMTSC_MSTR_MASK0 0xFFul
#define MCHP_I2C_TMTSC_BUS_POS 24u
#define MCHP_I2C_TMTSC_BUS_MASK 0xFF000000ul
#define MCHP_I2C_TMTSC_BUS_MASK0 0xFFul
/*
* Offset 0x60
* Wake Status register
*/
#define MCHP_I2C_WAKE_STS_OFS 0x60ul
#define MCHP_I2C_WAKE_STS_START_RWC (1ul << 0)
/*
* Offset 0x64
* Wake Enable register
*/
#define MCHP_I2C_WAKE_EN_OFS 0x64ul
#define MCHP_I2C_WAKE_EN (1ul << 0)
/*
* Offset 0x6C
* Slave Address captured from bus
*/
#define MCHP_I2C_SLV_ADDR_OFS 0x6Cul
#define MCHP_I2C_SLV_ADDR_MASK 0xFFul
/*
* Offset 0x70
* Promiscuous Interrupt Status
*/
#define MCHP_I2C_PROM_INTR_STS_OFS 0x70ul
#define MCHP_I2C_PROM_INTR_STS 0x01ul
/*
* Offset 0x74
* Promiscuous Interrupt Enable
*/
#define MCHP_I2C_PROM_INTR_EN_OFS 0x74ul
#define MCHP_I2C_PROM_INTR_EN 0x01ul
/*
* Offset 0x78
* Promiscuous Control
*/
#define MCHP_I2C_PROM_CTRL_OFS 0x78ul
#define MCHP_I2C_PROM_CTRL_ACK_ADDR 0x01ul
#define MCHP_I2C_PROM_CTRL_NACK_ADDR 0x00ul
/*
* I2C GIRQ and NVIC mapping
*/
#define MCHP_I2C_GIRQ 3u
#define MCHP_I2C_GIRQ_IDX (13u - 8u)
#define MCHP_I2C_NVIC_GIRQ 5u
#define MCHP_I2C0_NVIC_DIRECT 168u
#define MCHP_I2C1_NVIC_DIRECT 169u
#define MCHP_I2C2_NVIC_DIRECT 170u
#define MCHP_I2C_GIRQ_SRC_ADDR 0x4000E064ul
#define MCHP_I2C_GIRQ_SET_EN_ADDR 0x4000E068ul
#define MCHP_I2C_GIRQ_RESULT_ADDR 0x4000E06Cul
#define MCHP_I2C_GIRQ_CLR_EN_ADDR 0x4000E070ul
#define MCHP_I2C0_GIRQ_POS 5u
#define MCHP_I2C1_GIRQ_POS 6u
#define MCHP_I2C2_GIRQ_POS 7u
#define MCHP_I2C0_GIRQ_VAL (1ul << 5)
#define MCHP_I2C1_GIRQ_VAL (1ul << 6)
#define MCHP_I2C2_GIRQ_VAL (1ul << 7)
/*
* Register access by controller base address
*/
/* I2C Control register, write-only */
#define MCHP_I2C_CTRL_WO(ba) REG8(ba)
/* I2C Status register, read-only */
#define MCHP_I2C_STS_RO(ba) REG8(ba)
#define MCHP_I2C_CTRL(ba) REG8_OFS(ba, MCHP_I2C_CTRL_OFS)
/* Own Address register (slave addresses) */
#define MCHP_I2C_OWN_ADDR(ba) REG16_OFS(ba, MCHP_I2C_OWN_ADDR_OFS)
/* access bits[7:0] OWN_ADDRESS_1 */
#define MCHP_I2C_OWN_ADDR1(ba) REG8_OFS(ba, MCHP_I2C_OWN_ADDR_OFS)
/* access bits[15:8] OWN_ADDRESS_2 */
#define MCHP_I2C_OWN_ADDR2(ba) REG8_OFS(ba, (MCHP_I2C_OWN_ADDR_OFS + 1))
/* I2C Data register */
#define MCHP_I2C_DATA(ba) REG8_OFS(ba, MCHP_I2C_DATA_OFS)
/* Repeated Start Hold Time register */
#define MCHP_I2C_RSHT(ba) REG8_OFS(ba, MCHP_I2C_RSHT_OFS)
/* Completion register */
#define MCHP_I2C_CMPL(ba) REG32_OFS(ba, MCHP_I2C_CMPL_OFS)
/* access only bits[7:0] R/W timeout enables */
#define MCHP_I2C_CMPL_B0(ba) REG8_OFS(ba, MCHP_I2C_CMPL_OFS)
/* Idle Scaling register */
#define MCHP_I2C_IDLSC(ba) REG32_OFS(ba, MCHP_I2C_IDLSC_OFS)
/* Configuration register */
#define MCHP_I2C_CFG(ba) REG32_OFS(ba, MCHP_I2C_CFG_OFS)
/* access each byte */
#define MCHP_I2C_CFG_B0(ba) REG8_OFS(ba, (MCHP_I2C_CFG_OFS + 0x00ul))
#define MCHP_I2C_CFG_B1(ba) REG8_OFS(ba, (MCHP_I2C_CFG_OFS + 0x01ul))
#define MCHP_I2C_CFG_B2(ba) REG8_OFS(ba, (MCHP_I2C_CFG_OFS + 0x02ul))
#define MCHP_I2C_CFG_B3(ba) REG8_OFS(ba, (MCHP_I2C_CFG_OFS + 0x03ul))
/* Bus Clock register */
#define MCHP_I2C_BUS_CLK(ba) REG32_OFS(ba, MCHP_I2C_BUS_CLK_OFS)
#define MCHP_I2C_BUS_CLK_LO_PERIOD(ba) \
REG8_OFS(ba, (MCHP_I2C_BUS_CLK_OFS + 0x00ul))
#define MCHP_I2C_BUS_CLK_HI_PERIOD(ba) \
REG8_OFS(ba, (MCHP_I2C_BUS_CLK_OFS + 0x01ul))
/* Bit-Bang Control register */
#define MCHP_I2C_BB_CTRL(ba) REG8_OFS(ba, MCHP_I2C_BB_OFS)
/* MCHP Reserved 0x3C register */
#define MCHP_I2C_RSVD_3C(ba) REG8_OFS(ba, MCHP_I2C_RSVD_3C)
/* Data Timing register */
#define MCHP_I2C_DATA_TM(ba) REG32_OFS(ba, MCHP_I2C_DATA_TM_OFS)
/* Timeout Scaling register */
#define MCHP_I2C_TMTSC(ba) REG32_OFS(ba, MCHP_I2C_TMTSC_OFS)
/* Wake Status register */
#define MCHP_I2C_WAKE_STS(ba) REG8_OFS(ba, MCHP_I2C_WAKE_STS_OFS)
/* Wake Enable register */
#define MCHP_I2C_WAKE_ENABLE(ba) REG8_OFS(ba, MCHP_I2C_WAKE_EN_OFS)
/* Captured Slave Address */
#define MCHP_I2C_SLV_ADDR(ba) REG8_OFS(ba, MCHP_I2C_SLV_ADDR_OFS)
/* Promiscuous Interrupt Status */
#define MCHP_I2C_PROM_ISTS(ba) REG8_OFS(ba, MCHP_I2C_PROM_INTR_STS_OFS)
/* Promiscuous Interrupt Enable */
#define MCHP_I2C_PROM_IEN(ba) REG8_OFS(ba, MCHP_I2C_PROM_INTR_EN_OFS)
/* Promiscuous Interrupt Control */
#define MCHP_I2C_PROM_CTLR(ba) REG8_OFS(ba, MCHP_I2C_PROM_CTRL_OFS)
/* =========================================================================*/
/* ================ SMB ================ */
/* =========================================================================*/
/**
* @brief SMBus Network Layer Block (SMB)
*/
typedef struct i2c_regs
{ /*!< (@ 0x40004000) SMB Structure */
__IOM uint8_t CTRLSTS; /*!< (@ 0x00000000) I2C Status(RO), Control(WO) */
uint8_t RSVD1[3];
__IOM uint32_t OWN_ADDR; /*!< (@ 0x00000004) I2C Own address */
__IOM uint8_t I2CDATA; /*!< (@ 0x00000008) I2C I2C Data */
uint8_t RSVD2[15];
__IOM uint8_t RSHTM; /*!< (@ 0x00000018) I2C Repeated-Start hold time */
uint8_t RSVD3[7];
__IOM uint32_t COMPL; /*!< (@ 0x00000020) I2C Completion */
uint8_t RSVD4[4];
__IOM uint32_t CFG; /*!< (@ 0x00000028) I2C Configuration */
__IOM uint32_t BUSCLK; /*!< (@ 0x0000002C) I2C Bus Clock */
__IOM uint8_t BLKID; /*!< (@ 0x00000030) I2C Block ID */
uint8_t RSVD5[3];
__IOM uint8_t BLKREV; /*!< (@ 0x00000034) I2C Block revision */
uint8_t RSVD6[3];
__IOM uint8_t BBCTRL; /*!< (@ 0x00000038) I2C Bit-Bang control */
uint8_t RSVD7[7];
__IOM uint32_t DATATM; /*!< (@ 0x00000040) I2C Data timing */
__IOM uint32_t TMOUTSC; /*!< (@ 0x00000044) I2C Time-out scaling */
uint8_t RSVD8[0x60u - 0x48u];
__IOM uint8_t WAKE_STS; /*!< (@ 0x00000060) I2C Wake status */
uint8_t RSVD9[3];
__IOM uint8_t WAKE_EN; /*!< (@ 0x00000064) I2C Wake enable */
uint8_t RSVD10[4];
__IOM uint8_t SLV_ADDR; /*!< (@ 0x0000006C) I2C Slave Address */
uint8_t RSVD11[3];
__IOM uint8_t PROM_INTR_STS; /*!< (@ 0x00000070) I2C Promiscuous Interrupt Status */
uint8_t RSVD12[3];
__IOM uint8_t PROM_INTR_EN; /*!< (@ 0x00000074) I2C Promiscuous Interrupt Enable */
uint8_t RSVD13[3];
__IOM uint8_t PROM_CTRL; /*!< (@ 0x00000078) I2C Promiscuous Interrupt Enable */
uint8_t RSVD14[3];
} I2C_Type;
#endif // #ifndef _I2C_H
/* end i2c.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file kbc.h
*MEC1501 EM8042 Keyboard Controller Registers
*/
/** @defgroup MEC1501 Peripherals KBC
*/
#ifndef _KBC_H
#define _KBC_H
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
/* =========================================================================*/
/* ================ KBC ================ */
/* =========================================================================*/
#define MCHP_KBC_BASE_ADDR 0x400F0400ul
/*
* KBC interrupts
*/
#define MCHP_KBC_GIRQ 15u
#define MCHP_KBC_GIRQ_NVIC 7u
#define MCHP_KBC_OBE_NVIC_DIRECT 58u
#define MCHP_KBC_IBF_NVIC_DIRECT 59u
#define MCHP_KBC_OBE_GIRQ_POS 18u
#define MCHP_KBC_IBF_GIRQ_POS 19u
#define MCHP_KBC_OBE_GIRQ (1ul << 18)
#define MCHP_KBC_IBF_GIRQ (1ul << 19)
/*
* EC_KBC_STS and KBC_STS_RD bit definitions
*/
#define MCHP_KBC_STS_OBF_POS 0u
#define MCHP_KBC_STS_OBF (1ul << (MCHP_KBC_STS_OBF_POS))
#define MCHP_KBC_STS_IBF_POS 1u
#define MCHP_KBC_STS_IBF (1ul << (MCHP_KBC_STS_IBF_POS))
#define MCHP_KBC_STS_UD0_POS 2u
#define MCHP_KBC_STS_UD0 (1ul << (MCHP_KBC_STS_UD0_POS))
#define MCHP_KBC_STS_CD_POS 3u
#define MCHP_KBC_STS_CD (1ul << (MCHP_KBC_STS_CD_POS))
#define MCHP_KBC_STS_UD1_POS 4u
#define MCHP_KBC_STS_UD1 (1ul << (MCHP_KBC_STS_UD1_POS))
#define MCHP_KBC_STS_AUXOBF_POS 5u
#define MCHP_KBC_STS_AUXOBF (1ul << (MCHP_KBC_STS_AUXOBF_POS))
#define MCHP_KBC_STS_UD2_POS 6u
#define MCHP_KBC_STS_UD2_MASK0 0x03ul
#define MCHP_KBC_STS_UD2_MASK (0x03ul << 6)
#define MCHP_KBC_STS_UD2_0_POS 6u
#define MCHP_KBC_STS_UD2_0 (1ul << 6)
#define MCHP_KBC_STS_UD2_1 (1ul << 7)
/*
* KBC_CTRL bit definitions
*/
#define MCHP_KBC_CTRL_UD3_POS 0u
#define MCHP_KBC_CTRL_UD3 (1ul << (MCHP_KBC_CTRL_UD3_POS))
#define MCHP_KBC_CTRL_SAEN_POS 1u
#define MCHP_KBC_CTRL_SAEN (1ul << (MCHP_KBC_CTRL_SAEN_POS))
#define MCHP_KBC_CTRL_PCOBFEN_POS 2u
#define MCHP_KBC_CTRL_PCOBFEN (1ul << (MCHP_KBC_CTRL_PCOBFEN_POS))
#define MCHP_KBC_CTRL_UD4_POS 3u
#define MCHP_KBC_CTRL_UD4_MASK0 0x03ul
#define MCHP_KBC_CTRL_UD4_MASK (0x03ul << (MCHP_KBC_CTRL_UD4_POS))
#define MCHP_KBC_CTRL_OBFEN_POS 5u
#define MCHP_KBC_CTRL_OBFEN (1ul << (MCHP_KBC_CTRL_OBFEN_POS))
#define MCHP_KBC_CTRL_UD5_POS 6u
#define MCHP_KBC_CTRL_UD5 (1ul << (MCHP_KBC_CTRL_UD5_POS))
#define MCHP_KBC_CTRL_AUXH_POS 7u
#define MCHP_KBC_CTRL_AUXH (1ul << (MCHP_KBC_CTRL_AUXH_POS))
/*
* PCOBF register bit definitions
*/
#define MCHP_KBC_PCOBF_EN_POS 0u
#define MCHP_KBC_PCOBF_EN (1ul << (MCHP_KBC_PCOBF_EN_POS))
/*
* KBC_PORT92_EN register bit definitions
*/
#define MCHP_KBC_PORT92_EN_POS 0u
#define MCHP_KBC_PORT92_EN (1ul << (MCHP_KBC_PORT92_EN_POS))
/**
* @brief Keyboard Controller Registers (KBC)
*/
typedef struct kbc_regs
{
__IOM uint32_t HOST_AUX_DATA; /*!< (@ 0x0000) EC_HOST and AUX Data register */
__IOM uint32_t KBC_STS_RD; /*!< (@ 0x0004) Keyboard Status Read register */
uint8_t RSVD1[0x100u - 0x08u];
__IOM uint32_t EC_DATA; /*!< (@ 0x0100) EC Data */
__IOM uint32_t EC_KBC_STS; /*!< (@ 0x0104) EC KBC Status */
__IOM uint32_t KBC_CTRL; /*!< (@ 0x0108) KBC Control */
__IOM uint32_t EC_AUX_DATA; /*!< (@ 0x010C) EC Aux Data */
uint32_t RSVD2[1];
__IOM uint32_t PCOBF; /*!< (@ 0x0114) PCOBF register */
uint8_t RSVD3[0x0330ul - 0x0118ul];
__IOM uint32_t KBC_PORT92_EN; /*!< (@ 0x0330) Port92h enable */
} KBC_Type;
#endif /* #ifndef _KBC_H */
/* end kbc.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file keyscan.h
*MEC1501 Keyboard matrix scan controller registers
*/
/** @defgroup MEC1501 Peripherals KSCAN
*/
#ifndef _KSCAN_H
#define _KSCAN_H
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
/* =========================================================================*/
/* ================ KBC ================ */
/* =========================================================================*/
#define MCHP_KSCAN_BASE_ADDR 0x40009C00ul
/*
* KSCAN interrupts
*/
#define MCHP_KSCAN_GIRQ 21u
#define MCHP_KSCAN_GIRQ_NVIC 13u
/* Direct mode connection to NVIC */
#define MCHP_KSAN_NVIC 135u
#define MCHP_KSCAN_GIRQ_POS 25u
#define MCHP_KSCAN_GIRQ_VAL (1ul << 25)
/*
* KSO_SEL
*/
#define MCHP_KSCAN_KSO_SEL_REG_MASK 0xFFul
#define MCHP_KSCAN_KSO_LINES_POS 0u
#define MCHP_KSCAN_KSO_LINES_MASK0 0x1Ful
#define MCHP_KSCAN_KSO_LINES_MASK 0x1Ful
#define MCHP_KSCAN_KSO_ALL_POS 5u
#define MCHP_KSCAN_KSO_ALL (1ul << 5)
#define MCHP_KSCAN_KSO_EN_POS 6u
#define MCHP_KSCAN_KSO_EN (1ul << 6)
#define MCHP_KSCAN_KSO_INV_POS 7u
#define MCHP_KSCAN_KSO_INV (1ul << 7)
/*
* KSI_IN
*/
#define MCHP_KSCAN_KSI_IN_REG_MASK 0xFFul
/*
* KSI_STS
*/
#define MCHP_KSCAN_KSI_STS_REG_MASK 0xFFul
/*
* KSI_IEN
*/
#define MCHP_KSCAN_KSI_IEN_REG_MASK 0xFFul
/*
* EXT_CTRL
*/
#define MCHP_KSCAN_EXT_CTRL_REG_MASK 0x01ul
#define MCHP_KSCAN_EXT_CTRL_PREDRV_EN 0x01ul
/**
* @brief Keyboard Controller Registers (KSCAN)
*/
typedef struct kscan_regs
{
uint8_t RSVD[4];
__IOM uint32_t KSO_SEL; /*!< (@ 0x0004) KSO Select */
uint32_t KSI_IN; /*!< (@ 0x0008) KSI Input States */
__IOM uint32_t KSI_STS; /*!< (@ 0x000C) KSI Status */
__IOM uint32_t KSI_IEN; /*!< (@ 0x0010) KSI Interrupt Enable */
__IOM uint32_t EXT_CTRL; /*!< (@ 0x0014) Extended Control */
} KSCAN_Type;
#endif /* #ifndef _KSCAN_H */
/* end kscan.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file led.h
*MEC1501 Breathing-Blinking LED definitions
*/
/** @defgroup MEC1501 Peripherals LED
*/
#ifndef _LED_H
#define _LED_H
#define MCHP_LED_NUM_BLOCKS 3u
#define MCHP_LED_CFG_OFS 0x00ul
#define MCHP_LED_LIMITS_OFS 0x04ul
#define MCHP_LED_DELAY_OFS 0x08ul
#define MCHP_LED_UPD_STEP_OFS 0x0Cul
#define MCHP_LED_UPD_INTRVL_OFS 0x10ul
#define MCHP_LED_OUTPUT_DLY_OFS 0x14ul
/*
* LED Configuration Register
*/
#define MCHP_LED_CFG_CNTL_MASK 0x0003u
#define MCHP_LED_CFG_CNTL_LO 0x0000u
#define MCHP_LED_CFG_CNTL_BREATH 0x0001u
#define MCHP_LED_CFG_CNTL_BLINK 0x0002u
#define MCHP_LED_CFG_CNTL_HI 0x0003u
#define MCHP_LED_CFG_CLK_SRC_MCLK 0x0002u
#define MCHP_LED_CFG_CLK_SRC_32K 0x0000u
#define MCHP_LED_CFG_SYNC 0x0008u
#define MCHP_LED_CFG_PWM_COUNT_WIDTH_MASK 0x0030u
#define MCHP_LED_CFG_COUNT_WIDTH_8 0x0000u
#define MCHP_LED_CFG_COUNT_WIDTH_7 0x0010u
#define MCHP_LED_CFG_COUNT_WIDTH_6 0x0020u
#define MCHP_LED_CFG_EN_UPDATE 0x0040u
#define MCHP_LED_CFG_RESET 0x0080u
#define MCHP_LED_CFG_WDT_PRELOAD_MASK 0xFF00u
#define MCHP_LED_CFG_WDT_PRELOAD_POR 0x1400u
#define MCHP_LED_CFG_SYMMETRY_EN 0x10000u
/*
* LED Limit Register
*/
#define MCHP_LED_LIM_MIN_POS 0u
#define MCHP_LED_LIM_MIN_MASK 0xFFu
#define MCHP_LED_LIM_MAX_POS 8u
#define MCHP_LED_LIM_MAX_MASK 0xFF00ul
/*
* LED Delay Register
*/
#define MCHP_LED_DLY_LO_MASK 0x0000FFFul
#define MCHP_LED_DLY_HI_MASK 0x0FFF000ul
#define MCHP_LED_DLY_HI_POS 12u
/*
* LED Step Size Register
*/
#define MCHP_LED_STEP_FIELD_WIDTH 4u
#define MCHP_LED_STEP_MASK0 0x0Ful
#define MCHP_LED_STEP0_POS 0u
#define MCHP_LED_STEP0_MASK 0x0000000Ful
#define MCHP_LED_STEP1_POS 4u
#define MCHP_LED_STEP1_MASK 0x000000F0ul
#define MCHP_LED_STEP2_POS 8u
#define MCHP_LED_STEP2_MASK 0x00000F00ul
#define MCHP_LED_STEP3_POS 12u
#define MCHP_LED_STEP3_MASK 0x0000F000ul
#define MCHP_LED_STEP4_POS 16u
#define MCHP_LED_STEP4_MASK 0x000F0000ul
#define MCHP_LED_STEP5_POS 20u
#define MCHP_LED_STEP5_MASK 0x00F00000ul
#define MCHP_LED_STEP6_POS 24u
#define MCHP_LED_STEP6_MASK 0x0F000000ul
#define MCHP_LED_STEP7_POS 28u
#define MCHP_LED_STEP7_MASK 0xF0000000ul
/*
* LED Update Register
*/
#define MCHP_LED_UPDT_FIELD_WIDTH 4u
#define MCHP_LED_UPDT_MASK0 0x0Ful;
#define MCHP_LED_UPDT0_POS 0u
#define MCHP_LED_UPDT0_MASK 0x0000000Ful
#define MCHP_LED_UPDT1_POS 4u
#define MCHP_LED_UPDT1_MASK 0x000000F0ul
#define MCHP_LED_UPDT2_POS 8u
#define MCHP_LED_UPDT2_MASK 0x00000F00ul
#define MCHP_LED_UPDT3_POS 12u
#define MCHP_LED_UPDT3_MASK 0x0000F000ul
#define MCHP_LED_UPDT4_POS 16u
#define MCHP_LED_UPDT4_MASK 0x000F0000ul
#define MCHP_LED_UPDT5_POS 20u
#define MCHP_LED_UPDT5_MASK 0x00F00000ul
#define MCHP_LED_UPDT6_POS 24u
#define MCHP_LED_UPDT6_MASK 0x0F000000ul
#define MCHP_LED_UPDT7_POS 28u
#define MCHP_LED_UPDT7_MASK 0xF0000000ul
#define MCHP_BLINK_0P5_HZ_DUTY_CYCLE 0x010ul
#define MCHP_BLINK_0P5_HZ_PRESCALE 0x0FFul
#define MCHP_BLINK_1_HZ_DUTY_CYCLE 0x020ul
#define MCHP_BLINK_1_HZ_PRESCALE 0x07Ful
/* =======================================================================*/
/* ================ LED ================ */
/* =======================================================================*/
#define MCHP_LED_MAX_INSTANCES 4u
#define MCHP_LED_SPACING 0x100ul
#define MCHP_LED_SPACING_PWROF2 8u
#define MCHP_LED_BASE_ADDR 0x4000B800ul
#define MCHP_LED0_ADDR 0x4000B800ul
#define MCHP_LED1_ADDR 0x4000B900ul
#define MCHP_LED2_ADDR 0x4000BA00ul
#define MCHP_LED3_ADDR 0x4000BB00ul
#define MCHP_LED_ADDR(n) \
(MCHP_LED_BASE_ADDR + ((uint32_t)(n) << MCHP_LED_SPACING_PWROF2))
/**
* @brief Breathing-Blinking LED (LED)
*/
typedef struct led_regs
{ /*!< (@ 0x4000B800) LED Structure */
__IOM uint32_t CFG; /*! (@ 0x00000000) LED configuration */
__IOM uint32_t LIMIT; /*! (@ 0x00000004) LED limits */
__IOM uint32_t DLY; /*! (@ 0x00000008) LED delay */
__IOM uint32_t STEP; /*! (@ 0x0000000C) LED update step size */
__IOM uint32_t INTRVL; /*! (@ 0x00000010) LED update interval */
__IOM uint32_t OUTDLY; /*! (@ 0x00000014) LED output delay */
} LED_Type;
#endif /* #ifndef _LED_H */
/* end led.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file mailbox.h
*MEC1501 Mailbox Registers
*/
/** @defgroup MEC1501 Peripherals MBOX
*/
#ifndef _MAILBOX_H
#define _MAILBOX_H
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
/* =========================================================================*/
/* ================ MAILBOX ================ */
/* =========================================================================*/
#define MCHP_MBOX_BASE_ADDR 0x400F0000ul
/*
* KBC interrupts
*/
#define MCHP_MBOX_GIRQ 15u
#define MCHP_MBOX_GIRQ_NVIC 7u
#define MCHP_MBOX_NVIC_DIRECT 60u
#define MCHP_KBC_MBOX_GIRQ_POS 20u
#define MCHP_KBC_MBOX_GIRQ (1ul << 20u)
/*
* SMI Source register
*/
#define MCHP_MBOX_SMI_SRC_EC_WR_POS 0u
#define MCHP_MBOX_SMI_SRC_EC_WR (1ul << (MCHP_MBOX_SMI_SRC_WR_POS))
#define MCHP_MBOX_SMI_SRC_SWI_POS 1u
#define MCHP_MBOX_SMI_SRC_SWI_MASK0 0x7Ful
#define MCHP_MBOX_SMI_SRC_SWI_MASK 0xFEul
#define MCHP_MBOX_SMI_SRC_SWI0 (1ul << 1)
#define MCHP_MBOX_SMI_SRC_SWI1 (1ul << 2)
#define MCHP_MBOX_SMI_SRC_SWI2 (1ul << 3)
#define MCHP_MBOX_SMI_SRC_SWI3 (1ul << 4)
#define MCHP_MBOX_SMI_SRC_SWI4 (1ul << 5)
#define MCHP_MBOX_SMI_SRC_SWI5 (1ul << 6)
#define MCHP_MBOX_SMI_SRC_SWI6 (1ul << 7)
/*
* SMI Mask register
*/
#define MCHP_MBOX_SMI_MASK_WR_EN_POS 0u
#define MCHP_MBOX_SMI_MASK_WR_EN (1ul << (MCHP_MBOX_SMI_MASK_WR_EN_POS))
#define MCHP_MBOX_SMI_SWI_EN_POS 1u
#define MCHP_MBOX_SMI_SWI_EN_MASK0 0x7Ful
#define MCHP_MBOX_SMI_SWI_EN_MASK 0xFEul
#define MCHP_MBOX_SMI_SRC_EN_SWI0 (1ul << 1)
#define MCHP_MBOX_SMI_SRC_EN_SWI1 (1ul << 2)
#define MCHP_MBOX_SMI_SRC_EN_SWI2 (1ul << 3)
#define MCHP_MBOX_SMI_SRC_EN_SWI3 (1ul << 4)
#define MCHP_MBOX_SMI_SRC_EN_SWI4 (1ul << 5)
#define MCHP_MBOX_SMI_SRC_EN_SWI5 (1ul << 6)
#define MCHP_MBOX_SMI_SRC_EN_SWI6 (1ul << 7)
/**
* @brief Mailbox Registers (MBOX)
*/
typedef struct mbox_regs
{
__IOM uint8_t OS_IDX; /*!< (@ 0x0000) OS Index */
__IOM uint8_t OS_DATA; /*!< (@ 0x0001) OS Data */
uint8_t RSVD1[0x100u - 0x02u];
__IOM uint32_t HOST_TO_EC; /*!< (@ 0x0100) Host to EC */
__IOM uint32_t EC_TO_HOST; /*!< (@ 0x0104) EC to Host */
__IOM uint32_t SMI_SRC; /*!< (@ 0x0108) SMI Source */
__IOM uint32_t SMI_MASK; /*!< (@ 0x010C) SMI Mask */
__IOM uint32_t MBX_0_3; /*!< (@ 0x0110) Mailboxes 0 - 3 */
__IOM uint32_t MBX_4_7; /*!< (@ 0x0114) Mailboxes 4 - 7 */
__IOM uint32_t MBX_8_11; /*!< (@ 0x0118) Mailboxes 8 - 11 */
__IOM uint32_t MBX_12_15; /*!< (@ 0x011C) Mailboxes 12 - 15 */
__IOM uint32_t MBX_16_19; /*!< (@ 0x0120) Mailboxes 16 - 19 */
__IOM uint32_t MBX_20_23; /*!< (@ 0x0124) Mailboxes 20 - 23 */
__IOM uint32_t MBX_24_27; /*!< (@ 0x0128) Mailboxes 24 - 27 */
__IOM uint32_t MBX_28_31; /*!< (@ 0x012C) Mailboxes 28 - 31 */
} MBOX_Type;
#endif /* #ifndef _MAILBOX_H */
/* end mailbox.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file pcr.h
*MEC1501 Power Control Reset definitions
*/
/** @defgroup MEC1501 Peripherals PCR
*/
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
#ifndef _PCR_H
#define _PCR_H
#define MCHP_PCR_BASE_ADDR 0x40080100ul
#define MCHP_PCR_SYS_SLP_CTRL_OFS 0x00ul
#define MCHP_PCR_SYS_CLK_CTRL_OFS 0x04ul
#define MCHP_PCR_SLOW_CLK_CTRL_OFS 0x08ul
#define MCHP_PCR_OSC_ID_OFS 0x0Cul
#define MCHP_PCR_PRS_OFS 0x10ul
#define MCHP_PCR_PR_CTRL_OFS 0x14ul
#define MCHP_PCR_SYS_RESET_OFS 0x18ul
#define MCHP_PCR_PKE_CLK_CTRL_OFS 0x1Cul
#define MCHP_PCR_SLP_EN0_OFS 0x30ul
#define MCHP_PCR_SLP_EN1_OFS 0x34ul
#define MCHP_PCR_SLP_EN2_OFS 0x38ul
#define MCHP_PCR_SLP_EN3_OFS 0x3Cul
#define MCHP_PCR_SLP_EN4_OFS 0x40ul
#define MCHP_PCR_CLK_REQ0_OFS 0x50ul
#define MCHP_PCR_CLK_REQ1_OFS 0x54ul
#define MCHP_PCR_CLK_REQ2_OFS 0x58ul
#define MCHP_PCR_CLK_REQ3_OFS 0x5Cul
#define MCHP_PCR_CLK_REQ4_OFS 0x60ul
#define MCHP_PCR_PERIPH_RST0_OFS 0x70ul
#define MCHP_PCR_PERIPH_RST1_OFS 0x74ul
#define MCHP_PCR_PERIPH_RST2_OFS 0x78ul
#define MCHP_PCR_PERIPH_RST3_OFS 0x7Cul
#define MCHP_PCR_PERIPH_RST4_OFS 0x80ul
#define MCHP_PCR_PERIPH_RST_LCK_OFS 0x84ul
#define MCHP_PCR_SYS_SLP_CTRL_ADDR (MCHP_PCR_BASE_ADDR)
#define MCHP_PCR_SYS_CLK_CTRL_ADDR (MCHP_PCR_BASE_ADDR + 0x04ul)
#define MCHP_PCR_SLOW_CLK_CTRL_ADDR (MCHP_PCR_BASE_ADDR + 0x08ul)
#define MCHP_PCR_OSC_ID_ADDR (MCHP_PCR_BASE_ADDR + 0x0Cul)
#define MCHP_PCR_PRS_ADDR (MCHP_PCR_BASE_ADDR + 0x10ul)
#define MCHP_PCR_PR_CTRL_ADDR (MCHP_PCR_BASE_ADDR + 0x14ul)
#define MCHP_PCR_SYS_RESET_ADDR (MCHP_PCR_BASE_ADDR + 0x18ul)
#define MCHP_PCR_PKE_CLK_CTRL_ADDR (MCHP_PCR_BASE_ADDR + 0x1Cul)
#define MCHP_PCR_SLP_EN0_ADDR (MCHP_PCR_BASE_ADDR + 0x30ul)
#define MCHP_PCR_SLP_EN1_ADDR (MCHP_PCR_BASE_ADDR + 0x34ul)
#define MCHP_PCR_SLP_EN2_ADDR (MCHP_PCR_BASE_ADDR + 0x38ul)
#define MCHP_PCR_SLP_EN3_ADDR (MCHP_PCR_BASE_ADDR + 0x3Cul)
#define MCHP_PCR_SLP_EN4_ADDR (MCHP_PCR_BASE_ADDR + 0x40ul)
#define MCHP_PCR_CLK_REQ0_ADDR (MCHP_PCR_BASE_ADDR + 0x50ul)
#define MCHP_PCR_CLK_REQ1_ADDR (MCHP_PCR_BASE_ADDR + 0x54ul)
#define MCHP_PCR_CLK_REQ2_ADDR (MCHP_PCR_BASE_ADDR + 0x58ul)
#define MCHP_PCR_CLK_REQ3_ADDR (MCHP_PCR_BASE_ADDR + 0x5Cul)
#define MCHP_PCR_CLK_REQ4_ADDR (MCHP_PCR_BASE_ADDR + 0x60ul)
#define MCHP_PCR_PERIPH_RST0_ADDR (MCHP_PCR_BASE_ADDR + 0x70ul)
#define MCHP_PCR_PERIPH_RST1_ADDR (MCHP_PCR_BASE_ADDR + 0x74ul)
#define MCHP_PCR_PERIPH_RST2_ADDR (MCHP_PCR_BASE_ADDR + 0x78ul)
#define MCHP_PCR_PERIPH_RST3_ADDR (MCHP_PCR_BASE_ADDR + 0x7Cul)
#define MCHP_PCR_PERIPH_RST4_ADDR (MCHP_PCR_BASE_ADDR + 0x80ul)
#define MCHP_PCR_PERIPH_RESET_LOCK_ADDR (MCHP_PCR_BASE_ADDR + 0x84ul)
#define MCHP_PCR_SLP_EN_ADDR(n) \
(MCHP_PCR_BASE_ADDR + 0x30ul + ((uint32_t)(n) << 2))
#define MCHP_PCR_CLK_REQ_ADDR(n) \
(MCHP_PCR_BASE_ADDR + 0x50ul + ((uint32_t)(n) << 2))
#define MCHP_PCR_PERIPH_RESET_ADDR(n) \
(MCHP_PCR_BASE_ADDR + 0x70ul + ((uint32_t)(n) << 2))
#define MCHP_PCR_SLEEP_EN (1u)
#define MCHP_PCR_SLEEP_DIS (0u)
/*
* MEC1501 PCR implements multiple SLP_EN, CLR_REQ, and RST_EN registers.
* CLK_REQ bits are read-only. The peripheral sets its CLK_REQ if it requires
* clocks. CLK_REQ bits must all be zero for the PCR block to put the MEC17xx
* into light or heavy sleep.
* SLP_EN bit = 1 instructs HW to gate off clock tree to peripheral only if
* peripherals PCR CLK_REQ bit is 0.
* RST_EN bit = 1 will reset the peripheral at any time. The RST_EN registers
* must be unlocked by writing the unlock code to PCR Peripheral Reset Lock
* register.
* SLP_EN usage is:
* Initialization set all PCR SLP_EN bits = 0 except for crypto blocks as
* these IP do not implement internal clock gating.
* When firmware wants to enter light or heavy sleep.
* Configure wake up source(s)
* Write MCHP_PCR_SYS_SLP_CTR register to value based on light/heavy with
* SLEEP_ALL bit = 1.
* Execute Cortex-M4 WFI sequence. DSB(), ISB(), WFI(), NOP()
* Cortex-M4 will assert sleep signal to PCR block.
* PCR HW will spin until all CLK_REQ==0
* PCR will then turn off clocks based on light/heavy sleep.
*
* RST_EN usage is:
* Save and disable maskable interrupts
* Write unlock code to PCR Peripheral Reset Lock
* Write bit patterns to one or more of PCR RST_EN[0, 4] registers
* Selected peripherals will be reset.
* Write lock code to PCR Peripheral Reset Lock.
* Restore interrupts.
*/
#define MCHP_MAX_PCR_SCR_REGS 5ul
/*
* VTR Powered PCR registers
*/
#define MCHP_PCR_SLP(bitpos) (1ul << (bitpos))
/*
* PCR System Sleep Control
*/
#define MCHP_PCR_SYS_SLP_CTRL_MASK 0x0109ul
#define MCHP_PCR_SYS_SLP_CTRL_SLP_LIGHT (0ul << 0)
#define MCHP_PCR_SYS_SLP_CTRL_SLP_HEAVY (1ul << 0)
#define MCHP_PCR_SYS_SLP_CTRL_SLP_ALL (1ul << 3)
/*
* bit[8] can be used to prevent entry to heavy sleep unless the
* PLL is locked.
* bit[8]==0 (POR default) system will allow entry to light or heavy
* sleep if and only if PLL is locked.
* bit[8]==1 system will allow entry to heavy sleep before PLL is locked.
*/
#define MCHP_PCR_SYS_SLP_CTRL_SLP_PLL_LOCK (0ul << 8)
#define MCHP_PCR_SYS_SLP_CTRL_ALLOW_SLP_NO_PLL_LOCK (0ul << 8)
#define MCHP_PCR_SYS_SLP_LIGHT 0x08ul
#define MCHP_PCR_SYS_SLP_HEAVY 0x09ul
/*
* PCR Process Clock Control
* Divides 48MHz clock to ARM Cortex-M4 core including
* SysTick and NVIC.
*/
#define MCHP_PCR_PROC_CLK_CTRL_MASK 0xFFul
#define MCHP_PCR_PROC_CLK_CTRL_48MHZ 0x01ul
#define MCHP_PCR_PROC_CLK_CTRL_16MHZ 0x03ul
#define MCHP_PCR_PROC_CLK_CTRL_12MHZ 0x04ul
#define MCHP_PCR_PROC_CLK_CTRL_4MHZ 0x10ul
#define MCHP_PCR_PROC_CLK_CTRL_1MHZ 0x30ul
/*
* PCR Slow Clock Control
* Clock divicder for 100KHz clock domain
*/
#define MCHP_PCR_SLOW_CLK_CTRL_MASK 0x3FFul
#define MCHP_PCR_SLOW_CLK_CTRL_100KHZ 0x1E0ul
/*
* PCR Oscillator ID register (Read-Only)
*/
#define MCHP_PCR_OSC_ID_MASK 0x1FFul
#define MCHP_PCR_OSC_ID_PLL_LOCK (1ul << 8)
/*
* PCR Power Reset Status Register
*/
#define MCHP_PCR_PRS_MASK 0xCECul
#define MCHP_PCR_PRS_VCC_PWRGD_STATE_RO (1ul << 2)
#define MCHP_PCR_PRS_HOST_RESET_STATE_RO (1ul << 3)
#define MCHP_PCR_PRS_VBAT_RST_RWC (1ul << 5)
#define MCHP_PCR_PRS_VTR_RST_RWC (1ul << 6)
#define MCHP_PCR_PRS_JTAG_RST_RWC (1ul << 7)
#define MCHP_PCR_PRS_32K_ACTIVE_RO (1ul << 10)
#define MCHP_PCR_PRS_LPC_ESPI_CLK_ACTIVE_RO (1ul << 11)
/*
* PCR Power Reset Control Register
*/
#define MCHP_PCR_PR_CTRL_MASK 0x101ul
#define MCHP_PCR_PR_CTRL_PWR_INV (1ul << 0)
#define MCHP_PCR_PR_CTRL_USE_ESPI_PLTRST (0ul << 8)
#define MCHP_PCR_PR_CTRL_USE_PCI_RST (1ul << 8)
/*
* PCR System Reset Register
*/
#define MCHP_PCR_SYS_RESET_MASK 0x100ul
#define MCHP_PCR_SYS_RESET_NOW (1ul << 8)
/*
* PCR PKE Clock Register
*/
#define MCHP_PCR_PKE_CLK_CTRL_MASK 0x03ul
#define MCHP_PCR_PKE_CLK_CTRL_96M 0x00ul
#define MCHP_PCR_PKE_CLK_CTRL_48M 0x03ul
/*
* Sleep Enable Reg 0 (Offset +30h)
* Clock Required Reg 0 (Offset +50h)
* Reset Enable Reg 3 (Offset +70h)
*/
#define MCHP_PCR0_JTAG_STAP_POS 0u
/*
* Sleep Enable Reg 1 (Offset +34h)
* Clock Required Reg 1 (Offset +54h)
* Reset Enable Reg 1 (Offset +74h)
*/
#define MCHP_PCR1_ECIA_POS 0u
#define MCHP_PCR1_PECI_POS 1u
#define MCHP_PCR1_TACH0_POS 2u
#define MCHP_PCR1_PWM0_POS 4u
#define MCHP_PCR1_PMC_POS 5u
#define MCHP_PCR1_DMA_POS 6u
#define MCHP_PCR1_TFDP_POS 7u
#define MCHP_PCR1_CPU_POS 8u
#define MCHP_PCR1_WDT_POS 9u
#define MCHP_PCR1_SMB0_POS 10u
#define MCHP_PCR1_TACH1_POS 11u
#define MCHP_PCR1_TACH2_POS 12u
#define MCHP_PCR1_TACH3_POS 13u
#define MCHP_PCR1_PWM1_POS 20u
#define MCHP_PCR1_PWM2_POS 21u
#define MCHP_PCR1_PWM3_POS 22u
#define MCHP_PCR1_PWM4_POS 23u
#define MCHP_PCR1_PWM5_POS 24u
#define MCHP_PCR1_PWM6_POS 25u
#define MCHP_PCR1_PWM7_POS 26u
#define MCHP_PCR1_PWM8_POS 27u
#define MCHP_PCR1_ECS_POS 29u
#define MCHP_PCR1_B16TMR0_POS 30u
#define MCHP_PCR1_B16TMR1_POS 31u
/*
* Sleep Enable Reg 2 (Offset +38h)
* Clock Required Reg 2 (Offset +58h)
* Reset Enable Reg 2 (Offset +78h)
*/
#define MCHP_PCR2_EMI0_POS 0u
#define MCHP_PCR2_UART0_POS 1u
#define MCHP_PCR2_UART1_POS 2u
#define MCHP_PCR2_GCFG_POS 12u
#define MCHP_PCR2_ACPI_EC0_POS 13u
#define MCHP_PCR2_ACPI_EC1_POS 14u
#define MCHP_PCR2_ACPI_PM1_POS 15u
#define MCHP_PCR2_KBC_POS 16u
#define MCHP_PCR2_MBOX_POS 17u
#define MCHP_PCR2_RTC_POS 18u
#define MCHP_PCR2_ESPI_POS 19u
#define MCHP_PCR2_SCR32_POS 20u
#define MCHP_PCR2_ACPI_EC2_POS 21u
#define MCHP_PCR2_ACPI_EC3_POS 22u
#define MCHP_PCR2_PORT80CAP0_POS 25u
#define MCHP_PCR2_PORT80CAP1_POS 26u
#define MCHP_PCR2_ESPI_SAF_POS 27u
#define MCHP_PCR2_UART2_POS 28u
/*
* Sleep Enable Reg 3 (Offset +3Ch)
* Clock Required Reg 3 (Offset +5Ch)
* Reset Enable Reg 3 (Offset +7Ch)
*/
#define MCHP_PCR3_HDMI_CEC_POS 1u
#define MCHP_PCR3_ADC_POS 3u
#define MCHP_PCR3_PS2_0_POS 5u
#define MCHP_PCR3_PS2_1_POS 6u
#define MCHP_PCR3_HTMR0_POS 10u
#define MCHP_PCR3_KEYSCAN_POS 11u
#define MCHP_PCR3_SMB1_POS 13u
#define MCHP_PCR3_SMB2_POS 14u
#define MCHP_PCR3_SMB3_POS 15u
#define MCHP_PCR3_LED0_POS 16u
#define MCHP_PCR3_LED1_POS 17u
#define MCHP_PCR3_LED2_POS 18u
#define MCHP_PCR3_SMB4_POS 20u
#define MCHP_PCR3_B32TMR0_POS 23u
#define MCHP_PCR3_B32TMR1_POS 24u
#define MCHP_PCR3_PKE_POS 26u
#define MCHP_PCR3_RNG_POS 27u
#define MCHP_PCR3_AESH_POS 28u
#define MCHP_PCR3_HTMR1_POS 29u
#define MCHP_PCR3_CCT_POS 30u
#define MCHP_PCR3_CRYPTO_MASK \
((1ul << (MCHP_PCR3_PKE_POS)) +\
(1ul << (MCHP_PCR3_RNG_POS)) + (1ul << (MCHP_PCR3_AESH_POS)))
/*
* Sleep Enable Reg 4 (Offset +40h)
* Clock Required Reg 4 (Offset +60h)
* Reset Enable Reg 4 (Offset +80h)
*/
#define MCHP_PCR4_RTMR_POS 6u
#define MCHP_PCR4_QMSPI_POS 8u
#define MCHP_PCR4_I2C0_POS 10u
#define MCHP_PCR4_I2C1_POS 11u
#define MCHP_PCR4_I2C3_POS 12u
#define MCHP_PCR4_SPISLV_POS 16u
/* Reset Enable Lock (Offset +84h) */
#define MCHP_PCR_RSTEN_UNLOCK 0xA6382D4Cul
#define MCHP_PCR_RSTEN_LOCK 0xA6382D4Dul
/*
* PCR register access
*/
#define MCHP_PCR_SLP_CTRL() REG32(MCHP_PCR_SYS_SLP_CTRL_ADDR)
#define MCHP_PCR_PROC_CLK_DIV() REG8(MCHP_PCR_SYS_CLK_CTRL_ADDR)
#define MCHP_PCR_SLOW_CLK_CTRL() REG32(MCHP_PCR_SLOW_CLK_CTRL_ADDR)
#define MCHP_PCR_OSC_ID() REG32(MCHP_PCR_OSC_ID_ADDR)
#define MCHP_PCR_PRS() REG32(MCHP_PCR_PRS_ADDR)
#define MCHP_PCR_PR_CTRL() REG32(MCHP_PCR_PR_CTRL_ADDR)
#define MCHP_PCR_SYS_RESET() REG32(MCHP_PCR_SYS_RESET_ADDR)
#define MCHP_PCR_PERIPH_RST_LOCK() \
REG32(MCHP_PCR_PERIPH_RESET_LOCK_ADDR)
#define MCHP_PCR_SLP_EN(n) REG32(MCHP_PCR_SLP_EN_ADDR(n))
#define MCHP_PCR_CLK_REQ_RO(n) REG32(MCHP_PCR_CLK_REQ_ADDR(n))
#define MCHP_PCR_SLP_EN0() REG32(MCHP_PCR_SLP_EN_ADDR(0))
#define MCHP_PCR_SLP_EN1() REG32(MCHP_PCR_SLP_EN_ADDR(1))
#define MCHP_PCR_SLP_EN2() REG32(MCHP_PCR_SLP_EN_ADDR(2))
#define MCHP_PCR_SLP_EN3() REG32(MCHP_PCR_SLP_EN_ADDR(3))
#define MCHP_PCR_SLP_EN4() REG32(MCHP_PCR_SLP_EN_ADDR(4))
#define MCHP_PCR_CLK_REQ0_RO() REG32(MCHP_PCR_CLK_REQ_ADDR(0))
#define MCHP_PCR_CLK_REQ1_RO() REG32(MCHP_PCR_CLK_REQ_ADDR(1))
#define MCHP_PCR_CLK_REQ2_RO() REG32(MCHP_PCR_CLK_REQ_ADDR(2))
#define MCHP_PCR_CLK_REQ3_RO() REG32(MCHP_PCR_CLK_REQ_ADDR(3))
#define MCHP_PCR_CLK_REQ4_RO() REG32(MCHP_PCR_CLK_REQ_ADDR(4))
#define MCHP_PCR_PERIPH_RST(n) REG32(MCHP_PCR_PERIPH_RESET_ADDR(n))
#define MCHP_PCR_DEV_SLP_EN_CLR(n, b) \
REG32(MCHP_PCR_SLP_EN_ADDR(n)) &= ~(1ul << (uint32_t)(b))
#define MCHP_PCR_DEV_SLP_EN_SET(n, b) \
REG32(MCHP_PCR_SLP_EN_ADDR(n)) |= (1ul << (uint32_t)(b))
/*
* PCR SleepEn/CLK_REQ/ResetOnSleep register offset from
* SlpEn0/CLK_REQ0/ResetOnSleep0 registers in b[7:5]
* Bit position in register = b[4:0]
*/
typedef enum pcr_id {
PCR_STAP = 0u,
PCR_OTP = 1u,
PCR_ECIA = (128u + 0u), /* 4 << 5 = 128 */
PCR_PECI = (128u + 1u),
PCR_TACH0 = (128u + 2u),
PCR_PWM0 = (128u + 4u),
PCR_PMC = (128u + 5u),
PCR_DMA = (128u + 6u),
PCR_TFDP = (128u + 7u),
PCR_CPU = (128u + 8u),
PCR_WDT = (128u + 9u),
PCR_SMB0 = (128u + 10u),
PCR_TACH1 = (128u + 11u),
PCR_TACH2 = (128u + 12u),
PCR_TACH3 = (128u + 13u),
PCR_PWM1 = (128u + 20u),
PCR_PWM2 = (128u + 21u),
PCR_PWM3 = (128u + 22u),
PCR_PWM4 = (128u + 23u),
PCR_PWM5 = (128u + 24u),
PCR_PWM6 = (128u + 25u),
PCR_PWM7 = (128u + 26u),
PCR_PWM8 = (128u + 27u),
PCR_ECS = (128u + 29u),
PCR_B16TMR0 = (128u + 30u),
PCR_B16TMR1 = (128u + 31u),
PCR_EMI0 = (256u + 0u), /* 8 << 5 = 256 */
PCR_UART0 = (256u + 1u),
PCR_UART1 = (256u + 2u),
PCR_GCFG = (256u + 12u),
PCR_ACPI_EC0 = (256u + 13u),
PCR_ACPI_EC1 = (256u + 14u),
PCR_ACPI_PM1 = (256u + 15u),
PCR_KBC = (256u + 16u),
PCR_MBOX = (256u + 17u),
PCR_RTC = (256u + 18u),
PCR_ESPI = (256u + 19u),
PCR_SCR32 = (256u + 20u),
PCR_ACPI_EC2 = (256u + 21u),
PCR_ACPI_EC3 = (256u + 22u),
PCR_P80CAP0 = (256u + 25u),
PCR_P80CAP1 = (256u + 26u),
PCR_ESPI_SAF = (256u + 27u),
PCR_UART2 = (256u + 28u),
PCR_HDMI_CEC = (384u + 1u), /* 12 << 5 = 384 */
PCR_ADC = (384u + 3u),
PCR_PS2_0 = (384u + 5u),
PCR_PS2_1 = (384u + 6u),
PCR_HTMR0 = (384u + 10u),
PCR_KEYSCAN = (384u + 11u),
PCR_SMB1 = (384u + 13u),
PCR_SMB2 = (384u + 14u),
PCR_SMB3 = (384u + 15u),
PCR_LED0 = (384u + 16u),
PCR_LED1 = (384u + 17u),
PCR_LED2 = (384u + 18u),
PCR_SMB4 = (384u + 20u),
PCR_B32TMR0 = (384u + 23u),
PCR_B32TMR1 = (384u + 24u),
PCR_PKE = (384u + 26u),
PCR_NDRNG = (384u + 27u),
PCR_AESH = (384u + 28u),
PCR_HTMR1 = (384u + 29u),
PCR_CCT = (384u + 30u),
PCR_RTMR = (512u + 6u), /* 16 << 5 = 512 */
PCR_QMSPI = (512u + 8u),
PCR_I2C0 = (512u + 10u),
PCR_I2C1 = (512u + 11u),
PCR_I2C2 = (512u + 12u),
PCR_SPISLV = (512u + 16u),
PCR_MAX_ID,
} PCR_ID;
/* =====================================================================*/
/* ================ PCR ================ */
/* =====================================================================*/
/**
* @brief Power Control Reset (PCR)
*/
typedef struct pcr_regs
{ /*!< (@ 0x40080100) PCR Structure */
__IOM uint32_t SYS_SLP_CTRL; /*!< (@ 0x0000) System Sleep Control */
__IOM uint32_t PROC_CLK_CTRL; /*!< (@ 0x0004) Processor Clock Control */
__IOM uint32_t SLOW_CLK_CTRL; /*!< (@ 0x0008) Slow Clock Control */
__IOM uint32_t OSC_ID; /*!< (@ 0x000C) Processor Clock Control */
__IOM uint32_t PWR_RST_STS; /*!< (@ 0x0010) Power Reset Status */
__IOM uint32_t PWR_RST_CTRL; /*!< (@ 0x0014) Power Reset Control */
__IOM uint32_t SYS_RST; /*!< (@ 0x0018) System Reset */
__IOM uint32_t TEST1C;
__IOM uint32_t TEST20;
uint8_t RSVD1[12];
__IOM uint32_t SLP_EN0; /*!< (@ 0x0030) Sleep Enable 0 */
__IOM uint32_t SLP_EN1; /*!< (@ 0x0034) Sleep Enable 1 */
__IOM uint32_t SLP_EN2; /*!< (@ 0x0038) Sleep Enable 2 */
__IOM uint32_t SLP_EN3; /*!< (@ 0x003C) Sleep Enable 3 */
__IOM uint32_t SLP_EN4; /*!< (@ 0x0040) Sleep Enable 4 */
uint8_t RSVD2[12];
__IOM uint32_t CLK_REQ0; /*!< (@ 0x0050) Clock Required 0 (RO) */
__IOM uint32_t CLK_REQ1; /*!< (@ 0x0054) Clock Required 1 (RO) */
__IOM uint32_t CLK_REQ2; /*!< (@ 0x0058) Clock Required 2 (RO) */
__IOM uint32_t CLK_REQ3; /*!< (@ 0x005C) Clock Required 3 (RO) */
__IOM uint32_t CLK_REQ4; /*!< (@ 0x0060) Clock Required 4 (RO) */
uint8_t RSVD3[12];
__IOM uint32_t RST_EN0; /*!< (@ 0x0070) Peripheral Reset 0 */
__IOM uint32_t RST_EN1; /*!< (@ 0x0074) Peripheral Reset 1 */
__IOM uint32_t RST_EN2; /*!< (@ 0x0078) Peripheral Reset 2 */
__IOM uint32_t RST_EN3; /*!< (@ 0x007C) Peripheral Reset 3 */
__IOM uint32_t RST_EN4; /*!< (@ 0x0080) Peripheral Reset 4 */
__IOM uint32_t RST_EN_LOCK; /*!< (@ 0x0084) Peripheral Lock */
} PCR_Type;
static __attribute__ ((always_inline)) inline void
mchp_pcr_periph_slp_ctrl(PCR_ID pcr_id, uint8_t enable)
{
uintptr_t raddr = (uintptr_t) (MCHP_PCR_SLP_EN0_ADDR);
uint32_t bitpos = (uint32_t) pcr_id & 0x1F;
raddr += ((uint32_t) pcr_id >> 5);
if (enable) {
REG32(raddr) |= (1ul << bitpos);
} else {
REG32(raddr) &= ~(1ul << bitpos);
}
}
#endif // #ifndef _DEFS_H
/* end pcr.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file port92.h
*MEC1501 Fast Port92h Registers
*/
/** @defgroup MEC1501 Peripherals Fast Port92
*/
#ifndef _PORT92_H
#define _PORT92_H
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
/* =========================================================================*/
/* ================ PORT92 ================ */
/* =========================================================================*/
#define MCHP_PORT92_BASE_ADDR 0x400F2000ul
/*
* HOST_P92
*/
#define MCHP_PORT92_HOST_MASK 0x03ul
#define MCHP_PORT92_HOST_ALT_CPU_RST_POS 0u
#define MCHP_PORT92_HOST_ALT_CPU_RST (1ul << 0)
#define MCHP_PORT92_HOST_ALT_GA20_POS 1u
#define MCHP_PORT92_HOST_ALT_GA20 (1ul << 1)
/*
* GATEA20_CTRL
*/
#define MCHP_PORT92_GA20_CTRL_MASK 0x01ul
#define MCHP_PORT92_GA20_CTRL_VAL_POS 0u
#define MCHP_PORT92_GA20_CTRL_VAL_MASK (1ul << 0)
#define MCHP_PORT92_GA20_CTRL_VAL_HI (1ul << 0)
#define MCHP_PORT92_GA20_CTRL_VAL_LO (0ul << 0)
/*
* SETGA20L - writes of any data to this register causes
* GATEA20 latch to be set.
*/
#define MCHP_PORT92_SETGA20L_MASK 0x01ul
#define MCHP_PORT92_SETGA20L_SET_POS 0u
#define MCHP_PORT92_SETGA20L_SET (1ul << 0)
/*
* RSTGA20L - writes of any data to this register causes
* the GATEA20 latch to be reset
*/
#define MCHP_PORT92_RSTGA20L_MASK 0x01ul
#define MCHP_PORT92_RSTGA20L_SET_POS 0u
#define MCHP_PORT92_RSTGA20L_RST (1ul << 0)
/*
* ACTV
*/
#define MCHP_PORT92_ACTV_MASK 0x01ul
#define MCHP_PORT92_ACTV_ENABLE 0x01ul
/**
* @brief Fast Port92h Registers (PORT92)
*/
typedef struct port92_regs
{
__IOM uint32_t HOST_P92; /*!< (@ 0x0000) HOST Port92h register */
uint8_t RSVD1[0x100u - 0x04u];
__IOM uint32_t GATEA20_CTRL; /*!< (@ 0x0100) Gate A20 Control */
uint8_t RSVD2[4];
__IOM uint32_t SETGA20L; /*!< (@ 0x0108) Set Gate A20 */
__IOM uint32_t RSTGA20L; /*!< (@ 0x010C) Reset Gate A20 */
uint8_t RSVD3[0x0330ul - 0x0110ul];
__IOM uint32_t ACTV; /*!< (@ 0x0330) Logical device Activate */
} PORT92_Type;
#endif /* #ifndef _PORT92_H */
/* end port92.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file qmspi.h
*MEC1501 Quad Master SPI Registers
*/
/** @defgroup MEC1501 Peripherals QMSPI
*/
#ifndef _QMSPI_H_
#define _QMSPI_H_
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
#define QMPSPI_HW_VER 3u
#define MCHP_QMSPI_BASE_ADDR 0x40070000ul
#define MCHP_QMSPI_MAX_DESCR 16ul
#define MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ 48000000ul
#define MCHP_QMSPI_MAX_FREQ_KHZ ((MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ) / 1000ul)
#define MCHP_QMSPI_MIN_FREQ_KHZ (MCHP_QMSPI_MAX_FREQ_KHZ / 256ul)
#define MCHP_QMSPI_GIRQ_NUM 18u
#define MCHP_QMSPI_GIRQ_POS 1u
#define MCHP_QMSPI_GIRQ_OFS (((MCHP_QMSPI0_GIRQ_NUM) - 8) * 20u)
#define MCHP_QMSPI_GIRQ_BASE_ADDR 0x4000E0C8ul
/* Sleep Enable 4 bit 8 */
#define MCHP_QMSPI_PCR_SLP_EN_ADDR 0x40080140ul
#define MCHP_QMSPI_PCR_SLP_EN_BITPOS 8u
#define MCHP_QMSPI_GIRQ_SRC_ADDR (MCHP_QMSPI_GIRQ_BASE_ADDR)
#define MCHP_QMSPI_GIRQ_ENSET_ADDR (MCHP_QMSPI_GIRQ_BASE_ADDR + 0x04ul)
#define MCHP_QMSPI_GIRQ_RESULT_ADDR (MCHP_QMSPI_GIRQ_BASE_ADDR + 0x08ul)
#define MCHP_QMSPI_GIRQ_ENCLR_ADDR (MCHP_QMSPI_GIRQ_BASE_ADDR + 0x0Cul)
#define MCHP_QMSPI_GIRQ_EN (1ul << (MCHP_QMSPI_GIRQ_POS))
#define MCHP_QMSPI_GIRQ_STS (1ul << (MCHP_QMSPI_GIRQ_POS))
/* Mode 0: Clock idle = Low. Data changes on falling edge, sample on rising edge */
#define MCHP_QMSPI_SPI_MODE0 0ul
/* Mode 1: Clock idle = Low. Data changes on rising edge, sample on falling edge */
#define MCHP_QMSPI_SPI_MODE1 0x06ul
/* Mode 2: Clock idle = High. Data changes on rising edge, sample on falling edge */
#define MCHP_QMSPI_SPI_MODE2 0x06ul
/* Mode 3: Clock idle = High. Data changes on falling edge, sample on rising edge */
#define MCHP_QMSPI_SPI_MODE3 0x07ul
/* Device ID used in DMA channel Control.DeviceID field */
#define MCHP_QMSPI_TX_DMA_REQ_ID 10ul
#define MCHP_QMSPI_RX_DMA_REQ_ID 11ul
/* QMSPI transmit and receive FIFO lengths */
#define MCHP_QMSPI_TX_FIFO_LEN 8ul
#define MCHP_QMSPI_RX_FIFO_LEN 8ul
#define MCHP_QMSPI_M_ACT_SRST_OFS 0ul
#define MCHP_QMSPI_M_SPI_MODE_OFS 1ul
#define MCHP_QMSPI_M_CLK_DIV_OFS 2ul
#define MCHP_QMSPI_CTRL_OFS 4ul
#define MCHP_QMSPI_EXE_OFS 8ul
#define MCHP_QMSPI_IF_CTRL_OFS 0x0Cul
#define MCHP_QMSPI_STS_OFS 0x10ul
#define MCHP_QMSPI_BUF_CNT_STS_OFS 0x14ul
#define MCHP_QMSPI_IEN_OFS 0x18ul
#define MCHP_QMSPI_BUF_CNT_TRIG_OFS 0x1Cul
#define MCHP_QMSPI_TX_FIFO_OFS 0x20ul
#define MCHP_QMSPI_RX_FIFO_OFS 0x24ul
#define MCHP_QMSPI_CSTM_OFS 0x28ul
/* 0 <= n < MCHP_QMSPI_MAX_DESCR */
#define MCHP_QMSPI_DESCR_OFS(n) (0x30ul + ((uint32_t)(n) << 2))
#define MCHP_QMSPI_DESC0_OFS 0x30ul
#define MCHP_QMSPI_MODE_ADDR (MCHP_QMSPI_BASE_ADDR + 0x00)
#define MCHP_QMSPI_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x04)
#define MCHP_QMSPI_EXE_ADDR (MCHP_QMSPI_BASE_ADDR + 0x08)
#define MCHP_QMSPI_IFC_ADDR (MCHP_QMSPI_BASE_ADDR + 0x0C)
#define MCHP_QMSPI_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x10)
#define MCHP_QMSPI_BUFCNT_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x14)
#define MCHP_QMSPI_TX_BCNT_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x14)
#define MCHP_QMSPI_RX_BCNT_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x16)
#define MCHP_QMSPI_IEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x18)
#define MCHP_QMSPI_TXB_ADDR (MCHP_QMSPI_BASE_ADDR + 0x20)
#define MCHP_QMSPI_RXB_ADDR (MCHP_QMSPI_BASE_ADDR + 0x24)
#define MCHP_QMSPI_CSTM_ADDR (MCHP_QMSPI_BASE_ADDR + 0x28)
#define MCHP_QMSPI_DESCR_ADDR(n) \
(MCHP_QMSPI_BASE_ADDR + (0x30 + ((uint32_t)(n) << 2)))
/* Mode Register */
#define MCHP_QMSPI_M_SRST 0x02ul
#define MCHP_QMSPI_M_ACTIVATE 0x01ul
#define MCHP_QMSPI_M_SIG_POS 8u
#define MCHP_QMSPI_M_SIG_MASK0 0x07ul
#define MCHP_QMSPI_M_SIG_MASK 0x0700ul
#define MCHP_QMSPI_M_SIG_MODE0_VAL 0x00ul
#define MCHP_QMSPI_M_SIG_MODE1_VAL 0x06ul
#define MCHP_QMSPI_M_SIG_MODE2_VAL 0x01ul
#define MCHP_QMSPI_M_SIG_MODE3_VAL 0x07ul
#define MCHP_QMSPI_M_SIG_MODE0 (0x00ul << MCHP_QMSPI_M_SIG_POS)
#define MCHP_QMSPI_M_SIG_MODE1 (0x06ul << MCHP_QMSPI_M_SIG_POS)
#define MCHP_QMSPI_M_SIG_MODE2 (0x01ul << MCHP_QMSPI_M_SIG_POS)
#define MCHP_QMSPI_M_SIG_MODE3 (0x07ul << MCHP_QMSPI_M_SIG_POS)
#define MCHP_QMSPI_M_CS_POS 12u
#define MCHP_QMSPI_M_CS_MASK0 0x03ul
#define MCHP_QMSPI_M_CS_MASK (0x03ul << 12)
#define MCHP_QMSPI_M_CS0 (0x00ul << 12)
#define MCHP_QMSPI_M_CS1 (0x01ul << 12)
/* Two chip selects only 0 and 1 */
#define MCHP_QMSPI_M_CS(n) \
(((uint32_t)(n) & MCHP_QMSPI_M_CS_MASK0) << MCHP_QMSPI_M_CS_POS)
#define MCHP_QMSPI_M_FDIV_POS 16u
#define MCHP_QMSPI_M_FDIV_MASK0 0xFFul
#define MCHP_QMSPI_M_FDIV_MASK 0x00FF0000ul
/* Control/Descriptors */
#define MCHP_QMSPI_C_IFM_MASK 0x03ul
#define MCHP_QMSPI_C_IFM_1X 0x00ul
#define MCHP_QMSPI_C_IFM_2X 0x01ul
#define MCHP_QMSPI_C_IFM_4X 0x02ul
#define MCHP_QMSPI_C_TX_MASK (0x03ul << 2)
#define MCHP_QMSPI_C_TX_DIS (0x00ul << 2)
#define MCHP_QMSPI_C_TX_DATA (0x01ul << 2)
#define MCHP_QMSPI_C_TX_ZEROS (0x02ul << 2)
#define MCHP_QMSPI_C_TX_ONES (0x03ul << 2)
#define MCHP_QMSPI_C_TX_DMA_POS 4u
#define MCHP_QMSPI_C_TX_DMA_MASK (0x03ul << 4)
#define MCHP_QMSPI_C_TX_DMA_DIS (0x00ul << 4)
#define MCHP_QMSPI_C_TX_DMA_1B (0x01ul << 4)
#define MCHP_QMSPI_C_TX_DMA_2B (0x02ul << 4)
#define MCHP_QMSPI_C_TX_DMA_4B (0x03ul << 4)
#define MCHP_QMSPI_C_RX_DIS (0ul << 6)
#define MCHP_QMSPI_C_RX_EN (1ul << 6)
#define MCHP_QMSPI_C_RX_DMA_POS 7u
#define MCHP_QMSPI_C_RX_DMA_MASK (0x03ul << 7)
#define MCHP_QMSPI_C_RX_DMA_DIS (0x00ul << 7)
#define MCHP_QMSPI_C_RX_DMA_1B (0x01ul << 7)
#define MCHP_QMSPI_C_RX_DMA_2B (0x02ul << 7)
#define MCHP_QMSPI_C_RX_DMA_4B (0x03ul << 7)
#define MCHP_QMSPI_C_NO_CLOSE (0ul << 9)
#define MCHP_QMSPI_C_CLOSE (1ul << 9)
#define MCHP_QMSPI_C_XFR_UNITS_POS 10u
#define MCHP_QMSPI_C_XFR_UNITS_MASK (0x03ul << 10)
#define MCHP_QMSPI_C_XFR_UNITS_BITS (0x00ul << 10)
#define MCHP_QMSPI_C_XFR_UNITS_1 (0x01ul << 10)
#define MCHP_QMSPI_C_XFR_UNITS_4 (0x02ul << 10)
#define MCHP_QMSPI_C_XFR_UNITS_16 (0x03ul << 10)
#define MCHP_QMSPI_C_NEXT_DESCR_POS 12u
#define MCHP_QMSPI_C_NEXT_DESCR_MASK0 0x0Ful
#define MCHP_QMSPI_C_NEXT_DESCR_MASK (0x0Ful << 12)
#define MCHP_QMSPI_C_DESCR0 (0ul << 12)
#define MCHP_QMSPI_C_DESCR1 (1ul << 12)
#define MCHP_QMSPI_C_DESCR2 (2ul << 12)
#define MCHP_QMSPI_C_DESCR3 (3ul << 12)
#define MCHP_QMSPI_C_DESCR4 (4ul << 12)
/* Control register start descriptor field */
#define MCHP_QMSPI_C_DESCR(n) \
(((uint32_t)(n) & 0x0f) << 12)
/* Descriptor registers next descriptor field */
#define MCHP_QMSPI_C_NEXT_DESCR(n) \
(((uint32_t)(n) & 0x0f) << 12)
/* Control register descriptor mode enable */
#define MCHP_QMSPI_C_DESCR_EN_POS 16u
#define MCHP_QMSPI_C_DESCR_EN (1ul << 16)
/* Descriptor registers last descriptor flag */
#define MCHP_QMSPI_C_DESCR_LAST (1ul << 16)
#define MCHP_QMSPI_C_MAX_UNITS 0x7FFFul
#define MCHP_QMSPI_C_MAX_UNITS_MASK 0x7FFFul
#define MCHP_QMSPI_C_XFR_NUNITS_POS 17u
#define MCHP_QMSPI_C_XFR_NUNITS_MASK0 0x7FFFul
#define MCHP_QMSPI_C_XFR_NUNITS_MASK (0x7FFFul << 17)
#define MCHP_QMSPI_C_XFR_NUNITS(n) ((uint32_t)(n) << 17)
#define MCHP_QMSPI_C_XFR_NUNITS_GET(n) \
(((uint32_t)(n) >> 17) & MCHP_QMSPI_C_MAX_UNITS_MASK)
/* Exe */
#define MCHP_QMSPI_EXE_START 0x01ul
#define MCHP_QMSPI_EXE_STOP 0x02ul
#define MCHP_QMSPI_EXE_CLR_FIFOS 0x04ul
/* Interface Control */
#define MCHP_QMSPI_IFC_DFLT 0x00ul
/* Status Register */
#define MCHP_QMSPI_STS_REG_MASK 0x0F01FF1Ful
#define MCHP_QMSPI_STS_RO_MASK 0x0F013300ul
#define MCHP_QMSPI_STS_RW1C_MASK 0x0000CC1Ful
#define MCHP_QMSPI_STS_DONE (1ul << 0)
#define MCHP_QMSPI_STS_DMA_DONE (1ul << 1)
#define MCHP_QMSPI_STS_TXB_ERR (1ul << 2)
#define MCHP_QMSPI_STS_RXB_ERR (1ul << 3)
#define MCHP_QMSPI_STS_PROG_ERR (1ul << 4)
#define MCHP_QMSPI_STS_TXBF_RO (1ul << 8)
#define MCHP_QMSPI_STS_TXBE_RO (1ul << 9)
#define MCHP_QMSPI_STS_TXBR (1ul << 10)
#define MCHP_QMSPI_STS_TXBS (1ul << 11)
#define MCHP_QMSPI_STS_RXBF_RO (1ul << 12)
#define MCHP_QMSPI_STS_RXBE_RO (1ul << 13)
#define MCHP_QMSPI_STS_RXBR (1ul << 14)
#define MCHP_QMSPI_STS_RXBS (1ul << 15)
#define MCHP_QMSPI_STS_ACTIVE_RO (1ul << 16)
#define MCHP_QMSPI_STS_CD_POS 24u
#define MCHP_QMSPI_STS_CD_MASK0 0x0Ful
#define MCHP_QMSPI_STS_CD_MASK (0x0Ful << 24)
/* Buffer Count Status (RO) */
#define MCHP_QMSPI_TX_BUF_CNT_STS_POS 0u
#define MCHP_QMSPI_RX_BUF_CNT_STS_POS 16u
/* Interrupt Enable Register */
#define MCHP_QMSPI_IEN_XFR_DONE (1ul << 0)
#define MCHP_QMSPI_IEN_DMA_DONE (1ul << 1)
#define MCHP_QMSPI_IEN_TXB_ERR (1ul << 2)
#define MCHP_QMSPI_IEN_RXB_ERR (1ul << 3)
#define MCHP_QMSPI_IEN_PROG_ERR (1ul << 4)
#define MCHP_QMSPI_IEN_TXB_FULL (1ul << 8)
#define MCHP_QMSPI_IEN_TXB_EMPTY (1ul << 9)
#define MCHP_QMSPI_IEN_TXB_REQ (1ul << 10)
#define MCHP_QMSPI_IEN_RXB_FULL (1ul << 12)
#define MCHP_QMSPI_IEN_RXB_EMPTY (1ul << 13)
#define MCHP_QMSPI_IEN_RXB_REQ (1ul << 14)
/* Buffer Count Trigger (RW) */
#define MCHP_QMSPI_TX_BUF_CNT_TRIG_POS 0u
#define MCHP_QMSPI_RX_BUF_CNT_TRIG_POS 16u
/* Chip Select Timing (RW) */
#define MCHP_QMSPI_CSTM_MASK 0xFF0F0F0Ful
#define MCHP_QMSPI_CSTM_DFLT 0x06060406ul
#define MCHP_QMSPI_DLY_CS_ON_CK_STR_POS 0u
#define MCHP_QMSPI_DLY_CS_ON_CK_STR_MASK 0x0Ful
#define MCHP_QMSPI_DLY_CK_STP_CS_OFF_POS 8u
#define MCHP_QMSPI_DLY_CK_STP_CS_OFF_MASK (0x0Ful << 8)
#define MCHP_QMSPI_DLY_LST_DAT_HLD_POS 16u
#define MCHP_QMSPI_DLY_LST_DAT_HLD_MASK (0x0Ful << 16)
#define MCHP_QMSPI_DLY_CS_OFF_CS_ON_POS 24u
#define MCHP_QMSPI_DLY_CS_OFF_CS_ON_MASK (0x0Ful << 24)
#define MCHP_QMSPI_PORT_MAX_IO_PINS 4u
#define MCHP_QMSPI_PORT_MAX_CS 2u
/* Full duplex and Dual I/O:
* CS#, CLK, IO0(MOSI), IO1(MISO)
* do not connect IO2(WP#) or IO3(HOLD#) to MCHP_QMSPI.
*/
#define MCHP_QMSPI_PORT_MASK_FULL_DUPLEX 0x0Ful
#define MCHP_QMSPI_PORT_MASK_DUAL 0x0Ful
#define MCHP_QMSPI_PIN_IO0_POS 0u
#define MCHP_QMSPI_PIN_IO1_POS 1u
#define MCHP_QMSPI_PIN_IO2_POS 2u
#define MCHP_QMSPI_PIN_IO3_POS 3u
#define MCHP_QMSPI_PIN_CLK_POS 4u
#define MCHP_QMSPI_PIN_CS0_POS 8u
#define MCHP_QMSPI_PIN_CS1_POS 9u
#define MCHP_QMSPI_PIN_IO0 (1ul << MCHP_QMSPI_PIN_IO0_POS)
#define MCHP_QMSPI_PIN_IO1 (1ul << MCHP_QMSPI_PIN_IO1_POS)
#define MCHP_QMSPI_PIN_IO2 (1ul << MCHP_QMSPI_PIN_IO2_POS)
#define MCHP_QMSPI_PIN_IO3 (1ul << MCHP_QMSPI_PIN_IO3_POS)
#define MCHP_QMSPI_PIN_CLK (1ul << MCHP_QMSPI_PIN_CLK_POS)
#define MCHP_QMSPI_PIN_CS0 (1ul << MCHP_QMSPI_PIN_CS0_POS)
#define MCHP_QMSPI_PIN_CS1 (1ul << MCHP_QMSPI_PIN_CS1_POS)
/*
* Register Access
*/
#define MCHP_QMSPI_MODE() REG32(MCHP_QMSPI_MODE_ADDR)
#define MCHP_QMSPI_MODE_ACTRST() REG8(MCHP_QMSPI_MODE_ADDR)
#define MCHP_QMSPI_MODE_SIG() REG8(MCHP_QMSPI_MODE_ADDR + 1ul)
#define MCHP_QMSPI_MODE_FDIV() REG16(MCHP_QMSPI_MODE_ADDR + 2ul)
/* Control register */
#define MCHP_QMSPI_CTRL() REG32(MCHP_QMSPI_CTRL_ADDR)
/* Execute register */
#define MCHP_QMSPI_EXE() REG8(MCHP_QMSPI_EXE_ADDR)
/* Interface Control register */
#define MCHP_QMSPI_IFC() REG8(MCHP_QMSPI_IFC_ADDR)
/* Status register */
#define MCHP_QMSPI_STS() REG32(MCHP_QMSPI_STS_ADDR)
/* Buffer Count Status register (read-only) */
#define MCHP_QMSPI_BCNT_STS() REG32(MCHP_QMSPI_BUFCNT_STS_ADDR)
/* b[15:0] = TX buffer count */
#define MCHP_QMSPI_BCNT_TX_STS() REG16(MCHP_QMSPI_BUFCNT_STS_ADDR)
/* b[31:15] = RX buffer count */
#define MCHP_QMSPI_BCNT_RX_STS() REG16(MCHP_QMSPI_BUFCNT_STS_ADDR + 2ul)
/* Interrupt Enable register */
#define MCHP_QMSPI_IEN() REG32(MCHP_QMSPI_IEN_ADDR)
/* TX FIFO write-only */
#define MCHP_QMSPI_TXB_32() REG32(MCHP_QMSPI_TXB_ADDR)
#define MCHP_QMSPI_TXB_16() REG16(MCHP_QMSPI_TXB_ADDR)
#define MCHP_QMSPI_TXB_8() REG8(MCHP_QMSPI_TXB_ADDR)
/* RX FIFO read-only */
#define MCHP_QMSPI_RXB_32() REG32(MCHP_QMSPI_RXB_ADDR)
#define MCHP_QMSPI_RXB_16() REG16(MCHP_QMSPI_RXB_ADDR)
#define MCHP_QMSPI_RXB_8() REG8(MCHP_QMSPI_RXB_ADDR)
/*
* Descriptor registers
* 0 <= id < MCHP_QMSPI_MAX_DESCR
*/
#define MCHP_QMSPI_DESCR(id) REG32(MCHP_QMSPI_DESCR_ADDR(id))
#define MCHP_QMSPI_DESCR0() REG32(MCHP_QMSPI_DESCR_ADDR(0))
#define MCHP_QMSPI_DESCR1() REG32(MCHP_QMSPI_DESCR_ADDR(1))
#define MCHP_QMSPI_DESCR2() REG32(MCHP_QMSPI_DESCR_ADDR(2))
#define MCHP_QMSPI_DESCR3() REG32(MCHP_QMSPI_DESCR_ADDR(3))
#define MCHP_QMSPI_DESCR4() REG32(MCHP_QMSPI_DESCR_ADDR(4))
#define MCHP_QMSPI_DESCR_NUNITS(id, nu) MCHP_QMSPI_DESCR(id) = \
((MCHP_QMSPI_DESCR(id) & ~(MCHP_QMSPI_C_XFR_NUNITS_MASK)) +\
(((uint32_t)nu & MCHP_QMSPI_C_XFR_NUNITS_MASK0) \
<< MCHP_QMSPI_C_XFR_NUNITS_POS))
/* =========================================================================*/
/* ================ QMSPI ================ */
/* =========================================================================*/
typedef struct {
__IOM uint32_t u32;
} QMSPI_DESCR_Type;
/**
* @brief Quad Master SPI (QMSPI)
*/
typedef struct qmspi_regs
{
__IOM uint32_t MODE; /*!< (@ 0x00000000) QMSPI Mode */
__IOM uint32_t CTRL; /*!< (@ 0x00000004) QMSPI Control */
__IOM uint32_t EXE; /*!< (@ 0x00000008) QMSPI Execute */
__IOM uint32_t IFCTRL; /*!< (@ 0x0000000C) QMSPI Interface control */
__IOM uint32_t STS; /*!< (@ 0x00000010) QMSPI Status */
__IOM uint32_t BCNT_STS; /*!< (@ 0x00000014) QMSPI Buffer Count Status (RO) */
__IOM uint32_t IEN; /*!< (@ 0x00000018) QMSPI Interrupt Enable */
__IOM uint32_t BCNT_TRIG; /*!< (@ 0x0000001C) QMSPI Buffer Count Trigger */
__IOM uint32_t TX_FIFO; /*!< (@ 0x00000020) QMSPI TX FIFO */
__IOM uint32_t RX_FIFO; /*!< (@ 0x00000024) QMSPI RX FIFO */
uint8_t RSVD1[8];
QMSPI_DESCR_Type DESCR[QMSPI_MAX_DESCR]; /*!< (@ 0x00000030) QMSPI Descriptors 0-4 */
} QMSPI_Type;
#endif /* #ifndef _QMSPI_H */
/* end qmspi.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file smb.h
*MEC1501 SMB register definitions
*/
/** @defgroup MEC1501 Peripherals SMB
*/
#ifndef _SMB_H
#define _SMB_H
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
#define MCHP_I2C_SMB_MAX_INSTANCES 4u
#define MCHP_I2C_SMB_INST_SPACING 0x400ul
#define MCHP_I2C_SMB_INST_SPACING_P2 10u
#define MCHP_I2C_SMB0_BASE_ADDR 0x40004000ul
#define MCHP_I2C_SMB1_BASE_ADDR 0x40004400ul
#define MCHP_I2C_SMB2_BASE_ADDR 0x40004800ul
#define MCHP_I2C_SMB3_BASE_ADDR 0x40004C00ul
#define MCHP_I2C_SMB4_BASE_ADDR 0x40005000ul
/* 0 <= n < MCHP_I2C_SMB_MAX_INSTANCES */
#define MCHP_I2C_SMB_BASE_ADDR(n) \
((MCHP_I2C_SMB0_BASE_ADDR) +\
(uint32_t)(n) << (MCHP_I2C_SMB_INST_SPACING_P2))
/*
* Offset 0x00
* Control and Status register
* Write to Control
* Read from Status
* Size 8-bit
*/
#define MCHP_I2C_SMB_CTRL_OFS 0x00ul
#define MCHP_I2C_SMB_CTRL_MASK 0xCFul
#define MCHP_I2C_SMB_CTRL_ACK (1ul << 0)
#define MCHP_I2C_SMB_CTRL_STO (1ul << 1)
#define MCHP_I2C_SMB_CTRL_STA (1ul << 2)
#define MCHP_I2C_SMB_CTRL_ENI (1ul << 3)
/* bits [5:4] reserved */
#define MCHP_I2C_SMB_CTRL_ESO (1ul << 6)
#define MCHP_I2C_SMB_CTRL_PIN (1ul << 7)
/* Status Read-only */
#define MCHP_I2C_SMB_STS_OFS 0x00ul
#define MCHP_I2C_SMB_STS_NBB (1ul << 0)
#define MCHP_I2C_SMB_STS_LAB (1ul << 1)
#define MCHP_I2C_SMB_STS_AAS (1ul << 2)
#define MCHP_I2C_SMB_STS_LRB_AD0 (1ul << 3)
#define MCHP_I2C_SMB_STS_BER (1ul << 4)
#define MCHP_I2C_SMB_STS_EXT_STOP (1ul << 5)
#define MCHP_I2C_SMB_STS_SAD (1ul << 6)
#define MCHP_I2C_SMB_STS_PIN (1ul << 7)
/*
* Offset 0x04
* Own Address b[7:0] = Slave address 1
* b[14:8] = Slave address 2
*/
#define MCHP_I2C_SMB_OWN_ADDR_OFS 0x04ul
#define MCHP_I2C_SMB_OWN_ADDR2_OFS 0x05ul
#define MCHP_I2C_SMB_OWN_ADDR_MASK 0x7F7Ful
/*
* Offset 0x08
* Data register, 8-bit
* Data to be shifted out or shifted in.
*/
#define MCHP_I2C_SMB_DATA_OFS 0x08ul
/*
* Offset 0x0C
* Master Command register
*/
#define MCHP_I2C_SMB_MSTR_CMD_OFS 0x0Cul
#define MCHP_I2C_SMB_MSTR_CMD_RD_CNT_OFS 0x0Ful /* byte 3 */
#define MCHP_I2C_SMB_MSTR_CMD_WR_CNT_OFS 0x0Eul /* byte 2 */
#define MCHP_I2C_SMB_MSTR_CMD_OP_OFS 0x0Dul /* byte 1 */
#define MCHP_I2C_SMB_MSTR_CMD_M_OFS 0x0Cul /* byte 0 */
#define MCHP_I2C_SMB_MSTR_CMD_MASK 0xFFFF3FF3ul
/* 32-bit definitions */
#define MCHP_I2C_SMB_MSTR_CMD_MRUN (1ul << 0)
#define MCHP_I2C_SMB_MSTR_CMD_MPROCEED (1ul << 1)
#define MCHP_I2C_SMB_MSTR_CMD_START0 (1ul << 8)
#define MCHP_I2C_SMB_MSTR_CMD_STARTN (1ul << 9)
#define MCHP_I2C_SMB_MSTR_CMD_STOP (1ul << 10)
#define MCHP_I2C_SMB_MSTR_CMD_PEC_TERM (1ul << 11)
#define MCHP_I2C_SMB_MSTR_CMD_READM (1ul << 12)
#define MCHP_I2C_SMB_MSTR_CMD_READ_PEC (1ul << 13)
#define MCHP_I2C_SMB_MSTR_CMD_RD_CNT_POS 24u
#define MCHP_I2C_SMB_MSTR_CMD_WR_CNT_POS 16u
/* byte 0 definitions */
#define MCHP_I2C_SMB_MSTR_CMD_B0_MRUN (1ul << 0)
#define MCHP_I2C_SMB_MSTR_CMD_B0_MPROCEED (1ul << 1)
/* byte 1 definitions */
#define MCHP_I2C_SMB_MSTR_CMD_B1_START0 (1ul << (8-8))
#define MCHP_I2C_SMB_MSTR_CMD_B1_STARTN (1ul << (9-8))
#define MCHP_I2C_SMB_MSTR_CMD_B1_STOP (1ul << (10-8))
#define MCHP_I2C_SMB_MSTR_CMD_B1_PEC_TERM (1ul << (11-8))
#define MCHP_I2C_SMB_MSTR_CMD_B1_READM (1ul << (12-8))
#define MCHP_I2C_SMB_MSTR_CMD_B1_READ_PEC (1ul << (13-8))
/*
* Offset 0x10
* Slave Command register
*/
#define MCHP_I2C_SMB_SLV_CMD_OFS 0x10ul
#define MCHP_I2C_SMB_SLV_CMD_MASK 0x00FFFF07ul
#define MCHP_I2C_SMB_SLV_CMD_SRUN (1ul << 0)
#define MCHP_I2C_SMB_SLV_CMD_SPROCEED (1ul << 1)
#define MCHP_I2C_SMB_SLV_CMD_SEND_PEC (1ul << 2)
#define MCHP_I2C_SMB_SLV_WR_CNT_POS 8u
#define MCHP_I2C_SMB_SLV_RD_CNT_POS 16u
/*
* Offset 0x14
* PEC CRC register, 8-bit read-write
*/
#define MCHP_I2C_SMB_PEC_CRC_OFS 0x14ul
/*
* Offset 0x18
* Repeated Start Hold Time register, 8-bit read-write
*/
#define MCHP_I2C_SMB_RSHT_OFS 0x18ul
/*
* Offset 0x20
* Complettion register, 32-bit
*/
#define MCHP_I2C_SMB_CMPL_OFS 0x20ul
#define MCHP_I2C_SMB_CMPL_MASK 0xE33B7F7Cul
#define MCHP_I2C_SMB_CMPL_RW1C_MASK 0xE1397F00ul
#define MCHP_I2C_SMB_CMPL_DTEN (1ul << 2)
#define MCHP_I2C_SMB_CMPL_MCEN (1ul << 3)
#define MCHP_I2C_SMB_CMPL_SCEN (1ul << 4)
#define MCHP_I2C_SMB_CMPL_BIDEN (1ul << 5)
#define MCHP_I2C_SMB_CMPL_TIMERR (1ul << 6)
#define MCHP_I2C_SMB_CMPL_DTO_RWC (1ul << 8)
#define MCHP_I2C_SMB_CMPL_MCTO_RWC (1ul << 9)
#define MCHP_I2C_SMB_CMPL_SCTO_RWC (1ul << 10)
#define MCHP_I2C_SMB_CMPL_CHDL_RWC (1ul << 11)
#define MCHP_I2C_SMB_CMPL_CHDH_RWC (1ul << 12)
#define MCHP_I2C_SMB_CMPL_BER_RWC (1ul << 13)
#define MCHP_I2C_SMB_CMPL_LAB_RWC (1ul << 14)
#define MCHP_I2C_SMB_CMPL_SNAKR_RWC (1ul << 16)
#define MCHP_I2C_SMB_CMPL_STR_RO (1ul << 17)
#define MCHP_I2C_SMB_CMPL_SPROT_RWC (1ul << 19)
#define MCHP_I2C_SMB_CMPL_RPT_RD_RWC (1ul << 20)
#define MCHP_I2C_SMB_CMPL_RPT_WR_RWC (1ul << 21)
#define MCHP_I2C_SMB_CMPL_MNAKX_RWC (1ul << 24)
#define MCHP_I2C_SMB_CMPL_MTR_RO (1ul << 25)
#define MCHP_I2C_SMB_CMPL_IDLE_RWC (1ul << 29)
#define MCHP_I2C_SMB_CMPL_MDONE_RWC (1ul << 30)
#define MCHP_I2C_SMB_CMPL_SDONE_RWC (1ul << 31)
/*
* Offset 0x24
* Idle Scaling register
*/
#define MCHP_I2C_SMB_IDLSC_OFS 0x24ul
#define MCHP_I2C_SMB_IDLSC_DLY_OFS 0x24ul
#define MCHP_I2C_SMB_IDLSC_BUS_OFS 0x26ul
#define MCHP_I2C_SMB_IDLSC_MASK 0x0FFF0FFFul
#define MCHP_I2C_SMB_IDLSC_BUS_MIN_POS 0u
#define MCHP_I2C_SMB_IDLSC_DLY_POS 16u
/*
* Offset 0x28
* Configure register
*/
#define MCHP_I2C_SMB_CFG_OFS 0x28ul
#define MCHP_I2C_SMB_CFG_MASK 0xF00F5FBFul
#define MCHP_I2C_SMB_CFG_PORT_SEL_MASK 0x0Ful
#define MCHP_I2C_SMB_CFG_TCEN (1ul << 4)
#define MCHP_I2C_SMB_CFG_SLOW_CLK (1ul << 5)
#define MCHP_I2C_SMB_CFG_PCEN (1ul << 7)
#define MCHP_I2C_SMB_CFG_FEN (1ul << 8)
#define MCHP_I2C_SMB_CFG_RESET (1ul << 9)
#define MCHP_I2C_SMB_CFG_ENAB (1ul << 10)
#define MCHP_I2C_SMB_CFG_DSA (1ul << 11)
#define MCHP_I2C_SMB_CFG_FAIR (1ul << 12)
#define MCHP_I2C_SMB_CFG_GC_EN (1ul << 14)
#define MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO (1ul << 16)
#define MCHP_I2C_SMB_CFG_FLUSH_SRBUF_WO (1ul << 17)
#define MCHP_I2C_SMB_CFG_FLUSH_MXBUF_WO (1ul << 18)
#define MCHP_I2C_SMB_CFG_FLUSH_MRBUF_WO (1ul << 19)
#define MCHP_I2C_SMB_CFG_EN_AAS (1ul << 28)
#define MCHP_I2C_SMB_CFG_ENIDI (1ul << 29)
#define MCHP_I2C_SMB_CFG_ENMI (1ul << 30)
#define MCHP_I2C_SMB_CFG_ENSI (1ul << 31)
/*
* Offset 0x2C
* Bus Clock register
*/
#define MCHP_I2C_SMB_BUS_CLK_OFS 0x2Cul
#define MCHP_I2C_SMB_BUS_CLK_MASK 0x0000FFFFul
#define MCHP_I2C_SMB_BUS_CLK_LO_POS 0u
#define MCHP_I2C_SMB_BUS_CLK_HI_POS 8u
/*
* Offset 0x30
* Block ID register, 8-bit read-only
*/
#define MCHP_I2C_SMB_BLOCK_ID_OFS 0x30ul
#define MCHP_I2C_SMB_BLOCK_ID_MASK 0xFFul
/*
* Offset 0x34
* Block Revision register, 8-bit read-only
*/
#define MCHP_I2C_SMB_BLOCK_REV_OFS 0x34ul
#define MCHP_I2C_SMB_BLOCK_REV_MASK 0xFFul
/*
* Offset 0x38
* Bit-Bang Control register, 8-bit read-write
*/
#define MCHP_I2C_SMB_BB_OFS 0x38ul
#define MCHP_I2C_SMB_BB_MASK 0x7Ful
#define MCHP_I2C_SMB_BB_EN (1u << 0)
#define MCHP_I2C_SMB_BB_SCL_DIR_IN (0u << 1)
#define MCHP_I2C_SMB_BB_SCL_DIR_OUT (1u << 1)
#define MCHP_I2C_SMB_BB_SDA_DIR_IN (0u << 2)
#define MCHP_I2C_SMB_BB_SDA_DIR_OUT (1u << 2)
#define MCHP_I2C_SMB_BB_CL (1u << 3)
#define MCHP_I2C_SMB_BB_DAT (1u << 4)
#define MCHP_I2C_SMB_BB_IN_POS 5u
#define MCHP_I2C_SMB_BB_IN_MASK0 0x03u
#define MCHP_I2C_SMB_BB_IN_MASK (0x03u << 5)
#define MCHP_I2C_SMB_BB_CLKI_RO (1u << 5)
#define MCHP_I2C_SMB_BB_DATI_RO (1u << 6)
/*
* Offset 0x40
* Data Timing register
*/
#define MCHP_I2C_SMB_DATA_TM_OFS 0x40ul
#define MCHP_I2C_SMB_DATA_TM_MASK 0xFFFFFFFFul
#define MCHP_I2C_SMB_DATA_TM_DATA_HOLD_POS 0u
#define MCHP_I2C_SMB_DATA_TM_DATA_HOLD_MASK 0xFFul
#define MCHP_I2C_SMB_DATA_TM_DATA_HOLD_MASK0 0xFFul
#define MCHP_I2C_SMB_DATA_TM_RESTART_POS 8u
#define MCHP_I2C_SMB_DATA_TM_RESTART_MASK 0xFF00ul
#define MCHP_I2C_SMB_DATA_TM_RESTART_MASK0 0xFFul
#define MCHP_I2C_SMB_DATA_TM_STOP_POS 16u
#define MCHP_I2C_SMB_DATA_TM_STOP_MASK 0xFF0000ul
#define MCHP_I2C_SMB_DATA_TM_STOP_MASK0 0xFFul
#define MCHP_I2C_SMB_DATA_TM_FSTART_POS 24u
#define MCHP_I2C_SMB_DATA_TM_FSTART_MASK 0xFF000000ul
#define MCHP_I2C_SMB_DATA_TM_FSTART_MASK0 0xFFul
/*
* Offset 0x44
* Time-out Scaling register
*/
#define MCHP_I2C_SMB_TMTSC_OFS 0x44ul
#define MCHP_I2C_SMB_TMTSC_MASK 0xFFFFFFFFul
#define MCHP_I2C_SMB_TMTSC_CLK_HI_POS 0u
#define MCHP_I2C_SMB_TMTSC_CLK_HI_MASK 0xFFul
#define MCHP_I2C_SMB_TMTSC_CLK_HI_MASK0 0xFFul
#define MCHP_I2C_SMB_TMTSC_SLV_POS 8u
#define MCHP_I2C_SMB_TMTSC_SLV_MASK 0xFF00ul
#define MCHP_I2C_SMB_TMTSC_SLV_MASK0 0xFFul
#define MCHP_I2C_SMB_TMTSC_MSTR_POS 16u
#define MCHP_I2C_SMB_TMTSC_MSTR_MASK 0xFF0000ul
#define MCHP_I2C_SMB_TMTSC_MSTR_MASK0 0xFFul
#define MCHP_I2C_SMB_TMTSC_BUS_POS 24u
#define MCHP_I2C_SMB_TMTSC_BUS_MASK 0xFF000000ul
#define MCHP_I2C_SMB_TMTSC_BUS_MASK0 0xFFul
/*
* Offset 0x48
* Slave Transmit Buffer register
* 8-bit read-write
*/
#define MCHP_I2C_SMB_SLV_TX_BUF_OFS 0x48ul
/*
* Offset 0x4C
* Slave Receive Buffer register
* 8-bit read-write
*/
#define MCHP_I2C_SMB_SLV_RX_BUF_OFS 0x4Cul
/*
* Offset 0x50
* Master Transmit Buffer register
* 8-bit read-write
*/
#define MCHP_I2C_SMB_MTR_TX_BUF_OFS 0x50ul
/*
* Offset 0x54
* Master Receive Buffer register
* 8-bit read-write
*/
#define MCHP_I2C_SMB_MTR_RX_BUF_OFS 0x54ul
/*
* Offset 0x58
* I2C FSM read-only
*/
#define MCHP_I2C_SMB_I2C_FSM_OFS 0x58ul
/*
* Offset 0x5C
* SMB Netork layer FSM read-only
*/
#define MCHP_I2C_SMB_FSM_OFS 0x5Cul
/*
* Offset 0x60
* Wake Status register
*/
#define MCHP_I2C_SMB_WAKE_STS_OFS 0x60ul
#define MCHP_I2C_SMB_WAKE_STS_START_RWC (1ul << 0)
/*
* Offset 0x64
* Wake Enable register
*/
#define MCHP_I2C_SMB_WAKE_EN_OFS 0x64ul
#define MCHP_I2C_SMB_WAKE_EN (1ul << 0)
/*
* Offset 0x68
*/
#define MCHP_I2C_SMB_WAKE_SYNC_OFS 0x68ul
#define MCHP_I2C_SMB_WAKE_FAST_RESYNC_EN (1ul << 0)
/*
* I2C GIRQ and NVIC mapping
*/
#define MCHP_I2C_SMB_GIRQ 13u
#define MCHP_I2C_SMB_GIRQ_IDX (13u - 8u)
#define MCHP_I2C_SMB_NVIC_GIRQ 5u
#define MCHP_I2C_SMB0_NVIC_DIRECT 20u
#define MCHP_I2C_SMB1_NVIC_DIRECT 21u
#define MCHP_I2C_SMB2_NVIC_DIRECT 22u
#define MCHP_I2C_SMB3_NVIC_DIRECT 23u
#define MCHP_I2C_SMB4_NVIC_DIRECT 158u
#define MCHP_I2C_SMB_GIRQ_SRC_ADDR 0x4000E064ul
#define MCHP_I2C_SMB_GIRQ_SET_EN_ADDR 0x4000E068ul
#define MCHP_I2C_SMB_GIRQ_RESULT_ADDR 0x4000E06Cul
#define MCHP_I2C_SMB_GIRQ_CLR_EN_ADDR 0x4000E070ul
#define MCHP_I2C_SMB0_GIRQ_POS 0u
#define MCHP_I2C_SMB1_GIRQ_POS 1u
#define MCHP_I2C_SMB2_GIRQ_POS 2u
#define MCHP_I2C_SMB3_GIRQ_POS 3u
#define MCHP_I2C_SMB4_GIRQ_POS 4u
#define MCHP_I2C_SMB0_GIRQ_VAL (1ul << 0)
#define MCHP_I2C_SMB1_GIRQ_VAL (1ul << 1)
#define MCHP_I2C_SMB2_GIRQ_VAL (1ul << 2)
#define MCHP_I2C_SMB3_GIRQ_VAL (1ul << 3)
#define MCHP_I2C_SMB4_GIRQ_VAL (1ul << 4)
/*
* Register access by controller base address
*/
/* I2C Control register, write-only */
#define MCHP_I2C_SMB_CTRL_WO(ba) REG8(ba)
/* I2C Status register, read-only */
#define MCHP_I2C_SMB_STS_RO(ba) REG8(ba)
#define MCHP_I2C_SMB_CTRL(ba) REG8_OFS(ba, MCHP_I2C_SMB_CTRL_OFS)
/* Own Address register (slave addresses) */
#define MCHP_I2C_SMB_OWN_ADDR(ba) \
REG16_OFS(ba, MCHP_I2C_SMB_OWN_ADDR_OFS)
/* access bits[7:0] OWN_ADDRESS_1 */
#define MCHP_I2C_SMB_OWN_ADDR1(ba) \
REG8_OFS(ba, MCHP_I2C_SMB_OWN_ADDR_OFS)
/* access bits[15:8] OWN_ADDRESS_2 */
#define MCHP_I2C_SMB_OWN_ADDR2(ba) \
REG8_OFS(ba, (MCHP_I2C_SMB_OWN_ADDR_OFS + 1))
/* I2C Data register */
#define MCHP_I2C_SMB_DATA(ba) \
REG8_OFS(ba, MCHP_I2C_SMB_DATA_OFS)
/* Network layer Master Command register */
#define MCHP_I2C_SMB_MCMD(ba) REG32_OFS(ba, MCHP_I2C_SMB_MSTR_CMD_OFS)
#define MCHP_I2C_SMB_MCMD_MRP(ba) \
REG8_OFS(ba, (MCHP_I2C_SMB_MSTR_CMD_OFS + 0ul))
#define MCHP_I2C_SMB_MCMD_CTRL(ba) \
REG8_OFS(ba, (MCHP_I2C_SMB_MSTR_CMD_OFS + 1ul))
#define MCHP_I2C_SMB_MCMD_WCNT(ba) \
REG8_OFS(ba, (MCHP_I2C_SMB_MSTR_CMD_OFS + 2ul))
#define MCHP_I2C_SMB_MCMD_RCNT(ba) \
REG8_OFS(ba, (MCHP_I2C_SMB_MSTR_CMD_OFS + 3ul))
/* Network layer Slave Command register */
#define MCHP_I2C_SMB_SCMD(ba) REG32_OFS(ba, MCHP_I2C_SMB_SLV_CMD_OFS)
#define MCHP_I2C_SMB_SCMD_SRP(ba) \
REG8_OFS(ba, (MCHP_I2C_SMB_SLV_CMD_OFS + 0ul))
#define MCHP_I2C_SMB_SCMD_WCNT(ba) \
REG8_OFS(ba, (MCHP_I2C_SMB_SLV_CMD_OFS + 1ul))
#define MCHP_I2C_SMB_SCMD_RCNT(ba) \
REG8_OFS(ba, (MCHP_I2C_SMB_SLV_CMD_OFS + 2ul))
/* PEC register */
#define MCHP_I2C_SMB_PEC(ba) REG8_OFS(ba, MCHP_I2C_SMB_PEC_CRC_OFS)
/* Repeated Start Hold Time register */
#define MCHP_I2C_SMB_RSHT(ba) REG8_OFS(ba, MCHP_I2C_SMB_RSHT_OFS)
/* Completion register */
#define MCHP_I2C_SMB_CMPL(ba) REG32_OFS(ba, MCHP_I2C_SMB_CMPL_OFS)
/* access only bits[7:0] R/W timeout enables */
#define MCHP_I2C_SMB_CMPL_B0(ba) REG8_OFS(ba, MCHP_I2C_SMB_CMPL_OFS)
/* Idle Scaling register */
#define MCHP_I2C_SMB_IDLSC(ba) REG32_OFS(ba, MCHP_I2C_SMB_IDLSC_OFS)
/* Configuration register */
#define MCHP_I2C_SMB_CFG(ba) REG32_OFS(ba, MCHP_I2C_SMB_CFG_OFS)
/* access each byte */
#define MCHP_I2C_SMB_CFG_B0(ba) \
REG8_OFS(ba, (MCHP_I2C_SMB_CFG_OFS + 0x00ul))
#define MCHP_I2C_SMB_CFG_B1(ba) \
REG8_OFS(ba, (MCHP_I2C_SMB_CFG_OFS + 0x01ul))
#define MCHP_I2C_SMB_CFG_B2(ba) \
REG8_OFS(ba, (MCHP_I2C_SMB_CFG_OFS + 0x02ul))
#define MCHP_I2C_SMB_CFG_B3(ba) \
REG8_OFS(ba, (MCHP_I2C_SMB_CFG_OFS + 0x03ul))
/* Bus Clock register */
#define MCHP_I2C_SMB_BUS_CLK(ba) REG32_OFS(ba, MCHP_I2C_SMB_BUS_CLK_OFS)
#define MCHP_I2C_SMB_BUS_CLK_LO_PERIOD(ba) \
REG8_OFS(ba, (MCHP_I2C_SMB_BUS_CLK_OFS + 0x00ul))
#define MCHP_I2C_SMB_BUS_CLK_HI_PERIOD(ba) \
REG8_OFS(ba, (MCHP_I2C_SMB_BUS_CLK_OFS + 0x01ul))
/* Bit-Bang Control register */
#define MCHP_I2C_SMB_BB_CTRL(ba) REG8_OFS(ba, MCHP_I2C_SMB_BB_OFS)
/* MCHP Reserved 0x3C register */
#define MCHP_I2C_SMB_RSVD_3C(ba) REG8_OFS(ba, MCHP_I2C_SMB_RSVD_3C)
/* Data Timing register */
#define MCHP_I2C_SMB_DATA_TM(ba) REG32_OFS(ba, MCHP_I2C_SMB_DATA_TM_OFS)
/* Timeout Scaling register */
#define MCHP_I2C_SMB_TMTSC(ba) REG32_OFS(ba, MCHP_I2C_SMB_TMTSC_OFS)
/* Network layer Slave Transmit Buffer register */
#define MCHP_I2C_SMB_SLV_TXB(ba) REG8_OFS(ba, MCHP_I2C_SMB_SLV_TX_BUF_OFS)
/* Network layer Slave Receive Buffer register */
#define MCHP_I2C_SMB_SLV_RXB(ba) REG8_OFS(ba, MCHP_I2C_SMB_SLV_RX_BUF_OFS)
/* Network layer Master Transmit Buffer register */
#define MCHP_I2C_SMB_MTR_TXB(ba) REG8_OFS(ba, MCHP_I2C_SMB_MTR_TX_BUF_OFS)
/* Network layer Master Receive Buffer register */
#define MCHP_I2C_SMB_MTR_RXB(ba) REG8_OFS(ba, MCHP_I2C_SMB_MTR_RX_BUF_OFS)
/* Wake Status register */
#define MCHP_I2C_SMB_WAKE_STS(ba) REG8_OFS(ba, MCHP_I2C_SMB_WAKE_STS_OFS)
/* Wake Enable register */
#define MCHP_I2C_SMB_WAKE_ENABLE(ba) REG8_OFS(ba, MCHP_SMB_WAKE_EN_OFS)
/* =========================================================================*/
/* ================ SMB ================ */
/* =========================================================================*/
/**
* @brief SMBus Network Layer Block (SMB)
*/
typedef struct i2c_smb_regs
{ /*!< (@ 0x40004000) SMB Structure */
__IOM uint8_t CTRLSTS; /*!< (@ 0x00000000) SMB Status(RO), Control(WO) */
uint8_t RSVD1[3];
__IOM uint32_t OWN_ADDR; /*!< (@ 0x00000004) SMB Own address 1 */
__IOM uint8_t I2CDATA; /*!< (@ 0x00000008) SMB I2C Data */
uint8_t RSVD2[3];
__IOM uint32_t MCMD; /*!< (@ 0x0000000C) SMB SMB master command */
__IOM uint32_t SCMD; /*!< (@ 0x00000010) SMB SMB slave command */
__IOM uint8_t PEC; /*!< (@ 0x00000014) SMB PEC value */
uint8_t RSVD3[3];
__IOM uint8_t RSHTM; /*!< (@ 0x00000018) SMB Repeated-Start hold time */
uint8_t RSVD4[7];
__IOM uint32_t COMPL; /*!< (@ 0x00000020) SMB Completion */
__IOM uint32_t IDLSC; /*!< (@ 0x00000024) SMB Idle scaling */
__IOM uint32_t CFG; /*!< (@ 0x00000028) SMB Configuration */
__IOM uint32_t BUSCLK; /*!< (@ 0x0000002C) SMB Bus Clock */
__IOM uint8_t BLKID; /*!< (@ 0x00000030) SMB Block ID */
uint8_t RSVD5[3];
__IOM uint8_t BLKREV; /*!< (@ 0x00000034) SMB Block revision */
uint8_t RSVD6[3];
__IOM uint8_t BBCTRL; /*!< (@ 0x00000038) SMB Bit-Bang control */
uint8_t RSVD7[3];
__IOM uint32_t CLKSYNC; /*!< (@ 0x0000003C) SMB Clock Sync */
__IOM uint32_t DATATM; /*!< (@ 0x00000040) SMB Data timing */
__IOM uint32_t TMOUTSC; /*!< (@ 0x00000044) SMB Time-out scaling */
__IOM uint8_t SLV_TXB; /*!< (@ 0x00000048) SMB SMB slave TX buffer */
uint8_t RSVD8[3];
__IOM uint8_t SLV_RXB; /*!< (@ 0x0000004C) SMB SMB slave RX buffer */
uint8_t RSVD9[3];
__IOM uint8_t MTR_TXB; /*!< (@ 0x00000050) SMB SMB Master TX buffer */
uint8_t RSVD10[3];
__IOM uint8_t MTR_RXB; /*!< (@ 0x00000054) SMB SMB Master RX buffer */
uint8_t RSVD11[3];
__IOM uint32_t FSM; /*!< (@ 0x00000058) SMB FSM (RO) */
__IOM uint32_t FSM_SMB; /*!< (@ 0x0000005C) SMB FSM SMB (RO) */
__IOM uint8_t WAKE_STS; /*!< (@ 0x00000060) SMB Wake status */
uint8_t RSVD12[3];
__IOM uint8_t WAKE_EN; /*!< (@ 0x00000064) SMB Wake enable */
} I2C_SMB_Type;
#endif // #ifndef _SMB_H
/* end smb.h */
/** @}
*/

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mec/mec1501/component/timer.h Normal file
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@ -0,0 +1,362 @@
/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file timer.h
*MEC1501 Timer definitions
*/
/** @defgroup MEC1501 Peripherals Timers
*/
#ifndef _TIMER_H
#define _TIMER_H
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
/*
* Basic timers base address
* Offset between each timer block
*/
#define MCHP_B16TMR_BASE 0x40000C00ul
#define MCHP_B16TMR_MAX_INSTANCE 2u
#define MCHP_B32TMR_BASE 0x40000C80ul
#define MCHP_B32TMR_MAX_INSTANCE 2u
/*
* Offset between instances of the Basic Timer blocks
*/
#define MCHP_BTMR_INSTANCE_POS 5ul
#define MCHP_BTMR_INSTANCE_OFS (1ul << (MCHP_BTMR_INSTANCE_POS))
/* 0 <= n < MCHP_B16TMR_MAX_INSTANCE */
#define MCHP_B16TMR_ADDR(n) \
(MCHP_B16TMR_BASE + ((uint32_t)(n) << MCHP_BTMR_INSTANCE_POS))
#define MCHP_B16TMR0_ADDR 0x40000C00ul
#define MCHP_B16TMR1_ADDR 0x40000C20ul
/* 0 <= n < MCHP_B32TMR_MAX_INSTANCE */
#define MCHP_B32TMR_ADDR(n) \
(MCHP_B32TMR_BASE + ((uint32_t)(n) << MCHP_BTMR_INSTANCE_POS))
#define MCHP_B32TMR0_ADDR 0x40000C80ul
#define MCHP_B32TMR1_ADDR 0x40000CA0ul
/*
* Basic Timer Count Register (Offset +00h)
* 32-bit R/W
* 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
*/
#define MCHP_BTMR_CNT_OFS 0x00ul
/*
* Basic Timer Preload Register (Offset +04h)
* 32-bit R/W
* 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
*/
#define MCHP_BTMR_PRELOAD_OFS 0x04
/*
* Basic Timer Status Register (Offset +08h)
* R/W1C
*/
#define MCHP_BTMR_STS_OFS 0x08ul
#define MCHP_BTMR_STS_MASK 0x01ul
#define MCHP_BTMR_STS_ACTIVE_POS 0u
#define MCHP_BTMR_STS_ACTIVE 0x01ul
/*
* Basic Timer Interrupt Enable Register (Offset +0Ch)
*/
#define MCHP_BTMR_INTEN_OFS 0x0Cul
#define MCHP_BTMR_INTEN_MASK 0x01ul
#define MCHP_BTMR_INTEN_POS 0u
#define MCHP_BTMR_INTEN 0x01ul
#define MCHP_BTMR_INTDIS 0ul
/*
* Basic Timer Control Register (Offset +10h)
*/
#define MCHP_BTMR_CTRL_OFS 0x10ul
#define MCHP_BTMR_CTRL_MASK 0xFFFF00FDul
#define MCHP_BTMR_CTRL_PRESCALE_POS 16u
#define MCHP_BTMR_CTRL_PRESCALE_MASK0 0xFFFFul
#define MCHP_BTMR_CTRL_PRESCALE_MASK 0xFFFF0000ul
#define MCHP_BTMR_CTRL_HALT 0x80ul
#define MCHP_BTMR_CTRL_RELOAD 0x40ul
#define MCHP_BTMR_CTRL_START 0x20ul
#define MCHP_BTMR_CTRL_SOFT_RESET 0x10ul
#define MCHP_BTMR_CTRL_AUTO_RESTART 0x08ul
#define MCHP_BTMR_CTRL_COUNT_UP 0x04ul
#define MCHP_BTMR_CTRL_ENABLE 0x01ul
/* */
#define MCHP_BTMR_CTRL_HALT_POS 7u
#define MCHP_BTMR_CTRL_RELOAD_POS 6u
#define MCHP_BTMR_CTRL_START_POS 5u
#define MCHP_BTMR_CTRL_SRESET_POS 4u
#define MCHP_BTMR_CTRL_AUTO_RESTART_POS 3u
#define MCHP_BTMR_CTRL_COUNT_DIR_POS 2u
#define MCHP_BTMR_CTRL_ENABLE_POS 0u
/* =========================================================================*/
/* ================ 32/16-bit Basic Timer ================ */
/* =========================================================================*/
/**
* @brief 32-bit and 16-bit Basic Timer (BTMR)
* @note Basic timers 0 & 1 are 16-bit, 2 & 3 are 32-bit.
*/
typedef struct btmr_regs
{ /*!< (@ 0x40000C00) BTMR Structure */
__IOM uint32_t CNT; /*!< (@ 0x00000000) BTMR Count */
__IOM uint32_t PRLD; /*!< (@ 0x00000004) BTMR Preload */
__IOM uint8_t STS; /*!< (@ 0x00000008) BTMR Status */
uint8_t RSVDC[3];
__IOM uint8_t IEN; /*!< (@ 0x0000000C) BTMR Interrupt Enable */
uint8_t RSVDD[3];
__IOM uint32_t CTRL; /*!< (@ 0x00000010) BTMR Control */
} BTMR_Type;
/* =========================================================================*/
/* ================ HTMR ================ */
/* =========================================================================*/
#define MCHP_HTMR_BASE_ADDR 0x40009800ul
#define MCHP_HTMR_MAX_INSTANCES 2u
#define MCHP_HTMR_SPACING 0x20ul
#define MCHP_HTMR_SPACING_PWROF2 5u
#define MCHP_HTMR_ADDR(n) \
(MCHP_HTMR_BASE_ADDR + ((uint32_t)(n) << MCHP_HTMR_SPACING_PWROF2))
#define MCHP_HTMR0_ADDR 0x40009800ul
#define MCHP_HTMR1_ADDR 0x40009820ul
/*
* Set count resolution in bit[0]
* 0 = 30.5 us (32786 Hz)
* 1 = 125 ms (8 Hz)
*/
#define MCHP_HTMR_CTRL_REG_MASK 0x01ul
#define MCHP_HTMR_CTRL_RESOL_POS 0u
#define MCHP_HTMR_CTRL_RESOL_MASK (1u << (MCHP_HTMR_CTRL_EN_POS))
#define MCHP_HTMR_CTRL_RESOL_30US (0u << (MCHP_HTMR_CTRL_EN_POS))
#define MCHP_HTMR_CTRL_RESOL_125MS (1u << (MCHP_HTMR_CTRL_EN_POS))
/*
* Hibernation timer is started and stopped by writing a value
* to the CNT (count) register.
* Writing a non-zero value resets and start the counter counting down.
* Writing 0 stops the timer.
*/
#define MCHP_HTMR_CNT_STOP_VALUE 0u
/**
* @brief Hibernation Timer (HTMR)
*/
typedef struct htmr_regs
{ /*!< (@ 0x40009800) HTMR Structure */
__IOM uint16_t PRLD; /*!< (@ 0x00000000) HTMR Preload */
uint8_t RSVD1[2];
__IOM uint16_t CTRL; /*!< (@ 0x00000004) HTMR Control */
uint8_t RSVD2[2];
__IM uint16_t CNT; /*!< (@ 0x00000008) HTMR Count (RO) */
uint8_t RSVD3[2];
} HTMR_Type;
/* =========================================================================*/
/* ================ Capture/Compare Timer ================ */
/* =========================================================================*/
#define MCHP_CCT_BASE_ADDR 0x40001000ul
#define MCHP_CCT_MAX_INSTANCE 1u
/* Control register at offset 0x00 */
#define MCHP_CCT_CTRL_ACTIVATE (1ul << 0)
#define MCHP_CCT_CTRL_FRUN_EN (1ul << 1)
#define MCHP_CCT_CTRL_FRUN_RESET (1ul << 2) /* self clearing bit */
#define MCHP_CCT_CTRL_TCLK_MASK0 (0x07ul)
#define MCHP_CCT_CTRL_TCLK_MASK ((MCHP_CCT_CTRL_TCLK_MASK0) << 4)
#define MCHP_CCT_CTRL_TCLK_DIV_1 (0ul)
#define MCHP_CCT_CTRL_TCLK_DIV_2 (1ul << 4)
#define MCHP_CCT_CTRL_TCLK_DIV_4 (2ul << 4)
#define MCHP_CCT_CTRL_TCLK_DIV_8 (3ul << 4)
#define MCHP_CCT_CTRL_TCLK_DIV_16 (4ul << 4)
#define MCHP_CCT_CTRL_TCLK_DIV_32 (5ul << 4)
#define MCHP_CCT_CTRL_TCLK_DIV_64 (6ul << 4)
#define MCHP_CCT_CTRL_TCLK_DIV_128 (7ul << 4)
#define MCHP_CCT_CTRL_COMP0_EN (1ul << 8)
#define MCHP_CCT_CTRL_COMP1_EN (1ul << 9)
#define MCHP_CCT_CTRL_COMP1_SET (1ul << 16) /* R/WS */
#define MCHP_CCT_CTRL_COMP0_SET (1ul << 17) /* R/WS */
/**
* @brief Capture/Compare Timer (CCT)
*/
typedef struct cct_regs
{ /*!< (@ 0x40001000) CCT Structure */
__IOM uint32_t CTRL; /*!< (@ 0x00000000) CCT Control */
__IOM uint32_t CAP0_CTRL; /*!< (@ 0x00000004) CCT Capture 0 Control */
__IOM uint32_t CAP1_CTRL; /*!< (@ 0x00000008) CCT Capture 1 Control */
__IOM uint32_t FREE_RUN; /*!< (@ 0x0000000C) CCT Free run counter */
__IOM uint32_t CAP0; /*!< (@ 0x00000010) CCT Capture 0 */
__IOM uint32_t CAP1; /*!< (@ 0x00000014) CCT Capture 1 */
__IOM uint32_t CAP2; /*!< (@ 0x00000018) CCT Capture 2 */
__IOM uint32_t CAP3; /*!< (@ 0x0000001C) CCT Capture 3 */
__IOM uint32_t CAP4; /*!< (@ 0x00000020) CCT Capture 4 */
__IOM uint32_t CAP5; /*!< (@ 0x00000024) CCT Capture 5 */
__IOM uint32_t COMP0; /*!< (@ 0x00000028) CCT Compare 0 */
__IOM uint32_t COMP1; /*!< (@ 0x0000002C) CCT Compare 1 */
} CCT_Type;
/* =========================================================================*/
/* ================ RTMR ================ */
/* =========================================================================*/
#define MCHP_RTMR_BASE_ADDR 0x40007400ul
#define MCHP_RTMR_FREQ_HZ 32768ul
#define MCHP_RTMR_CTRL_MASK 0x1Ful
#define MCHP_RTMR_CTRL_BLK_EN_POS 0u
#define MCHP_RTMR_CTRL_BLK_EN_MASK (1ul << (MCHP_RTMR_CTRL_BLK_EN_POS))
#define MCHP_RTMR_CTRL_BLK_EN (1ul << (MCHP_RTMR_CTRL_BLK_EN_POS))
#define MCHP_RTMR_CTRL_AUTO_RELOAD_POS 1u
#define MCHP_RTMR_CTRL_AUTO_RELOAD_MASK (1ul << (MCHP_RTMR_CTRL_AUTO_RELOAD_POS))
#define MCHP_RTMR_CTRL_AUTO_RELOAD (1ul << (MCHP_RTMR_CTRL_AUTO_RELOAD_POS))
#define MCHP_RTMR_CTRL_START_POS 2u
#define MCHP_RTMR_CTRL_START_MASK (1ul << (MCHP_RTMR_CTRL_START_POS))
#define MCHP_RTMR_CTRL_START (1ul << (MCHP_RTMR_CTRL_START_POS))
#define MCHP_RTMR_CTRL_HW_HALT_EN_POS 3u
#define MCHP_RTMR_CTRL_HW_HALT_EN_MASK (1ul << (MCHP_RTMR_CTRL_HW_HALT_EN_POS))
#define MCHP_RTMR_CTRL_HW_HALT_EN (1ul << (MCHP_RTMR_CTRL_HW_HALT_EN_POS))
#define MCHP_RTMR_CTRL_FW_HALT_EN_POS 4u
#define MCHP_RTMR_CTRL_FW_HALT_EN_MASK (1ul << (MCHP_RTMR_CTRL_FW_HALT_EN_POS))
#define MCHP_RTMR_CTRL_FW_HALT_EN (1ul << (MCHP_RTMR_CTRL_FW_HALT_EN_POS))
/**
* @brief RTOS Timer (RTMR)
*/
typedef struct rtmr_regs
{ /*!< (@ 0x40007400) RTMR Structure */
__IOM uint32_t CNT; /*!< (@ 0x00000000) RTMR Counter */
__IOM uint32_t PRLD; /*!< (@ 0x00000004) RTMR Preload */
__IOM uint8_t CTRL; /*!< (@ 0x00000008) RTMR Control */
uint8_t RSVD1[3];
__IOM uint32_t SOFTIRQ; /*!< (@ 0x0000000C) RTMR Soft IRQ */
} RTMR_Type;
/* =========================================================================*/
/* ================ WKTMR ================ */
/* =========================================================================*/
#define MCHP_WKTMR_BASE_ADDR 0x4000AC80ul
#define MCHP_WKTMR_CTRL_MASK 0x41ul
#define MCHP_WKTMR_CTRL_WT_EN_POS 0u
#define MCHP_WKTMR_CTRL_WT_EN_MASK (1ul << (MCHP_WKTMR_CTRL_WT_EN_POS))
#define MCHP_WKTMR_CTRL_WT_EN (1ul << (MCHP_WKTMR_CTRL_WT_EN_POS))
#define MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS 6u
#define MCHP_WKTMR_CTRL_PWRUP_EV_EN_MASK \
(1ul << (MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS))
#define MCHP_WKTMR_CTRL_PWRUP_EV_EN \
(1ul << (MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS))
#define MCHP_WKTMR_ALARM_CNT_MASK 0x0FFFFFFFul
#define MCHP_WKTMR_TMR_CMP_MASK 0x0FFFFFFFul
#define MCHP_WKTMR_CLK_DIV_MASK 0x7FFFul
#define MCHP_WKTMR_SS_MASK 0x0Ful
#define MCHP_WKTMR_SS_RATE_DIS 0x00ul
#define MCHP_WKTMR_SS_RATE_2HZ 0x01ul
#define MCHP_WKTMR_SS_RATE_4HZ 0x02ul
#define MCHP_WKTMR_SS_RATE_8HZ 0x03ul
#define MCHP_WKTMR_SS_RATE_16HZ 0x04ul
#define MCHP_WKTMR_SS_RATE_32HZ 0x05ul
#define MCHP_WKTMR_SS_RATE_64HZ 0x06ul
#define MCHP_WKTMR_SS_RATE_128HZ 0x07ul
#define MCHP_WKTMR_SS_RATE_256HZ 0x08ul
#define MCHP_WKTMR_SS_RATE_512HZ 0x09ul
#define MCHP_WKTMR_SS_RATE_1024HZ 0x0Aul
#define MCHP_WKTMR_SS_RATE_2048HZ 0x0Bul
#define MCHP_WKTMR_SS_RATE_4096HZ 0x0Cul
#define MCHP_WKTMR_SS_RATE_8192HZ 0x0Dul
#define MCHP_WKTMR_SS_RATE_16384HZ 0x0Eul
#define MCHP_WKTMR_SS_RATE_32768HZ 0x0Ful
#define MCHP_WKTMR_SWKC_MASK 0x3C3ul
#define MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS 0ul
#define MCHP_WKTMR_SWKC_PWRUP_EV_STS_MASK \
(1ul << (MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS))
#define MCHP_WKTMR_SWKC_PWRUP_EV_STS \
(1ul << (MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS))
#define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS 4ul
#define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_MASK \
(1ul << (MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS))
#define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS \
(1ul << (MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS))
#define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS 5ul
#define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_MASK \
(1ul << (MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS))
#define MCHP_WKTMR_SWKC_SYSPWR_PRES_EN \
(1ul << (MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS))
#define MCHP_WKTMR_SWKC_AUTO_RELOAD_POS \
6ul
#define MCHP_WKTMR_SWKC_AUTO_RELOAD_MASK \
(1ul << (MCHP_WKTMR_SWKC_AUTO_RELOAD_POS))
#define MCHP_WKTMR_SWKC_AUTO_RELOAD \
(1ul << (MCHP_WKTMR_SWKC_AUTO_RELOAD_POS))
/**
* @brief Week Timer (WKTMR)
*/
typedef struct wktmr_regs
{ /*!< (@ 0x4000AC80) WKTMR Structure */
__IOM uint32_t CTRL; /*! (@ 0x00000000) WKTMR control */
__IOM uint32_t ALARM_CNT; /*! (@ 0x00000004) WKTMR Week alarm counter */
__IOM uint32_t TMR_COMP; /*! (@ 0x00000008) WKTMR Week timer compare */
__IM uint32_t CLKDIV; /*! (@ 0x0000000C) WKTMR Clock Divider (RO) */
__IOM uint32_t SS_INTR_SEL; /*! (@ 0x00000010) WKTMR Sub-second interrupt select */
__IOM uint32_t SWK_CTRL; /*! (@ 0x00000014) WKTMR Sub-week control */
__IOM uint32_t SWK_ALARM; /*! (@ 0x00000018) WKTMR Sub-week alarm */
__IOM uint32_t BGPO_DATA; /*! (@ 0x0000001C) WKTMR BGPO data */
__IOM uint32_t BGPO_PWR; /*! (@ 0x00000020) WKTMR BGPO power */
__IOM uint32_t BGPO_RST; /*! (@ 0x00000024) WKTMR BGPO reset */
} WKTMR_Type;
#endif /* #ifndef _TIMER_H */
/* end timer.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file uart.h
*MEC1501 UART Peripheral Library API
*/
/** @defgroup MEC1501 Peripherals UART
*/
#ifndef _UART_H
#define _UART_H
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
#define MCHP_UART0_ID 0u
#define MCHP_UART1_ID 1u
#define MCHP_UART2_ID 2u
#define MCHP_UART_MAX_ID 3u
#define MCHP_UART_RX_FIFO_MAX_LEN 16u
#define MCHP_UART_TX_FIFO_MAX_LEN 16u
#define MCHP_UART_BAUD_RATE_MIN 50ul
#define MCHP_UART_BAUD_RATE_MAX 1500000ul
#define MCHP_UART0_BASE_ADDRESS 0x400F2400ul
#define MCHP_UART1_BASE_ADDRESS 0x400F2800ul
#define MCHP_UART2_BASE_ADDRESS 0x400F2C00ul
#define MCHP_UART_BASE_ADDR(n) \
(MCHP_UART0_BASE_ADDRESS + ((uint32_t)(n) << 10u))
#define MCHP_UART_GIRQ_NUM 15u
#define MCHP_UART_GIRQ_ID 7u
#define MCHP_UART_GIRQ_SRC_ADDR 0x4000E08Cul
#define MCHP_UART_GIRQ_EN_SET_ADDR 0x4000E090ul
#define MCHP_UART_GIRQ_RESULT_ADDR 0x4000E094ul
#define MCHP_UART_GIRQ_EN_CLR_ADDR 0x4000E098ul
#define MCHP_UART0_GIRQ_BIT 0u
#define MCHP_UART1_GIRQ_BIT 1u
#define MCHP_UART2_GIRQ_BIT 4u
#define MCHP_UART0_GIRQ_VAL (1ul << (MCHP_UART0_GIRQ_BIT))
#define MCHP_UART1_GIRQ_VAL (1ul << (MCHP_UART1_GIRQ_BIT))
#define MCHP_UART2_GIRQ_VAL (1ul << (MCHP_UART2_GIRQ_BIT))
#define MCHP_UART0_NVIC_DIRECT_NUM 40u
#define MCHP_UART1_NVIC_DIRECT_NUM 41u
#define MCHP_UART2_NVIC_DIRECT_NUM 44u
#define MCHP_UART_NVIC_SETEN_GIRQ_ADDR 0xE000E100ul
#define MCHP_UART_NVIC_SETEN_GIRQ_BIT 7u /* aggregated */
#define MCHP_UART_NVIC_SETEN_DIRECT_ADDR 0xE000E104ul
#define MCHP_UART0_NVIC_SETEN_DIRECT_BIT (40u - 32u)
#define MCHP_UART1_NVIC_SETEN_DIRECT_BIT (41u - 32u)
#define MCHP_UART2_NVIC_SETEN_DIRECT_BIT (44u - 32u)
/* CMSIS NVIC macro IRQn parameter */
#define MCHP_UART_NVIC_IRQn 7ul /* aggregated */
#define MCHP_UART0_NVIC_IRQn 41ul /* UART0 direct mode */
#define MCHP_UART1_NVIC_IRQn 42ul /* UART1 direct mode */
#define MCHP_UART2_NVIC_IRQn 44ul /* UART2 direct mode */
/*
* LCR DLAB=0
* Transmit buffer(WO), Receive buffer(RO)
* LCR DLAB=1, BAUD rate divisor LSB
*/
#define MCHP_UART_RTXB_OFS 0u
#define MCHP_UART_BRGD_LSB_OFS 0u
/*
* LCR DLAB=0
* Interrupt Enable Register, R/W
* LCR DLAB=1, BAUD rate divisor MSB
*/
#define MCHP_UART_BRGD_MSB_OFS 1u
#define MCHP_UART_IER_OFS 1u
#define MCHP_UART_IER_MASK 0x0Ful
#define MCHP_UART_IER_ERDAI 0x01ul /* Received data available and timeouts */
#define MCHP_UART_IER_ETHREI 0x02ul /* TX Holding register empty */
#define MCHP_UART_IER_ELSI 0x04ul /* Errors: Overrun, Parity, Framing, and Break */
#define MCHP_UART_IER_EMSI 0x08ul /* Modem Status */
#define MCHP_UART_IER_ALL 0x0Ful
/* FIFO Contro Register, Write-Only */
#define MCHP_UART_FCR_OFS 2u
#define MCHP_UART_FCR_MASK 0xCFu
#define MCHP_UART_FCR_EXRF 0x01u /* Enable TX & RX FIFO's */
#define MCHP_UART_FCR_CLR_RX_FIFO 0x02u /* Clear RX FIFO, bit is self-clearing */
#define MCHP_UART_FCR_CLR_TX_FIFO 0x04u /* Clear TX FIFO, bit is self-clearing */
#define MCHP_UART_FCR_DMA_EN 0x08u /* DMA Mode Enable. Not implemented */
#define MCHP_UART_FCR_RX_FIFO_LVL_MASK 0xC0u /* RX FIFO trigger level mask */
#define MCHP_UART_FCR_RX_FIFO_LVL_1 0x00u
#define MCHP_UART_FCR_RX_FIFO_LVL_4 0x40u
#define MCHP_UART_FCR_RX_FIFO_LVL_8 0x80u
#define MCHP_UART_FCR_RX_FIFO_LVL_14 0xC0u
/* Interrupt Identification Register, Read-Only */
#define MCHP_UART_IIR_OFS 2u
#define MCHP_UART_IIR_MASK 0xCFu
#define MCHP_UART_IIR_NOT_IPEND 0x01u
#define MCHP_UART_IIR_INTID_MASK0 0x07u
#define MCHP_UART_IIR_INTID_POS 1u
#define MCHP_UART_IIR_INTID_MASK 0x0Eu
#define MCHP_UART_IIR_FIFO_EN_MASK 0xC0u
/* interrupt values */
#define MCHP_UART_IIR_INT_NONE 0x01u
#define MCHP_UART_IIR_INT_LS 0x06u /* Highest priority: Line status, overrun, framing, or break */
#define MCHP_UART_IIR_INT_RX 0x04u /* Highest-1. RX data available or RX FIFO trigger level reached */
#define MCHP_UART_IIR_INT_RX_TMOUT 0x0Cu /* Highest-2. RX timeout */
#define MCHP_UART_IIR_INT_THRE 0x02u /* Highest-3. TX Holding register empty. */
#define MCHP_UART_IIR_INT_MS 0x00u /* Highest-4. MODEM status. */
/* Line Control Register R/W */
#define MCHP_UART_LCR_OFS 3u
#define MCHP_UART_LCR_WORD_LEN_MASK 0x03u
#define MCHP_UART_LCR_WORD_LEN_5 0x00u
#define MCHP_UART_LCR_WORD_LEN_6 0x01u
#define MCHP_UART_LCR_WORD_LEN_7 0x02u
#define MCHP_UART_LCR_WORD_LEN_8 0x03u
#define MCHP_UART_LCR_STOP_BIT_1 0x00u
#define MCHP_UART_LCR_STOP_BIT_2 0x04u /* 2 for 6-8 bits or 1.5 for 5 bits */
#define MCHP_UART_LCR_PARITY_NONE 0x00u
#define MCHP_UART_LCR_PARITY_EN 0x08u
#define MCHP_UART_LCR_PARITY_ODD 0x00u
#define MCHP_UART_LCR_PARITY_EVEN 0x10u
#define MCHP_UART_LCR_STICK_PARITY 0x20u
#define MCHP_UART_LCR_BREAK_EN 0x40u
#define MCHP_UART_LCR_DLAB_EN 0x80u
/* MODEM Control Register R/W */
#define MCHP_UART_MCR_OFS 4u
#define MCHP_UART_MCR_MASK 0x1Fu
#define MCHP_UART_MCR_DTRn 0x01u
#define MCHP_UART_MCR_RTSn 0x02u
#define MCHP_UART_MCR_OUT1 0x04u
#define MCHP_UART_MCR_OUT2 0x08u
#define MCHP_UART_MCR_LOOPBCK_EN 0x10u
/* Line Status Register RO */
#define MCHP_UART_LSR_OFS 5u
#define MCHP_UART_LSR_DATA_RDY 0x01u
#define MCHP_UART_LSR_OVERRUN 0x02u
#define MCHP_UART_LSR_PARITY 0x04u
#define MCHP_UART_LSR_FRAME 0x08u
#define MCHP_UART_LSR_RX_BREAK 0x10u
#define MCHP_UART_LSR_THRE 0x20u
#define MCHP_UART_LSR_TEMT 0x40u
#define MCHP_UART_LSR_FIFO_ERR 0x80u
#define MCHP_UART_LSR_ANY 0xFFu
/* MODEM Status Register RO */
#define MCHP_UART_MSR_OFS 6u
#define MCHP_UART_MSR_DCTS 0x01u
#define MCHP_UART_MSR_DDSR 0x02u
#define MCHP_UART_MSR_TERI 0x04u
#define MCHP_UART_MSR_DDCD 0x08u
#define MCHP_UART_MSR_CTS 0x10u
#define MCHP_UART_MSR_DSR 0x20u
#define MCHP_UART_MSR_RI 0x40u
#define MCHP_UART_MSR_DCD 0x80u
/* Scratch Register RO */
#define MCHP_UART_SCR_OFS 7u
/* UART Logical Device Activate Register */
#define MCHP_UART_LD_ACT 0x330ul
#define MCHP_UART_LD_ACTIVATE 0x01ul
/* UART Logical Device Config Register */
#define MCHP_UART_LD_CFG 0x3F0ul
#define MCHP_UART_LD_CFG_INTCLK (0u << 0)
#define MCHP_UART_LD_CFG_EXTCLK (1u << 0)
#define MCHP_UART_LD_CFG_RESET_SYS (0u << 1)
#define MCHP_UART_LD_CFG_RESET_VCC (1u << 1)
#define MCHP_UART_LD_CFG_NO_INVERT (0u << 2)
#define MCHP_UART_LD_CFG_INVERT (1u << 2)
/* BAUD rate generator */
#define MCHP_UART_INT_CLK_24M (1ul << 15)
/* 1.8MHz internal clock source */
#define MCHP_UART_1P8M_BAUD_50 2304u
#define MCHP_UART_1P8M_BAUD_110 1536u
#define MCHP_UART_1P8M_BAUD_150 768u
#define MCHP_UART_1P8M_BAUD_300 384u
#define MCHP_UART_1P8M_BAUD_1200 96u
#define MCHP_UART_1P8M_BAUD_2400 48u
#define MCHP_UART_1P8M_BAUD_9600 12u
#define MCHP_UART_1P8M_BAUD_19200 6u
#define MCHP_UART_1P8M_BAUD_38400 3u
#define MCHP_UART_1P8M_BAUD_57600 2u
#define MCHP_UART_1P8M_BAUD_115200 1u
/* 24MHz internal clock source. n = 24e6 / (BAUD * 16) = 1500000 / BAUD */
#define MCHP_UART_24M_BAUD_115200 ((13u) + (MCHP_UART_INT_CLK_24M))
#define MCHP_UART_24M_BAUD_57600 ((26u) + (MCHP_UART_INT_CLK_24M))
/*
* Register access by UART zero based ID
* 0 <= uart id <= 1
*/
#define MCHP_UART_TXB_WO_ID(id) \
REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_RTXB_OFS)
#define MCHP_UART_RXB_RO_ID(id) \
REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_RTXB_OFS)
#define MCHP_UART_BRGD_LSB_ID(id) \
REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_BRGD_LSB_OFS)
#define MCHP_UART_BRGD_MSB_ID(id) \
REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_BRGD_MSB_OFS)
#define MCHP_UART_FCR_WO_ID(id) \
REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_FCR_OFS)
#define MCHP_UART_IIR_RO_ID(id) \
REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_IIR_OFS)
#define MCHP_UART_LCR_ID(id) \
REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_LCR_OFS)
#define MCHP_UART_MCR_ID(id) \
REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_MCR_OFS)
#define MCHP_UART_LSR_RO_ID(id) \
REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_LSR_OFS)
#define MCHP_UART_MSR_RO_ID(id) \
REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_MSR_OFS)
#define MCHP_UART_SCR_ID(id) \
REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_SCR_OFS)
/*
* Register access by UART base address
*/
#define MCHP_UART_TXB_WO(ba) REG8_OFS((ba), MCHP_UART_RTXB_OFS)
#define MCHP_UART_RXB_RO(ba) REG8_OFS((ba), MCHP_UART_RTXB_OFS)
#define MCHP_UART_BRGD_LSB(ba) REG8_OFS((ba), MCHP_UART_BRGD_LSB_OFS)
#define MCHP_UART_BRGD_MSB(ba) REG8_OFS((ba), MCHP_UART_BRGD_MSB_OFS)
#define MCHP_UART_FCR_WO(ba) REG8_OFS((ba), MCHP_UART_FCR_OFS)
#define MCHP_UART_IIR_RO(ba) REG8_OFS((ba), MCHP_UART_IIR_OFS)
#define MCHP_UART_LCR(ba) REG8_OFS((ba), MCHP_UART_LCR_OFS)
#define MCHP_UART_MCR(ba) REG8_OFS((ba), MCHP_UART_MCR_OFS)
#define MCHP_UART_LSR_RO(ba) REG8_OFS((ba), MCHP_UART_LSR_OFS)
#define MCHP_UART_MSR_RO(ba) REG8_OFS((ba), MCHP_UART_MSR_OFS)
#define MCHP_UART_SCR(ba) REG8_OFS((ba), MCHP_UART_SCR_OFS)
/* =========================================================================*/
/* ================ UART ================ */
/* =========================================================================*/
/**
* @brief UART interface (UART)
*/
#define MCHP_UART_NUM_INSTANCES 3u
#define MCHP_UART_SPACING 0x400ul
#define MCHP_UART_SPACING_PWROF2 10u
typedef struct uart_regs
{ /*!< (@ 0x400F2400) UART Structure */
__IOM uint8_t RTXB; /*!< (@ 0x0000) UART RXB(RO), TXB(WO). BRGD_LSB(RW LCR.DLAB=1) */
__IOM uint8_t IER; /*!< (@ 0x0001) UART IER(RW). BRGD_MSB(RW LCR.DLAB=1) */
__IOM uint8_t IIR_FCR; /*!< (@ 0x0002) UART IIR(RO), FCR(WO) */
__IOM uint8_t LCR; /*!< (@ 0x0003) UART Line Control(RW) */
__IOM uint8_t MCR; /*!< (@ 0x0004) UART Modem Control(RW) */
__IOM uint8_t LSR; /*!< (@ 0x0005) UART Line Status(RO) */
__IOM uint8_t MSR; /*!< (@ 0x0006) UART Modem Status(RO) */
__IOM uint8_t SCR; /*!< (@ 0x0007) UART Scratch(RW) */
uint8_t RSVDA[0x330u - 0x08u];
__IOM uint8_t ACTV; /*!< (@ 0x0330) UART Activate(RW) */
uint8_t RSVDB[0x3F0u - 0x331u];
__IOM uint8_t CFG_SEL; /*!< (@ 0x03F0) UART Configuration Select(RW) */
} UART_Type;
#endif /* #ifndef _MCHP_UART_H */
/* end uart.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file vbat.h
*MEC1501 VBAT Registers and memory definitions
*/
/** @defgroup MEC1501 Peripherals VBAT
*/
#ifndef _VBAT_H
#define _VBAT_H
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
/*
* VBAT Registers Registers
*/
#define MCHP_VBAT_REGISTERS_ADDR 0x4000A400ul
#define MCHP_VBAT_MEMORY_ADDR 0x4000A800ul
#define MCHP_VBAT_MEMORY_SIZE 64ul
/*
* Offset 0x00 Power-Fail and Reset Status
*/
#define MCHP_VBATR_PFRS_OFS 0ul
#define MCHP_VBATR_PFRS_MASK 0x7Cul
#define MCHP_VBATR_PFRS_SYS_RST_POS 2u
#define MCHP_VBATR_PFRS_JTAG_POS 3u
#define MCHP_VBATR_PFRS_RESETI_POS 4u
#define MCHP_VBATR_PFRS_WDT_POS 5u
#define MCHP_VBATR_PFRS_SYSRESETREQ_POS 6u
#define MCHP_VBATR_PFRS_VBAT_RST_POS 7u
#define MCHP_VBATR_PFRS_SYS_RST (1ul << 2)
#define MCHP_VBATR_PFRS_JTAG (1ul << 3)
#define MCHP_VBATR_PFRS_RESETI (1ul << 4)
#define MCHP_VBATR_PFRS_WDT (1ul << 5)
#define MCHP_VBATR_PFRS_SYSRESETREQ (1ul << 6)
#define MCHP_VBATR_PFRS_VBAT_RST (1ul << 7)
/*
* Offset 0x08 32K Clock Enable
*/
#define MCHP_VBATR_CLKEN_OFS 0x08ul
#define MCHP_VBATR_CLKEN_MASK 0x0Eul
#define MCHP_VBATR_CLKEN_32K_DOM_POS 1u
#define MCHP_VBATR_CLKEN_32K_SRC_POS 2u
#define MCHP_VBATR_CLKEN_XTAL_SEL_POS 3u
#define MCHP_VBATR_CLKEN_32K_DOM_ALWYS_ON (0ul << 1)
#define MCHP_VBATR_CLKEN_32K_DOM_32K_IN_PIN (1ul << 1)
#define MCHP_VBATR_CLKEN_32K_ALWYS_ON_SI_OSC (0ul << 2)
#define MCHP_VBATR_CLKEN_32K_ALWYS_ON_XTAL (1ul << 2)
#define MCHP_VBATR_CLKEN_XTAL12_PARALLEL (0ul << 3)
#define MCHP_VBATR_CLKEN_XTAL2_SE_32K (1ul << 3)
#define MCHP_VBATR_USE_SIL_OSC 0x00ul
#define MCHP_VBATR_USE_32KIN_PIN MCHP_VBATR_CLKEN_32K_DOM_32K_IN_PIN
#define MCHP_VBATR_USE_PAR_CRYSTAL \
(MCHP_VBATR_CLKEN_32K_ALWYS_ON_XTAL + MCHP_VBATR_CLKEN_XTAL12_PARALLEL)
#define MCHP_VBATR_USE_SE_CRYSTAL \
(MCHP_VBATR_CLKEN_32K_ALWYS_ON_XTAL + MCHP_VBATR_CLKEN_XTAL2_SE_32K)
/*
* Monotonic Counter
*/
#define MCHP_VBATR_MCNT_LSW_OFS 0x20ul
#define MCHP_VBATR_MCNT_MSW_OFS 0x24ul
/*
* Register access
*/
#define MCHP_VBATR_PFRS() \
REG8(MCHP_VBAT_REGISTERS_ADDR + MCHP_VBATR_PFRS_OFS)
#define MCHP_VBATR_CLKEN() \
REG8(MCHP_VBAT_REGISTERS_ADDR + MCHP_VBATR_CLKEN_OFS)
#define MCHP_VBATR_MCNT_LO() \
REG32(MCHP_VBAT_REGISTERS_ADDR + MCHP_VBATR_MCNT_LSW_OFS)
#define MCHP_VBATR_MCNT_HI() \
REG32(MCHP_VBAT_REGISTERS_ADDR + MCHP_VBATR_MCNT_MSW_OFS)
/* =========================================================================*/
/* ================ VBATR ================ */
/* =========================================================================*/
/**
* @brief VBAT Register Bank (VBATR)
*/
typedef struct vbatr_regs
{ /*!< (@ 0x4000A400) VBATR Structure */
__IOM uint32_t PFRS; /*! (@ 0x00000000) VBATR Power Fail Reset Status */
uint8_t RSVD1[4];
__IOM uint32_t CLK32_EN; /*! (@ 0x00000008) VBATR 32K clock enable */
uint8_t RSVD2[20];
__IOM uint32_t MCNT_LO; /*! (@ 0x00000020) VBATR monotonic count lo */
__IOM uint32_t MCNT_HI; /*! (@ 0x00000024) VBATR monotonic count hi */
} VBATR_Type;
/* =========================================================================*/
/* ================ VBATM ================ */
/* =========================================================================*/
/**
* @brief VBAT Memory (VBATM)
*/
#define MCHP_VBAT_MEM_LEN 64ul
typedef struct vbatm_regs
{ /*!< (@ 0x4000A800) VBATM Structure */
union vbmem_u {
uint32_t u32[(MCHP_VBAT_MEM_LEN) / 4];
uint16_t u16[(MCHP_VBAT_MEM_LEN) / 2];
uint8_t u8[MCHP_VBAT_MEM_LEN];
} MEM;
} VBATM_Type;
#endif /* #ifndef _VBAT_H */
/* end vbat.h */
/** @}
*/

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/**
*
* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file wdt.h
*MEC1501 Watch Dog Timer Registers
*/
/** @defgroup MEC1501 Peripherals WDT
*/
#ifndef _WDT_H
#define _WDT_H
#include <stdint.h>
#include <stddef.h>
#include "regaccess.h"
/* =========================================================================*/
/* ================ WDT ================ */
/* =========================================================================*/
#define MCHP_WDT_BASE_ADDR 0x40000400ul
#define MCHP_WDT_CTRL_MASK 0x021Dul
#define MCHP_WDT_CTRL_EN_POS 0u
#define MCHP_WDT_CTRL_EN_MASK (1u1 << (MCHP_WDT_CTRL_EN_POS))
#define MCHP_WDT_CTRL_EN (1u1 << (MCHP_WDT_CTRL_EN_POS))
#define MCHP_WDT_CTRL_HTMR_STALL_POS 2u
#define MCHP_WDT_CTRL_HTMR_STALL_MASK (1u1 << (MCHP_WDT_CTRL_HTMR_STALL_POS))
#define MCHP_WDT_CTRL_HTMR_STALL_EN (1u1 << (MCHP_WDT_CTRL_HTMR_STALL_POS))
#define MCHP_WDT_CTRL_WKTMR_STALL_POS 3u
#define MCHP_WDT_CTRL_WKTMR_STALL_MASK (1u1 << (MCHP_WDT_CTRL_WKTMR_STALL_POS))
#define MCHP_WDT_CTRL_WKTMR_STALL_EN (1u1 << (MCHP_WDT_CTRL_WKTMR_STALL_POS))
#define MCHP_WDT_CTRL_JTAG_STALL_POS 4u
#define MCHP_WDT_CTRL_JTAG_STALL_MASK (1u1 << (MCHP_WDT_CTRL_JTAG_STALL_POS))
#define MCHP_WDT_CTRL_JTAG_STALL_EN (1u1 << (MCHP_WDT_CTRL_JTAG_STALL_POS))
/* WDT Kick register. Write any value to reload counter */
#define MCHP_WDT_KICK_OFS 0x08ul
/* WDT Count register. Read only */
#define MCHP_WDT_CNT_RO_OFS 0x0Cul
#define MCHP_WDT_CNT_RO_MASK 0xFFFFul
/*
* If this bit is set when the WDT counts down it will clear this
* bit, fire an interrupt if IEN is enabled, and start counting up.
* Once it reaches maximum count it actives its reset output.
* This feature allows WDT ISR time to take action before WDT asserts
* its reset signal.
* If this bit is clear WDT will immediately assert its reset signal
* when counter counts down to 0.
*/
#define WDT_CTRL_INH1_POS 9u
#define WDT_CTRL_INH1_MASK (1u1 << (WDT_CTRL_INH1_POS))
#define WDT_CTRL_INH1_EN (1u1 << (WDT_CTRL_INH1_POS))
/* Interrupt Enable Register */
#define WDT_IEN_MASK 0x01ul
#define WDT_IEN_EVENT_IRQ_POS 0u
#define WDT_IEN_EVENT_IRQ_MASK (1ul << (WDT_IEN_EVENT_IRQ_POS))
#define WDT_IEN_EVENT_IRQ_EN (1ul << (WDT_IEN_EVENT_IRQ_POS))
/**
* @brief Watch Dog Timer (WDT)
*/
typedef struct wdt_regs
{
__IOM uint16_t LOAD; /*!< (@ 0x00000000) WDT Load */
uint8_t RSVD1[2];
__IOM uint16_t CTRL; /*!< (@ 0x00000004) WDT Control */
uint8_t RSVD2[2];
__OM uint8_t KICK; /*!< (@ 0x00000008) WDT Kick (WO) */
uint8_t RSVD3[3];
__IM uint16_t CNT; /*!< (@ 0x0000000C) WDT Count (RO) */
uint8_t RSVD4[2];
__IOM uint16_t STS; /*!< (@ 0x00000010) WDT Status */
uint8_t RSVD5[2];
__IOM uint8_t IEN; /*!< (@ 0x00000010) WDT Interrupt Enable */
} WDT_Type;
#endif /* #ifndef _WDT_H */
/* end wdt.h */
/** @}
*/