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modules: microchip: mec1501 Add GIRQ source definitions 

Origin:
    MCHP
        https://github.com/MicrochipTech/hal_microchip

Status:
    version 1.2.0

Add all GIRQ interrupt source definitions to the ECIA
component header. Add peripheral instance numbers to
main MEC1501 header. Add common BIT macro if not defined
in an outside header.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit is contained in:
Scott Worley 2021-04-20 10:33:00 -04:00 committed by Anas Nashif
parent a1ec761014
commit ba967b6a4b
6 changed files with 583 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.txt
View File

@ -13,4 +13,4 @@ MEC1501 component style is located at:
https://github.com/MicrochipTech/hal_microchip
Version: 1.1.0
Version: 1.2.0

52
mec/common/mec_cpu.h
View File

@ -79,31 +79,6 @@ extern "C" {
#define CPU_CLZ(x) __clz(x)
/*
* The microsecond delay register is implemented in a Normal Data Memory
* Region. Normal regions have relaxed data ordering semantics. This can
* cause issues because writes to this register can complete before a
* previous write to Device or Strongly ordered memory. Please use the
* inline code after this definition. It uses the Data Synchronization
* Barrier instruction to insure all outstanding writes complete before
* the instruction after DSB is executed.
* #define MEC2016_DELAY_REG *((volatile uint8_t*) MEC2016_DELAY_REG_BASE)
*/
static inline void MICROSEC_DELAY(unsigned char n)
{
volatile unsigned long *pdly_reg;
pdly_reg = (volatile unsigned long *)0x10000000ul;
__asm volatile (
"\tstrb n, [pdly_reg]\n"
"\tldrb n, [pdly_reg]\n"
"\tadd n, #0\n"
"\tdmb\n"
);
}
#elif defined(__XC32_PART_SUPPORT_VERSION) /* Microchip XC32 compiler customized GCC */
#error "!!! FORCED BUILD ERROR: compiler.h XC32 support has not been implemented !!!"
@ -214,33 +189,6 @@ static inline __attribute__((always_inline, noreturn)) void CPU_JMP(uint32_t add
while(1);
}
/*
* The microsecond delay register is implemented in a Normal Data Memory
* Region. Normal regions have relaxed data ordering semantics. This can
* cause issues because writes to this register can complete before a
* previous write to Device or Strongly ordered memory. Please use the
* inline code after this definition. It uses the Data Synchronization
* Barrier instruction to insure all outstanding writes complete before
* the instruction after DSB is executed.
* #define MEC2016_DELAY_REG *((volatile uint8_t*) MEC2016_DELAY_REG_BASE)
*/
static __always_inline void MICROSEC_DELAY(uint8_t n)
{
uint32_t dly_reg_addr = 0x10000000ul;
__asm volatile (
"\tstrb %0, [%1]\n"
"\tldrb %0, [%1]\n"
"\tadd %0, #0\n"
"\tdmb\n"
:
: "r" (n), "r" (dly_reg_addr)
: "memory"
);
}
static __always_inline void write_read_back8(volatile uint8_t* addr, uint8_t val)
{
__asm__ __volatile__ (

51
mec/common/mec_defs.h Normal file
View File

@ -0,0 +1,51 @@
/**
*
* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
/** @file mec_defs.h
*MEC Peripheral library return values
*/
/** @defgroup MEC type and bit defines
*/
#ifndef _MEC_DEFS_H
#define _MEC_DEFS_H
#ifndef BIT
#define BIT(n) (1ul << (n))
#endif
#ifndef SHLU32
#define SHLU32(v, n) ((unsigned long)(v) << (n))
#endif
#ifndef BIT_CLR
#define BIT_CLR(v, bpos) (v) &= ~BIT(bpos)
#endif
#endif /* #ifndef _MEC_DEFS_H */
/* end mec_defs.h */
/** @}
*/

8
mec/common/regaccess.h
View File

@ -57,5 +57,13 @@
#define REG16_OFS(a, ofs) *(volatile uint16_t *)((uintptr_t)(a) + (uintptr_t)(ofs))
#define REG8_OFS(a, ofs) *(volatile uint8_t *)((uintptr_t)(a) + (uintptr_t)(ofs))
#define REG32_BIT_SET(a, b) *(volatile uint32_t *)(a) |= (1ul << (b))
#define REG32_BIT_CLR(a, b) *(volatile uint32_t *)(a) &= ~(1ul << (b))
#define REG16_BIT_SET(a, b) *(volatile uint16_t *)(a) |= (1ul << (b))
#define REG16_BIT_CLR(a, b) *(volatile uint16_t *)(a) &= ~(1ul << (b))
#define REG8_BIT_SET(a, b) *(volatile uint8_t *)(a) |= (1ul << (b))
#define REG8_BIT_CLR(a, b) *(volatile uint8_t *)(a) &= ~(1ul << (b))
#endif // #ifndef _REGACCESS_H

53
mec/mec1501/MEC1501hsz.h
View File

@ -428,8 +428,61 @@ typedef enum IRQn {
#define GCFG_BASE (PERIPH_BASE + 0xFFF00ul) /*!< (GCFG ) Base Address */
#define DELAY_US_BASE (0x10000000ul) /*!< (1 us Delay register) Base Address */
/** @} *//* End of group Device_Peripheral_peripheralAddr */
#define MCHP_ACMP_INSTANCES 1
#define MCHP_ACPI_EC_INSTANCES 4
#define MCHP_ACPI_PM1_INSTANCES 1
#define MCHP_ADC_INSTANCES 1
#define MCHP_BTMR16_INSTANCES 2
#define MCHP_BTMR32_INSTANCES 2
#define MCHP_CCT_INSTANCES 1
#define MCHP_CTMR_INSTANCES 0
#define MCHP_DMA_INSTANCES 1
#define MCHP_ECIA_INSTANCES 1
#define MCHP_EMI_INSTANCES 2
#define MCHP_HDMI_CEC_INSTANCES 1
#define MCHP_HTMR_INSTANCES 2
#define MCHP_I2C_INSTANCES 3
#define MCHP_I2C_SMB_INSTANCES 5
#define MCHP_LED_INSTANCES 3
#define MCHP_MBOX_INSTANCES 1
#define MCHP_OTP_INSTANCES 1
#define MCHP_P80CAP_INSTANCES 2
#define MCHP_PECI_INSTANCES 1
#define MCHP_PROCHOT_INSTANCES 1
#define MCHP_PS2_INSTANCES 2
#define MCHP_PWM_INSTANCES 9
#define MCHP_QMSPI_INSTANCES 1
#define MCHP_RCID_INSTANCES 3
#define MCHP_RPMFAN_INSTANCES 0
#define MCHP_RTC_INSTANCES 1
#define MCHP_RTMR_INSTANCES 1
#define MCHP_SPIEP_INSTANCES 1
#define MCHP_TACH_INSTANCES 4
#define MCHP_TFDP_INSTANCES 1
#define MCHP_UART_INSTANCES 3
#define MCHP_WDT_INSTANCES 1
#define MCHP_WKTMR_INSTANCES 1
#define MCHP_ACMP_CHANNELS 2
#define MCHP_ADC_CHANNELS 8
#define MCHP_BGPO_GPIO_PINS 3
#define MCHP_DMA_CHANNELS 12
#define MCHP_GIRQS 19
#define MCHP_GPIO_PINS 128
#define MCHP_GPIO_PORTS 6
#define MCHP_GPTP_PORTS 3
#define MCHP_I2C_SMB_PORTS 15
#define MCHP_I2C_PORTMAP 0xFFFFul;
#define MCHP_QMSPI_PORTS 3
#define MCHP_PS2_PORTS 2
#define MCHP_VCI_IN_PINS 4
#define MCHP_VCI_OUT_PINS 1
#define MCHP_VCI_OVRD_IN_PINS 0
#include "component/acpi_ec.h"
#include "component/adc.h"
#include "component/dma.h"

492
mec/mec1501/component/ecia.h
View File

@ -44,15 +44,11 @@
#define MCHP_ECIA_GIRQ_NO_NVIC 22u
#define MCHP_ECIA_AGGR_BITMAP ((1ul << 8) + (1ul << 9) + (1ul << 10) +\
(1ul << 11) + (1ul << 12) + (1ul << 24) +\
(1ul << 25) + (1ul << 26))
#define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) |\
BIT(12) | BIT(24) | BIT(25) | BIT(26))
#define MCHP_ECIA_DIRECT_BITMAP ((1ul << 13) + (1ul << 14) +\
(1ul << 15) + (1ul << 16) +\
(1ul << 17) + (1ul << 18) +\
(1ul << 19) + (1ul << 20) +\
(1ul << 21) + (1ul << 23))
#define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) |\
BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(23))
/*
* ARM Cortex-M4 NVIC registers
@ -69,16 +65,16 @@
/* 0 <= n < MCHP_NUM_NVIC_REGS */
#define MCHP_NVIC_SET_EN(n) \
REG32(MCHP_NVIC_SET_EN_BASE + ((uintptr_t)(n) << 2))
REG32(MCHP_NVIC_SET_EN_BASE + ((uintptr_t)(n) * 4U))
#define MCHP_NVIC_CLR_EN(n) \
REG32(MCHP_NVIC_CLR_EN_BASE + ((uintptr_t)(n) << 2))
REG32(MCHP_NVIC_CLR_EN_BASE + ((uintptr_t)(n) * 4U))
#define MCHP_NVIC_SET_PEND(n) \
REG32(MCHP_NVIC_SET_PEND_BASE + ((uintptr_t)(n) << 2))
REG32(MCHP_NVIC_SET_PEND_BASE + ((uintptr_t)(n) * 4U))
#define MCHP_NVIC_CLR_PEND(n) \
REG32(MCHP_NVIC_CLR_PEND_BASE + ((uintptr_t)(n) << 2))
REG32(MCHP_NVIC_CLR_PEND_BASE + ((uintptr_t)(n) * 4U))
/*
* ECIA registers
@ -273,13 +269,13 @@
* 8 <= n <= 26 corresponding to GIRQ08, GIRQ09, ..., GIRQ26
*/
#define MCHP_GIRQ_BLK_SETEN(n) \
REG32(MCHP_GIRQ_BLK_ENSET_ADDR) = (1ul << (uint32_t)(n))
REG32(MCHP_GIRQ_BLK_ENSET_ADDR) = BIT(n)
#define MCHP_GIRQ_BLK_CLREN(n) \
REG32(MCHP_GIRQ_BLK_ENCLR_ADDR) = (1ul << (uint32_t)(n))
REG32(MCHP_GIRQ_BLK_ENCLR_ADDR) = BIT(n)
#define MCHP_GIRQ_BLK_IS_ACTIVE(n) \
((REG32(MCHP_GIRQ_BLK_ACTIVE_ADDR) & (1ul << (uint32_t)(n))) != 0ul)
((REG32(MCHP_GIRQ_BLK_ACTIVE_ADDR) & BIT(n)) != 0ul)
/* 8 <= n <= 26 corresponding to GIRQ08, GIRQ09, ..., GIRQ26 */
#define MCHP_GIRQ_SRC(n) REG32(MCHP_GIRQ_SRC_ADDR(n))
@ -294,16 +290,16 @@
* 0 <= pos <= 31 the bit position of the peripheral interrupt source.
*/
#define MCHP_GIRQ_SRC_CLR(n, pos) \
REG32(MCHP_GIRQ_SRC_ADDR(n)) = (1ul << (uint32_t)(pos))
REG32(MCHP_GIRQ_SRC_ADDR(n)) = BIT(pos)
#define MCHP_GIRQ_SET_EN(n, pos) \
REG32(MCHP_GIRQ_ENSET_ADDR(n)) = (1ul << (uint32_t)(pos))
REG32(MCHP_GIRQ_ENSET_ADDR(n)) = BIT(pos)
#define MCHP_GIRQ_CLR_EN(n, pos) \
REG32(MCHP_GIRQ_ENCLR_ADDR(n)) = (1ul << (uint32_t)(pos))
REG32(MCHP_GIRQ_ENCLR_ADDR(n)) = BIT(pos)
#define MCHP_GIRQ_IS_RESULT(n, pos) \
(REG32(MCHP_GIRQ_RESULT_ADDR(n)) & (1ul << (uint32_t)(pos)) != 0ul)
((REG32(MCHP_GIRQ_RESULT_ADDR(n)) & BIT(pos)) != 0ul)
/* =========================================================================*/
/* ================ ECIA ================ */
@ -332,9 +328,427 @@ enum MCHP_GIRQ_IDS {
MCHP_GIRQ_ID_MAX,
};
/* GIRQ Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_PORT80_DEBUG0_GIRQ_VAL (1ul << 22)
#define MCHP_PORT80_DEBUG1_GIRQ_VAL (1ul << 23)
/*
* Legacy names: Port 80h capture peripherals.
* GIRQ Source, Enable_Set/Clr, Result registers bit positions
*/
#define MCHP_PORT80_DEBUG0_GIRQ_VAL BIT(22)
#define MCHP_PORT80_DEBUG1_GIRQ_VAL BIT(23)
/* GIRQ08 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_GPIO_0140_GIRQ_BIT BIT(0)
#define MCHP_GPIO_0141_GIRQ_BIT BIT(1)
#define MCHP_GPIO_0142_GIRQ_BIT BIT(2)
#define MCHP_GPIO_0143_GIRQ_BIT BIT(3)
#define MCHP_GPIO_0144_GIRQ_BIT BIT(4)
#define MCHP_GPIO_0145_GIRQ_BIT BIT(5)
#define MCHP_GPIO_0146_GIRQ_BIT BIT(6)
#define MCHP_GPIO_0147_GIRQ_BIT BIT(7)
#define MCHP_GPIO_0150_GIRQ_BIT BIT(8)
#define MCHP_GPIO_0151_GIRQ_BIT BIT(9)
#define MCHP_GPIO_0152_GIRQ_BIT BIT(10)
#define MCHP_GPIO_0153_GIRQ_BIT BIT(11)
#define MCHP_GPIO_0154_GIRQ_BIT BIT(12)
#define MCHP_GPIO_0155_GIRQ_BIT BIT(13)
#define MCHP_GPIO_0156_GIRQ_BIT BIT(14)
#define MCHP_GPIO_0157_GIRQ_BIT BIT(15)
#define MCHP_GPIO_0161_GIRQ_BIT BIT(17)
#define MCHP_GPIO_0162_GIRQ_BIT BIT(18)
#define MCHP_GPIO_0163_GIRQ_BIT BIT(19)
#define MCHP_GPIO_0165_GIRQ_BIT BIT(21)
#define MCHP_GPIO_0170_GIRQ_BIT BIT(24)
#define MCHP_GPIO_0171_GIRQ_BIT BIT(25)
#define MCHP_GPIO_0172_GIRQ_BIT BIT(26)
#define MCHP_GPIO_0175_GIRQ_BIT BIT(29)
#define MCHP_GPIO_0140_0176_GIRQ_MASK 0x272EFFFFu
/* GIRQ09 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_GPIO_0100_GIRQ_BIT BIT(0)
#define MCHP_GPIO_0101_GIRQ_BIT BIT(1)
#define MCHP_GPIO_0102_GIRQ_BIT BIT(2)
#define MCHP_GPIO_0104_GIRQ_BIT BIT(4)
#define MCHP_GPIO_0105_GIRQ_BIT BIT(5)
#define MCHP_GPIO_0106_GIRQ_BIT BIT(6)
#define MCHP_GPIO_0107_GIRQ_BIT BIT(7)
#define MCHP_GPIO_0112_GIRQ_BIT BIT(10)
#define MCHP_GPIO_0113_GIRQ_BIT BIT(11)
#define MCHP_GPIO_0114_GIRQ_BIT BIT(12)
#define MCHP_GPIO_0115_GIRQ_BIT BIT(13)
#define MCHP_GPIO_0116_GIRQ_BIT BIT(14)
#define MCHP_GPIO_0117_GIRQ_BIT BIT(15)
#define MCHP_GPIO_0120_GIRQ_BIT BIT(16)
#define MCHP_GPIO_0121_GIRQ_BIT BIT(17)
#define MCHP_GPIO_0122_GIRQ_BIT BIT(18)
#define MCHP_GPIO_0123_GIRQ_BIT BIT(19)
#define MCHP_GPIO_0124_GIRQ_BIT BIT(20)
#define MCHP_GPIO_0125_GIRQ_BIT BIT(21)
#define MCHP_GPIO_0126_GIRQ_BIT BIT(22)
#define MCHP_GPIO_0127_GIRQ_BIT BIT(23)
#define MCHP_GPIO_0130_GIRQ_BIT BIT(24)
#define MCHP_GPIO_0131_GIRQ_BIT BIT(25)
#define MCHP_GPIO_0132_GIRQ_BIT BIT(26)
#define MCHP_GPIO_0100_0136_GIRQ_MASK 0x07FFFCF7u
/* GIRQ10 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_GPIO_0040_GIRQ_BIT BIT(0)
#define MCHP_GPIO_0042_GIRQ_BIT BIT(2)
#define MCHP_GPIO_0043_GIRQ_BIT BIT(3)
#define MCHP_GPIO_0044_GIRQ_BIT BIT(4)
#define MCHP_GPIO_0045_GIRQ_BIT BIT(5)
#define MCHP_GPIO_0046_GIRQ_BIT BIT(6)
#define MCHP_GPIO_0047_GIRQ_BIT BIT(7)
#define MCHP_GPIO_0050_GIRQ_BIT BIT(8)
#define MCHP_GPIO_0051_GIRQ_BIT BIT(9)
#define MCHP_GPIO_0052_GIRQ_BIT BIT(10)
#define MCHP_GPIO_0053_GIRQ_BIT BIT(11)
#define MCHP_GPIO_0054_GIRQ_BIT BIT(12)
#define MCHP_GPIO_0055_GIRQ_BIT BIT(13)
#define MCHP_GPIO_0056_GIRQ_BIT BIT(14)
#define MCHP_GPIO_0057_GIRQ_BIT BIT(15)
#define MCHP_GPIO_0060_GIRQ_BIT BIT(16)
#define MCHP_GPIO_0061_GIRQ_BIT BIT(17)
#define MCHP_GPIO_0062_GIRQ_BIT BIT(18)
#define MCHP_GPIO_0063_GIRQ_BIT BIT(19)
#define MCHP_GPIO_0064_GIRQ_BIT BIT(20)
#define MCHP_GPIO_0065_GIRQ_BIT BIT(21)
#define MCHP_GPIO_0066_GIRQ_BIT BIT(22)
#define MCHP_GPIO_0067_GIRQ_BIT BIT(23)
#define MCHP_GPIO_0070_GIRQ_BIT BIT(24)
#define MCHP_GPIO_0071_GIRQ_BIT BIT(25)
#define MCHP_GPIO_0072_GIRQ_BIT BIT(26)
#define MCHP_GPIO_0073_GIRQ_BIT BIT(27)
#define MCHP_GPIO_0074_GIRQ_BIT BIT(28)
#define MCHP_GPIO_0075_GIRQ_BIT BIT(29)
#define MCHP_GPIO_0040_0076_GIRQ_MASK 0x3FFFFFFDu
/* GIRQ11 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_GPIO_0000_GIRQ_BIT BIT(0)
#define MCHP_GPIO_0002_GIRQ_BIT BIT(2)
#define MCHP_GPIO_0003_GIRQ_BIT BIT(3)
#define MCHP_GPIO_0004_GIRQ_BIT BIT(4)
#define MCHP_GPIO_0007_GIRQ_BIT BIT(7)
#define MCHP_GPIO_0010_GIRQ_BIT BIT(8)
#define MCHP_GPIO_0011_GIRQ_BIT BIT(9)
#define MCHP_GPIO_0012_GIRQ_BIT BIT(10)
#define MCHP_GPIO_0013_GIRQ_BIT BIT(11)
#define MCHP_GPIO_0014_GIRQ_BIT BIT(12)
#define MCHP_GPIO_0015_GIRQ_BIT BIT(13)
#define MCHP_GPIO_0016_GIRQ_BIT BIT(14)
#define MCHP_GPIO_0017_GIRQ_BIT BIT(15)
#define MCHP_GPIO_0020_GIRQ_BIT BIT(16)
#define MCHP_GPIO_0021_GIRQ_BIT BIT(17)
#define MCHP_GPIO_0022_GIRQ_BIT BIT(18)
#define MCHP_GPIO_0023_GIRQ_BIT BIT(19)
#define MCHP_GPIO_0024_GIRQ_BIT BIT(20)
#define MCHP_GPIO_0025_GIRQ_BIT BIT(21)
#define MCHP_GPIO_0026_GIRQ_BIT BIT(22)
#define MCHP_GPIO_0027_GIRQ_BIT BIT(23)
#define MCHP_GPIO_0030_GIRQ_BIT BIT(24)
#define MCHP_GPIO_0031_GIRQ_BIT BIT(25)
#define MCHP_GPIO_0032_GIRQ_BIT BIT(26)
#define MCHP_GPIO_0033_GIRQ_BIT BIT(27)
#define MCHP_GPIO_0034_GIRQ_BIT BIT(28)
#define MCHP_GPIO_0035_GIRQ_BIT BIT(29)
#define MCHP_GPIO_0036_GIRQ_BIT BIT(30)
#define MCHP_GPIO_0000_0036_GIRQ_MASK 0x7FFFFF9Du
/* GIRQ12 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_GPIO_0200_GIRQ_BIT BIT(0)
#define MCHP_GPIO_0201_GIRQ_BIT BIT(1)
#define MCHP_GPIO_0202_GIRQ_BIT BIT(2)
#define MCHP_GPIO_0203_GIRQ_BIT BIT(3)
#define MCHP_GPIO_0204_GIRQ_BIT BIT(4)
#define MCHP_GPIO_0205_GIRQ_BIT BIT(5)
#define MCHP_GPIO_0206_GIRQ_BIT BIT(6)
#define MCHP_GPIO_0207_GIRQ_BIT BIT(7)
#define MCHP_GPIO_0211_GIRQ_BIT BIT(9)
#define MCHP_GPIO_0212_GIRQ_BIT BIT(10)
#define MCHP_GPIO_0213_GIRQ_BIT BIT(11)
#define MCHP_GPIO_0221_GIRQ_BIT BIT(17)
#define MCHP_GPIO_0222_GIRQ_BIT BIT(18)
#define MCHP_GPIO_0223_GIRQ_BIT BIT(19)
#define MCHP_GPIO_0224_GIRQ_BIT BIT(20)
#define MCHP_GPIO_0226_GIRQ_BIT BIT(22)
#define MCHP_GPIO_0227_GIRQ_BIT BIT(23)
#define MCHP_GPIO_0200_0236_GIRQ_MASK 0x00DE0EFFu
/* GIRQ13 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_I2C_SMB_0_GIRQ_BIT BIT(0)
#define MCHP_I2C_SMB_1_GIRQ_BIT BIT(1)
#define MCHP_I2C_SMB_2_GIRQ_BIT BIT(2)
#define MCHP_I2C_SMB_3_GIRQ_BIT BIT(3)
#define MCHP_I2C_SMB_4_GIRQ_BIT BIT(4)
#define MCHP_I2C_0_GIRQ_BIT BIT(5)
#define MCHP_I2C_1_GIRQ_BIT BIT(6)
#define MCHP_I2C_2_GIRQ_BIT BIT(7)
/* Masks for blocks with multiple instances or sources */
#define MCHP_SMB_I2C_GIRQ_MASK 0x1Fu
#define MCHP_I2C_GIRQ_MASK 0xE0u
/* GIRQ14 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_DMA_CH00_GIRQ_BIT BIT(0)
#define MCHP_DMA_CH01_GIRQ_BIT BIT(1)
#define MCHP_DMA_CH02_GIRQ_BIT BIT(2)
#define MCHP_DMA_CH03_GIRQ_BIT BIT(3)
#define MCHP_DMA_CH04_GIRQ_BIT BIT(4)
#define MCHP_DMA_CH05_GIRQ_BIT BIT(5)
#define MCHP_DMA_CH06_GIRQ_BIT BIT(6)
#define MCHP_DMA_CH07_GIRQ_BIT BIT(7)
#define MCHP_DMA_CH08_GIRQ_BIT BIT(8)
#define MCHP_DMA_CH09_GIRQ_BIT BIT(9)
#define MCHP_DMA_CH10_GIRQ_BIT BIT(10)
#define MCHP_DMA_CH11_GIRQ_BIT BIT(11)
#define MCHP_DMA_GIRQ_MASK 0x0FFFu
/* GIRQ15 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_UART_0_GIRQ_BIT BIT(0)
#define MCHP_UART_1_GIRQ_BIT BIT(1)
#define MCHP_EMI_0_GIRQ_BIT BIT(2)
#define MCHP_EMI_1_GIRQ_BIT BIT(3)
#define MCHP_UART_2_GIRQ_BIT BIT(4)
#define MCHP_ACPI_EC_0_IBF_GIRQ_BIT BIT(5)
#define MCHP_ACPI_EC_0_OBE_GIRQ_BIT BIT(6)
#define MCHP_ACPI_EC_1_IBF_GIRQ_BIT BIT(7)
#define MCHP_ACPI_EC_1_OBE_GIRQ_BIT BIT(8)
#define MCHP_ACPI_EC_2_IBF_GIRQ_BIT BIT(9)
#define MCHP_ACPI_EC_2_OBE_GIRQ_BIT BIT(10)
#define MCHP_ACPI_EC_3_IBF_GIRQ_BIT BIT(11)
#define MCHP_ACPI_EC_3_OBE_GIRQ_BIT BIT(12)
#define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15)
#define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16)
#define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17)
#define MCHP_KBC_OBE_GIRQ_BIT BIT(18)
#define MCHP_KBC_IBF_GIRQ_BIT BIT(19)
#define MCHP_MBOX_0_GIRQ_BIT BIT(20)
#define MCHP_P80BD_0_GIRQ_BIT BIT(22)
#define MCHP_P80BD_1_GIRQ_BIT BIT(23)
/* Masks for blocks with multiple instances or sources */
#define MCHP_UART_GIRQ_MASK 0x13u
#define MCHP_UART_EMI_GIRQ_MASK 0x0Cu
#define MCHP_ACPI_EC_GIRQ_MASK 0x01FE0u
#define MCHP_ACPI_PM1_GIRQ_MASK 0x38000u
#define MCHP_KBC_GIRQ_MASK 0xC0000u
#define MCHP_BDP_MASK 0xC00000u
#define MCHP_HOST_PERIPH_GIRQ_MASK 0xDF9FFFu
/* GIRQ16 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_PK_ERR_GIRQ_BIT BIT(0)
#define MCHP_PK_END_GIRQ_BIT BIT(1)
#define MCHP_RNG_GIRQ_BIT BIT(2)
#define MCHP_AES_GIRQ_BIT BIT(3)
#define MCHP_HASH_GIRQ_BIT BIT(4)
#define MCHP_CRYPTO_GIRQ_MASK 0x1Fu
/* GIRQ17 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_PECI_GIRQ_BIT BIT(0)
#define MCHP_TACH_0_GIRQ_BIT BIT(1)
#define MCHP_TACH_1_GIRQ_BIT BIT(2)
#define MCHP_TACH_2_GIRQ_BIT BIT(3)
#define MCHP_TACH_3_GIRQ_BIT BIT(4)
#define MCHP_HDMI_CEC_0_GIRQ_BIT BIT(5)
#define MCHP_ADC_0_SGL_GIRQ_BIT BIT(8)
#define MCHP_ADC_0_RPT_GIRQ_BIT BIT(9)
#define MCHP_LED_0_GIRQ_BIT BIT(13)
#define MCHP_LED_1_GIRQ_BIT BIT(14)
#define MCHP_LED_2_GIRQ_BIT BIT(15)
#define MCHP_PHOT_0_GIRQ_BIT BIT(17)
/* Masks for blocks with multiple instances or sources */
#define MCHP_TACH_GIRQ_MASK 0x1Eu
#define MCHP_ADC_GIRQ_MASK 0x300u
#define MCHP_LED_GIRQ_MASK 0xE000u
#define MCHP_PERIPH_GROUP_1_MASK 0x2E33Fu
/* GIRQ18 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_SPIEP_0_GIRQ_BIT BIT(0)
#define MCHP_QMSPI_0_GIRQ_BIT BIT(1)
#define MCHP_PS2_0_ACT_GIRQ_BIT BIT(10)
#define MCHP_PS2_1_ACT_GIRQ_BIT BIT(11)
#define MCHP_EERPROMC_0_GIRQ_BIT BIT(13)
#define MCHP_CCT_0_CNT_GIRQ_BIT BIT(20)
#define MCHP_CCT_0_CAP0_GIRQ_BIT BIT(21)
#define MCHP_CCT_0_CAP1_GIRQ_BIT BIT(22)
#define MCHP_CCT_0_CAP2_GIRQ_BIT BIT(23)
#define MCHP_CCT_0_CAP3_GIRQ_BIT BIT(24)
#define MCHP_CCT_0_CAP4_GIRQ_BIT BIT(25)
#define MCHP_CCT_0_CAP5_GIRQ_BIT BIT(26)
#define MCHP_CCT_0_CMP0_GIRQ_BIT BIT(27)
#define MCHP_CCT_0_CMP1_GIRQ_BIT BIT(28)
/* Masks for blocks with multiple instances or sources */
#define MCHP_PS2_GIRQ_MASK 0xC00u
#define MCHP_CCT_0_GIRQ_MASK 0x1FF00000u
#define MCHP_PERIPH_GROUP_2_MASK 0x1FF02C03u
/* GIRQ19 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_ESPI_PC_GIRQ_BIT BIT(0)
#define MCHP_ESPI_BM1_GIRQ_BIT BIT(1)
#define MCHP_ESPI_BM2_GIRQ_BIT BIT(2)
#define MCHP_ESPI_LTR_GIRQ_BIT BIT(3)
#define MCHP_ESPI_OOB_UP_GIRQ_BIT BIT(4)
#define MCHP_ESPI_OOB_DN_GIRQ_BIT BIT(5)
#define MCHP_ESPI_FC_GIRQ_BIT BIT(6)
#define MCHP_ESPI_RESET_GIRQ_BIT BIT(7)
#define MCHP_ESPI_VWEN_GIRQ_BIT BIT(8)
#define MCHP_ESPI_SAF_DONE_GIRQ_BIT BIT(9)
#define MCHP_ESPI_SAF_ERR_GIRQ_BIT BIT(10)
/* Masks for blocks with multiple instances or sources */
#define MCHP_ESPI_BM_GIRQ_MASK 0x006u
#define MCHP_ESPI_OOB_GIRQ_MASK 0x030u
#define MCHP_ESPI_SAF_GIRQ_MASK 0x600u
#define MCHP_ESPI_GIRQ_MASK 0xFFFu
/* GIRQ20 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_STAP_OBF_GIRQ_BIT BIT(0)
#define MCHP_STAP_IBF_GIRQ_BIT BIT(1)
#define MCHP_STAP_WAKE_GIRQ_BIT BIT(2)
#define MCHP_OTP_READY_GIRQ_BIT BIT(3)
/* Masks for blocks with multiple instances or sources */
#define MCHP_STAP_GIRQ_MASK 0x007u
#define MCHP_PERIPH_GROUP_3_MASK 0x00Fu
/* GIRQ21 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_WDT_GIRQ_BIT BIT(2)
#define MCHP_WTMR_ALARM_GIRQ_BIT BIT(3)
#define MCHP_WTMR_SUBWK_GIRQ_BIT BIT(4)
#define MCHP_WTMR_ONESEC_GIRQ_BIT BIT(5)
#define MCHP_WTMR_SUBSEC_GIRQ_BIT BIT(6)
#define MCHP_WTMR_SPP_GIRQ_BIT BIT(7)
#define MCHP_RTC_GIRQ_BIT BIT(8)
#define MCHP_RTC_ALARM_GIRQ_BIT BIT(9)
#define MCHP_VCI_OVRD_IN_GIRQ_BIT BIT(10)
#define MCHP_VCI_IN0_GIRQ_BIT BIT(11)
#define MCHP_VCI_IN1_GIRQ_BIT BIT(12)
#define MCHP_VCI_IN2_GIRQ_BIT BIT(13)
#define MCHP_VCI_IN3_GIRQ_BIT BIT(14)
#define MCHP_PS2_0_PORT0A_WK_GIRQ_BIT BIT(18)
#define MCHP_PS2_0_PORT0B_WK_GIRQ_BIT BIT(19)
#define MCHP_PS2_0_PORT1B_WK_GIRQ_BIT BIT(21)
#define MCHP_KEYSCAN_GIRQ_BIT BIT(25)
#define MCHP_GLUE_GIRQ_BIT BIT(26)
/* Masks for blocks with multiple instances or sources */
#define MCHP_WTMR_GIRQ_MASK 0xF8u
#define MCHP_RTC_GIRQ_MASK 0x300u
#define MCHP_VCI_GIRQ_MASK 0x7C00u
#define MCHP_PS2_PORT_WK_GIRQ_MASK 0x2C0000u
#define MCHP_PERIPH_GROUP_4_MASK 0x62C7FFCu
/*
* GIRQ22 Source, Enable_Set/Clr, Result registers bit positions
* NOTE: These wake sources allow the peripheral to turn back on clocks
* long enough to facilite the data transfer. No interrupt to the EC occurs
* unless the peripheral was configured to generate an EC interrupt for
* the specific data transfer.
*/
#define MCHP_SPIEP_WK_CLK_GIRQ_BIT BIT(0)
#define MCHP_I2C_SMB_0_WK_CLK_GIRQ_BIT BIT(1)
#define MCHP_I2C_SMB_1_WK_CLK_GIRQ_BIT BIT(2)
#define MCHP_I2C_SMB_2_WK_CLK_GIRQ_BIT BIT(3)
#define MCHP_I2C_SMB_3_WK_CLK_GIRQ_BIT BIT(4)
#define MCHP_I2C_SMB_4_WK_CLK_GIRQ_BIT BIT(5)
#define MCHP_I2C_0_WK_CLK_GIRQ_BIT BIT(6)
#define MCHP_I2C_1_WK_CLK_GIRQ_BIT BIT(7)
#define MCHP_I2C_2_WK_CLK_GIRQ_BIT BIT(8)
#define MCHP_ESPI_WK_CLK_GIRQ_BIT BIT(9)
/* Masks for blocks with multiple instances or sources */
#define MCHP_I2C_SMB_WK_CLK_GIRQ_MASK 0x3Eu
#define MCHP_I2C_WK_CLK_GIRQ_MASK 0x1C0u
#define MCHP_CLK_WK_CLK_GIRQ_MASK 0x3FFu
/* GIRQ23 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_BTMR16_0_GIRQ_BIT BIT(0)
#define MCHP_BTMR16_1_GIRQ_BIT BIT(1)
#define MCHP_BTMR32_0_GIRQ_BIT BIT(4)
#define MCHP_BTMR32_1_GIRQ_BIT BIT(5)
#define MCHP_RTMR_0_GIRQ_BIT BIT(10)
#define MCHP_RTMR_0_SWI0_GIRQ_BIT BIT(11)
#define MCHP_RTMR_0_SWI1_GIRQ_BIT BIT(12)
#define MCHP_RTMR_0_SWI2_GIRQ_BIT BIT(13)
#define MCHP_RTMR_0_SWI3_GIRQ_BIT BIT(14)
#define MCHP_HTMR_0_GIRQ_BIT BIT(16)
#define MCHP_HTMR_1_GIRQ_BIT BIT(17)
/* Masks for blocks with multiple instances or sources */
#define MCHP_BTMR16_GIRQ_MASK 0x03u
#define MCHP_BTMR32_GIRQ_MASK 0x30u
#define MCHP_RMTR_GIRQ_MASK 0x7C00u
#define MCHP_HTMR_GIRQ_MASK 0x30000u
#define MCHP_PERIPH_GROUP_5_GIRQ_MASK 0x37C33u
/* GIRQ24 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_MSVW00_SRC0_GIRQ_BIT BIT(0)
#define MCHP_MSVW00_SRC1_GIRQ_BIT BIT(1)
#define MCHP_MSVW00_SRC2_GIRQ_BIT BIT(2)
#define MCHP_MSVW00_SRC3_GIRQ_BIT BIT(3)
#define MCHP_MSVW01_SRC0_GIRQ_BIT BIT(4)
#define MCHP_MSVW01_SRC1_GIRQ_BIT BIT(5)
#define MCHP_MSVW01_SRC2_GIRQ_BIT BIT(6)
#define MCHP_MSVW01_SRC3_GIRQ_BIT BIT(7)
#define MCHP_MSVW02_SRC0_GIRQ_BIT BIT(8)
#define MCHP_MSVW02_SRC1_GIRQ_BIT BIT(9)
#define MCHP_MSVW02_SRC2_GIRQ_BIT BIT(10)
#define MCHP_MSVW02_SRC3_GIRQ_BIT BIT(11)
#define MCHP_MSVW03_SRC0_GIRQ_BIT BIT(12)
#define MCHP_MSVW03_SRC1_GIRQ_BIT BIT(13)
#define MCHP_MSVW03_SRC2_GIRQ_BIT BIT(14)
#define MCHP_MSVW03_SRC3_GIRQ_BIT BIT(15)
#define MCHP_MSVW04_SRC0_GIRQ_BIT BIT(16)
#define MCHP_MSVW04_SRC1_GIRQ_BIT BIT(17)
#define MCHP_MSVW04_SRC2_GIRQ_BIT BIT(18)
#define MCHP_MSVW04_SRC3_GIRQ_BIT BIT(19)
#define MCHP_MSVW05_SRC0_GIRQ_BIT BIT(20)
#define MCHP_MSVW05_SRC1_GIRQ_BIT BIT(21)
#define MCHP_MSVW05_SRC2_GIRQ_BIT BIT(22)
#define MCHP_MSVW05_SRC3_GIRQ_BIT BIT(23)
#define MCHP_MSVW06_SRC0_GIRQ_BIT BIT(24)
#define MCHP_MSVW06_SRC1_GIRQ_BIT BIT(25)
#define MCHP_MSVW06_SRC2_GIRQ_BIT BIT(26)
#define MCHP_MSVW06_SRC3_GIRQ_BIT BIT(27)
/* Masks for blocks with multiple instances or sources */
#define MCHP_MSVW00_GIRQ_MASK 0xFu
#define MCHP_MSVW01_GIRQ_MASK 0xF0u
#define MCHP_MSVW02_GIRQ_MASK 0xF00u
#define MCHP_MSVW03_GIRQ_MASK 0xF000u
#define MCHP_MSVW04_GIRQ_MASK 0xF0000u
#define MCHP_MSVW05_GIRQ_MASK 0xF00000u
#define MCHP_MSVW06_GIRQ_MASK 0xF000000u
#define MCHP_MSVW00_06_GIRQ_MASK 0x0FFFFFFFu
/* GIRQ25 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_MSVW07_SRC0_GIRQ_BIT BIT(0)
#define MCHP_MSVW07_SRC1_GIRQ_BIT BIT(1)
#define MCHP_MSVW07_SRC2_GIRQ_BIT BIT(2)
#define MCHP_MSVW07_SRC3_GIRQ_BIT BIT(3)
#define MCHP_MSVW08_SRC0_GIRQ_BIT BIT(4)
#define MCHP_MSVW08_SRC1_GIRQ_BIT BIT(5)
#define MCHP_MSVW08_SRC2_GIRQ_BIT BIT(6)
#define MCHP_MSVW08_SRC3_GIRQ_BIT BIT(7)
#define MCHP_MSVW09_SRC0_GIRQ_BIT BIT(8)
#define MCHP_MSVW09_SRC1_GIRQ_BIT BIT(9)
#define MCHP_MSVW09_SRC2_GIRQ_BIT BIT(10)
#define MCHP_MSVW09_SRC3_GIRQ_BIT BIT(11)
#define MCHP_MSVW10_SRC0_GIRQ_BIT BIT(12)
#define MCHP_MSVW10_SRC1_GIRQ_BIT BIT(13)
#define MCHP_MSVW10_SRC2_GIRQ_BIT BIT(14)
#define MCHP_MSVW10_SRC3_GIRQ_BIT BIT(15)
/* Masks for blocks with multiple instances or sources */
#define MCHP_MSVW07_GIRQ_MASK 0xFu
#define MCHP_MSVW08_GIRQ_MASK 0xF0u
#define MCHP_MSVW09_GIRQ_MASK 0xF00u
#define MCHP_MSVW10_GIRQ_MASK 0xF000u
#define MCHP_MSVW07_10_GIRQ_MASK 0xFFFFu
/* GIRQ26 Source, Enable_Set/Clr, Result registers bit positions */
#define MCHP_GPIO_0240_GIRQ_BIT BIT(0)
#define MCHP_GPIO_0241_GIRQ_BIT BIT(1)
#define MCHP_GPIO_0242_GIRQ_BIT BIT(2)
#define MCHP_GPIO_0243_GIRQ_BIT BIT(3)
#define MCHP_GPIO_0244_GIRQ_BIT BIT(4)
#define MCHP_GPIO_0245_GIRQ_BIT BIT(5)
#define MCHP_GPIO_0246_GIRQ_BIT BIT(6)
#define MCHP_GPIO_0250_GIRQ_BIT BIT(8)
#define MCHP_GPIO_0253_GIRQ_BIT BIT(11)
#define MCHP_GPIO_0254_GIRQ_BIT BIT(12)
#define MCHP_GPIO_0255_GIRQ_BIT BIT(13)
/* Masks for blocks with multiple instances or sources */
#define MCHP_GPIO_0240_0276_GIRQ_MASK 0x397Fu
/**
* @brief EC Interrupt Aggregator (ECIA)
@ -356,6 +770,7 @@ typedef struct girq_regs
uint8_t RSVD1[4];
} GIRQ_Type;
#if 0
typedef struct ecia_regs
{ /*!< (@ 0x4000E000) ECIA Structure */
GIRQ_Type GIRQ08; /*!< (@ 0x0000) GIRQ08 Source, Enable Set, Result, Enable Clear, Reserved */
@ -382,6 +797,39 @@ typedef struct ecia_regs
__IOM uint32_t BLK_EN_CLR; /*! (@ 0x00000204) Aggregated GIRQ output Enable Clear */
__IM uint32_t BLK_ACTIVE; /*! (@ 0x00000204) GIRQ Active bitmap (RO) */
} ECIA_Type;
#else
typedef struct ecia_regs
{ /*!< (@ 0x4000E000) ECIA Structure */
union {
struct {
GIRQ_Type GIRQ08; /*!< (@ 0x0000) GIRQ08 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ09; /*!< (@ 0x0014) GIRQ09 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ10; /*!< (@ 0x0028) GIRQ10 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ11; /*!< (@ 0x003C) GIRQ11 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ12; /*!< (@ 0x0050) GIRQ12 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ13; /*!< (@ 0x0064) GIRQ13 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ14; /*!< (@ 0x0078) GIRQ14 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ15; /*!< (@ 0x008C) GIRQ15 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ16; /*!< (@ 0x00A0) GIRQ16 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ17; /*!< (@ 0x00B4) GIRQ17 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ18; /*!< (@ 0x00C8) GIRQ18 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ19; /*!< (@ 0x00DC) GIRQ19 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ20; /*!< (@ 0x00F0) GIRQ20 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ21; /*!< (@ 0x0104) GIRQ21 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ22; /*!< (@ 0x0118) GIRQ22 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ23; /*!< (@ 0x012C) GIRQ23 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ24; /*!< (@ 0x0140) GIRQ24 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ25; /*!< (@ 0x0154) GIRQ25 Source, Enable Set, Result, Enable Clear, Reserved */
GIRQ_Type GIRQ26; /*!< (@ 0x0168) GIRQ26 Source, Enable Set, Result, Enable Clear, Reserved */
};
GIRQ_Type GIRQ[19];
};
uint8_t RSVD2[(0x0200ul - 0x017Cul)]; /* offsets 0x017C - 0x1FF */
__IOM uint32_t BLK_EN_SET; /*! (@ 0x00000200) Aggregated GIRQ output Enable Set */
__IOM uint32_t BLK_EN_CLR; /*! (@ 0x00000204) Aggregated GIRQ output Enable Clear */
__IM uint32_t BLK_ACTIVE; /*! (@ 0x00000204) GIRQ Active bitmap (RO) */
} ECIA_Type;
#endif
#endif // #ifndef _ECIA_H
/* end ecia.h */