ext : hal : Microchip MEC1501 PS/2 and global configuration updates.
Added header files for PS/2 and global configuration hardware blocks to MEC1501 HAL. Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit is contained in:
Scott Worley
Andrew Boie
parent
409325aaa0
commit
9e1d2a4a68
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@ -439,6 +439,7 @@ typedef enum IRQn {
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#include "component/espi_io.h"
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#include "component/espi_mem.h"
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#include "component/espi_vw.h"
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#include "component/global_cfg.h"
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#include "component/i2c.h"
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#include "component/kbc.h"
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#include "component/keyscan.h"
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@ -447,6 +448,7 @@ typedef enum IRQn {
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#include "component/pcr.h"
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#include "component/port80cap.h"
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#include "component/port92.h"
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#include "component/ps2_ctrl.h"
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#include "component/smb.h"
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#include "component/tfdp.h"
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#include "component/timer.h"
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@ -494,6 +496,9 @@ typedef enum IRQn {
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#define TFDP_REGS ((TFDP_Type *) TFDP_BASE)
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#define PS2_0_REGS ((PS2_Type *) PS2_0_BASE)
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#define PS2_1_REGS ((PS2_Type *) PS2_1_BASE)
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#define HTMR0_REGS ((HTMR_Type *) HTMR0_BASE)
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#define HTMR1_REGS ((HTMR_Type *) HTMR1_BASE)
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@ -584,6 +589,8 @@ typedef enum IRQn {
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#define PORT80_CAP0_REGS ((PORT80_CAP_Type *)(P80CAP0_BASE))
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#define PORT80_CAP1_REGS ((PORT80_CAP_Type *)(P80CAP1_BASE))
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#define GLOBAL_CFG_REGS ((GLOBAL_CFG_Type *) GCFG_BASE)
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/** @} *//* End of group MEC1501 */
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/** @} *//* End of group MCHP */
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@ -0,0 +1,158 @@
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/**
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*
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* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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/** @file global_cfg.h
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*MEC1501 Global Configuration Registers
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*/
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/** @defgroup MEC1501 Peripherals GlobalConfig
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*/
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#ifndef _GLOBAL_CFG_H
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#define _GLOBAL_CFG_H
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#include <stdint.h>
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#include <stddef.h>
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#include "regaccess.h"
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/* ===================================================================*/
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/* ================ Global Config ============= */
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/* ===================================================================*/
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#define MCHP_GCFG_BASE_ADDR 0x400FFF00ul
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/*
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* Device and Revision ID 32-bit register
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* b[7:0] = Revision
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* b[15:8] = Device Sub-ID
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* b[31:16] = Device ID
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* This register can be accesses as bytes or a single 32-bit read from
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* the EC. Host access byte access via the Host visible configuration
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* register space at 0x2E/0x2F(default).
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*/
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#define MCHP_GCFG_DEV_ID_REG32_OFS 0x1C
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#define MCHP_GCFG_DEV_ID_REG_MASK 0xFFFFFFFFul
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#define MCHP_GCFG_REV_ID_POS 0
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#define MCHP_GCFG_DID_REV_MASK0 0xFFul
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#define MCHP_GCFG_DID_REV_MASK 0xFFul
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#define MCHP_GCFG_DID_SUB_ID_POS 8
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#define MCHP_GCFG_DID_SUB_ID_MASK0 0xFFul
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#define MCHP_GCFG_DID_SUB_ID_MASK (0xFFul << 8)
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#define MCHP_GCFG_DID_DEV_ID_POS 16
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#define MCHP_GCFG_DID_DEV_ID_MASK0 0xFFFFul
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#define MCHP_GCFG_DID_DEV_ID_MASK (0xFFFFul << 16)
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/* Byte[0] at offset 0x1C is the 8-bit revision ID */
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#define MCHP_GCFG_REV_ID_REG_OFS 0x1C
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#define MCHP_GCFG_REV_A1 0x02
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#define MCHP_GCFG_REV_B0 0x03
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/*
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* Byte[1] at offset 0x1D is the 8-bit Sub-ID
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* bits[3:0] = package type
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* bits[7:4] = chip family
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*/
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#define MCHP_GCFG_SUB_ID_OFS 0x1D
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#define MCHP_GCFG_SUB_ID_PKG_POS 0
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#define MCHP_GCFG_SUB_ID_PKG_MASK0 0x0F
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#define MCHP_GCFG_SUB_ID_PKG_MASK 0x0F
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#define MCHP_GCFG_SUB_ID_PKG_UNDEF 0x00
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#define MCHP_GCFG_SUB_ID_PKG_64_PIN 0x01
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#define MCHP_GCFG_SUB_ID_PKG_84_PIN 0x02
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#define MCHP_GCFG_SUB_ID_PKG_128_PIN 0x03
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#define MCHP_GCFG_SUB_ID_PKG_144_PIN 0x04
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/* chip family field */
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#define MCHP_GCFG_SUB_ID_FAM_POS 4
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#define MCHP_GCFG_SUB_ID_FAM_MASK0 0x0F
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#define MCHP_GCFG_SUB_ID_FAM_MASK 0xF0
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#define MCHP_GCFG_SUB_ID_FAM_UNDEF 0x00
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#define MCHP_GCFG_SUB_ID_FAM_MEC 0x01
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#define MCHP_GCFG_SUB_ID_FAM_2 0x02
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#define MCHP_GCFG_SUB_ID_FAM_3 0x03
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#define MCHP_GCFG_SUB_ID_FAM_4 0x04
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#define MCHP_GCFG_SUB_ID_FAM_5 0x05
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#define MCHP_GCFG_DEV_ID_LSB_OFS 0x1E
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#define MCHP_GCFG_DEV_ID_MSB_OFS 0x1F
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#define MCHP_GCFG_DEV_ID_15XX 0x0020
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#define MCHP_GCFG_DEV_ID_15XX_LSB 0x20
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#define MCHP_GCFG_DEV_ID_15XX_MSB 0x00
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/* Legacy Device ID value */
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#define MCHP_CCFG_LEGACY_DID_REG_OFS 0x20
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#define MCHP_GCFG_LEGACY_DEV_ID 0xFE
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/*
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* Host access via configuration port (default I/O locations 0x2E/0x2F)
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*/
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#define MCHP_HOST_CFG_INDEX_IO_DFLT 0x2E
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#define MCHP_HOST_CFG_DATA_IO_DFLT 0x2F
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#define MCHP_HOST_CFG_UNLOCK 0x55
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#define MCHP_HOST_CFG_LOCK 0xAA
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/*
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* Logical Device Configuration Indices.
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*/
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#define MCHP_HOST_CFG_LDN_IDX 0x07
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#define MCHP_HOST_CFG_LD_ACTIVATE_IDX 0x30
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#define MCHP_HOST_CFG_LD_BASE_ADDR_IDX 0x34
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#define MCHP_HOST_CFG_LD_CFG_SEL_IDX 0xF0
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/* Read 32-bit Device, Sub, and Revision ID */
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#define MCHP_DEVICE_REV_ID() \
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REG32(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_DEV_ID_REG32_OFS)
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/* Read 16-bit Device ID */
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#define MCHP_DEVICE_ID() \
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REG16(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_DEV_ID_LSB_OFS)
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/* Read 8-bit Sub ID */
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#define MCHP_DEV_SUB_ID() \
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REG8(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_SUB_ID_OFS)
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/* Read 8-bit Revision ID */
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#define MCHP_REVISION_ID() \
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REG8(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_REV_ID_REG_OFS)
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/**
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* @brief Glocal Configuration Registers (GLOBAL_CFG)
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*/
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typedef struct global_cfg_regs
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{
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__IOM uint8_t RSVD0[2];
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__IOM uint8_t TEST02; /*!< (@ 0x0002) MCHP Test */
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__IOM uint8_t RSVD1[4];
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__IOM uint8_t LOG_DEV_NUM; /*!< (@ 0x0007) Global Config Logical Device Number */
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__IOM uint8_t RSVD2[20];
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__IOM uint32_t DEV_REV_ID; /*!< (@ 0x001C) Device and revision ID */
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__IOM uint8_t LEGACY_DEV_ID; /*!< (@ 0x0020) Legacy Device ID */
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__IOM uint8_t RSVD3[14];
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} GLOBAL_CFG_Type;
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#endif /* #ifndef _GLOBAL_CFG_H */
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/* end global_cfg.h */
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/** @}
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*/
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@ -0,0 +1,168 @@
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/**
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*
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* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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/** @file ps2_ctrl.h
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*MEC1501 PS/2 Controller Registers
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*/
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/** @defgroup MEC1501 Peripherals PS/2
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*/
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#ifndef _PS2_CTRL_H
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#define _PS2_CTRL_H
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#include <stdint.h>
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#include <stddef.h>
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#include "regaccess.h"
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/* ===================================================================*/
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/* ================ PS2 ============= */
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/* ===================================================================*/
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#define MCHP_PS2_MAX_INSTANCES 2u
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#define MCHP_PS2_SPACING 0x40ul
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#define MCHP_PS2_SPACING_PWROF2 6u
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#define MCHP_PS2_0_BASE_ADDR 0x40009000ul
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#define MCHP_PS2_1_BASE_ADDR 0x40009040ul
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/*
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* PS2 interrupts
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*/
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#define MCHP_PS2_0_GIRQ 18u
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#define MCHP_PS2_1_GIRQ 18u
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#define MCHP_PS2_0_GIRQ_NVIC 10u
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#define MCHP_PS2_1_GIRQ_NVIC 10u
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#define MCHP_PS2_0_NVIC_DIRECT 100u
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#define MCHP_PS2_1_NVIC_DIRECT 101u
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#define MCHP_PS2_0_GIRQ_POS 10u
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#define MCHP_PS2_1_GIRQ_POS 11u
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#define MCHP_PS2_0_GIRQ_VAL (1ul << 10)
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#define MCHP_PS2_1_GIRQ_VAL (1ul << 11)
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/*
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* PS2 TRX Buffer register
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* Writes -> Transmit buffer
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* Read <- Receive buffer
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*/
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#define MCHP_PS2_TRX_BUFF_REG_MASK 0xFFUL
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/*
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* PS2 Control register
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*/
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#define MCHP_PS2_CTRL_REG_MASK 0x3FUL
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/* Select Transmit or Receive */
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#define MCHP_PS2_CTRL_TR_POS 0
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#define MCHP_PS2_CTRL_TR_RX (0U << (MCHP_PS2_CTRL_TR_POS))
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#define MCHP_PS2_CTRL_TR_TX (1U << (MCHP_PS2_CTRL_TR_POS))
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/* Enable PS2 state machine */
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#define MCHP_PS2_CTRL_EN_POS 1
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#define MCHP_PS2_CTRL_EN (1U << (MCHP_PS2_CTRL_EN_POS))
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/* Protocol parity selection */
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#define MCHP_PS2_CTRL_PAR_POS 2
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#define MCHP_PS2_CTRL_PAR_MASK0 0x03U
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#define MCHP_PS2_CTRL_PAR_MASK ((MCHP_PS2_CTRL_PAR_MASK0) \
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<< (MCHP_PS2_CTRL_PAR_POS))
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#define MCHP_PS2_CTRL_PAR_ODD (0U << (MCHP_PS2_CTRL_PAR_POS))
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#define MCHP_PS2_CTRL_PAR_EVEN (1U << (MCHP_PS2_CTRL_PAR_POS))
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#define MCHP_PS2_CTRL_PAR_IGNORE (2U << (MCHP_PS2_CTRL_PAR_POS))
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#define MCHP_PS2_CTRL_PAR_RSVD (3U << (MCHP_PS2_CTRL_PAR_POS))
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/* Protocol stop bit selection */
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#define MCHP_PS2_CTRL_STOP_POS 4
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#define MCHP_PS2_CTRL_STOP_MASK0 0x03U
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#define MCHP_PS2_CTRL_STOP_MASK ((MCHP_PS2_CTRL_STOP_MASK0) \
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<< (MCHP_PS2_CTRL_STOP_POS))
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#define MCHP_PS2_CTRL_STOP_ACT_HI (0U << (MCHP_PS2_CTRL_STOP_POS))
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#define MCHP_PS2_CTRL_STOP_ACT_LO (1U << (MCHP_PS2_CTRL_STOP_POS))
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#define MCHP_PS2_CTRL_STOP_IGNORE (2U << (MCHP_PS2_CTRL_STOP_POS))
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#define MCHP_PS2_CTRL_STOP_RSVD (3U << (MCHP_PS2_CTRL_STOP_POS))
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/*
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* PS2 Status register
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*/
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#define MCHP_PS2_STATUS_REG_MASK 0xFFUL
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#define MCHP_PS2_STATUS_RW1C_MASK 0xAEUL
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#define MCHP_PS2_STATUS_RO_MASK 0x51UL
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/* RX Data Ready(Read-Only) */
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#define MCHP_PS2_STATUS_RXD_RDY_POS 0
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#define MCHP_PS2_STATUS_RXD_RDY (1U << (MCHP_PS2_STATUS_RXD_RDY_POS))
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/* RX Timeout(R/W1C) */
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#define MCHP_PS2_STATUS_RX_TMOUT_POS 1
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#define MCHP_PS2_STATUS_RX_TMOUT (1U << (MCHP_PS2_STATUS_RX_TMOUT_POS))
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/* Parity Error(R/W1C) */
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#define MCHP_PS2_STATUS_PE_POS 2
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#define MCHP_PS2_STATUS_PE (1U << (MCHP_PS2_STATUS_PE_POS))
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/* Framing Error(R/W1C) */
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#define MCHP_PS2_STATUS_FE_POS 3
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#define MCHP_PS2_STATUS_FE (1U << (MCHP_PS2_STATUS_FE_POS))
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/* Transmitter is Idle(Read-Only) */
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#define MCHP_PS2_STATUS_TX_IDLE_POS 4
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#define MCHP_PS2_STATUS_TX_IDLE (1U << (MCHP_PS2_STATUS_TX_IDLE_POS))
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/* Transmitter timeout(R/W1C) */
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#define MCHP_PS2_STATUS_TX_TMOUT_POS 5
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#define MCHP_PS2_STATUS_TX_TMOUT (1U << (MCHP_PS2_STATUS_TX_TMOUT_POS))
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/* RX is Busy(Read-Only) */
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#define MCHP_PS2_STATUS_RX_BUSY_POS 6
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#define MCHP_PS2_STATUS_RX_BUSY (1U << (MCHP_PS2_STATUS_RX_BUSY_POS))
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/* Transmitter start timeout(R/W1C) */
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#define MCHP_PS2_STATUS_TX_ST_TMOUT_POS 7
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#define MCHP_PS2_STATUS_TX_ST_TMOUT (1U << (MCHP_PS2_STATUS_TX_ST_TMOUT_POS))
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/*
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* PS2 Protocol bit positions
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*/
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#define MCHP_PS2_PROT_START_BIT_POS 1
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#define MCHP_PS2_PROT_DATA_BIT0_POS 2
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#define MCHP_PS2_PROT_DATA_BIT1_POS 3
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#define MCHP_PS2_PROT_DATA_BIT2_POS 4
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#define MCHP_PS2_PROT_DATA_BIT3_POS 5
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#define MCHP_PS2_PROT_DATA_BIT4_POS 6
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#define MCHP_PS2_PROT_DATA_BIT5_POS 7
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#define MCHP_PS2_PROT_DATA_BIT6_POS 8
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#define MCHP_PS2_PROT_DATA_BIT7_POS 9
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#define MCHP_PS2_PROT_PARITY_POS 10
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#define MCHP_PS2_PROT_STOP_BIT_POS 11
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/**
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* @brief PS/2 Controller Registers (PS2)
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*/
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typedef struct ps2_regs
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{
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__IOM uint32_t TRX_BUFF; /*!< (@ 0x0000) PS/2 Transmit buffer(WO), Receive buffer(RO) */
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__IOM uint32_t CTRL; /*!< (@ 0x0004) PS/2 Control */
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__IOM uint32_t STATUS; /*!< (@ 0x0008) PS/2 Status */
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} PS2_Type;
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#endif /* #ifndef _PS2_CTRL_H */
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/* end ps2_ctrl.h */
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/** @}
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*/
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