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modules: microchip: mpfs: Adding Polarfire SoC mpfs hal

Browse source 
Origin https://github.com/polarfire-soc/platform

Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
This commit is contained in:
Peter Mc Shane 2021-12-22 16:54:49 +00:00 committed by jvasanth1
parent 870d05e6a6
commit 3ac6315ede
204 changed files with 138371 additions and 0 deletions
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16
mpfs/CMakeLists.txt Normal file
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#
# Copyright (c) 2021, Microchip Technology Inc.
#
# SPDX-License-Identifier: Apache-2.0
#
zephyr_include_directories(.)
zephyr_include_directories(hal)
zephyr_include_directories(mpfs_hal)
zephyr_include_directories(boards/icicle-kit-es)
zephyr_include_directories(boards/icicle-kit-es/platform_config)
zephyr_include_directories(mpfs_hal/common)
zephyr_include_directories(mpfs_hal/common/nwc)
add_subdirectory(drivers/mss/mss_gpio)
add_subdirectory(mpfs_hal/common)

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mpfs/boards/icicle-kit-es/fpga_design/design_description/ICICLE_MSS_eMMC_cfg.xml Normal file
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mpfs/boards/icicle-kit-es/fpga_design/design_description/ICICLE_MSS_mss_cfg.xml Normal file
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197
mpfs/boards/icicle-kit-es/fpga_design_config/clocks/hw_clk_ddr_pll.h Normal file
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_ddr_pll.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_DDR_PLL_H_
#define HW_CLK_DDR_PLL_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_DDR_SOFT_RESET)
/*This is a compulsory register for all SCB slaves and must be at the same
offset in all slaves to facilitate global soft reset of all SCB registers with
a single broadcast write from the SCB master. */
#define LIBERO_SETTING_DDR_SOFT_RESET 0x00000000UL
/* NV_MAP [0:1] RST */
/* V_MAP [1:1] RST */
/* PERIPH [8:1] RST */
/* BLOCKID [16:16] ID */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_CTRL)
/*PLL control register */
#define LIBERO_SETTING_DDR_PLL_CTRL 0x0100003FUL
/* REG_POWERDOWN_B [0:1] RW value= 0x1 */
/* REG_RFDIV_EN [1:1] RW value= 0x1 */
/* REG_DIVQ0_EN [2:1] RW value= 0x1 */
/* REG_DIVQ1_EN [3:1] RW value= 0x1 */
/* REG_DIVQ2_EN [4:1] RW value= 0x1 */
/* REG_DIVQ3_EN [5:1] RW value= 0x1 */
/* REG_RFCLK_SEL [6:1] RW value= 0x0 */
/* RESETONLOCK [7:1] RW value= 0x0 */
/* BYPCK_SEL [8:4] RW value= 0x0 */
/* REG_BYPASS_GO_B [12:1] RW value= 0x0 */
/* RESERVE10 [13:3] RSVD */
/* REG_BYPASSPRE [16:4] RW value= 0x0 */
/* REG_BYPASSPOST [20:4] RW value= 0x0 */
/* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */
/* LOCK [25:1] RO */
/* LOCK_INT_EN [26:1] RW value= 0x0 */
/* UNLOCK_INT_EN [27:1] RW value= 0x0 */
/* LOCK_INT [28:1] SW1C */
/* UNLOCK_INT [29:1] SW1C */
/* RESERVE11 [30:1] RSVD */
/* LOCK_B [31:1] RO */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_REF_FB)
/*PLL reference and feedback registers */
#define LIBERO_SETTING_DDR_PLL_REF_FB 0x00000500UL
/* FSE_B [0:1] RW value= 0x0 */
/* FBCK_SEL [1:2] RW value= 0x0 */
/* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */
/* RESERVE12 [4:4] RSVD */
/* RFDIV [8:6] RW value= 0x5 */
/* RESERVE13 [14:2] RSVD */
/* RESERVE14 [16:12] RSVD */
/* RESERVE15 [28:4] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_FRACN)
/*PLL fractional register */
#define LIBERO_SETTING_DDR_PLL_FRACN 0x00000000UL
/* FRACN_EN [0:1] RW value= 0x0 */
/* FRACN_DAC_EN [1:1] RW value= 0x0 */
/* RESERVE16 [2:6] RSVD */
/* RESERVE17 [8:24] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_DIV_0_1)
/*PLL 0/1 division registers */
#define LIBERO_SETTING_DDR_PLL_DIV_0_1 0x02000100UL
/* VCO0PH_SEL [0:3] RO */
/* DIV0_START [3:3] RW value= 0x0 */
/* RESERVE18 [6:2] RSVD */
/* POST0DIV [8:7] RW value= 0x1 */
/* RESERVE19 [15:1] RSVD */
/* VCO1PH_SEL [16:3] RO */
/* DIV1_START [19:3] RW value= 0x0 */
/* RESERVE20 [22:2] RSVD */
/* POST1DIV [24:7] RW value= 0x2 */
/* RESERVE21 [31:1] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_DIV_2_3)
/*PLL 2/3 division registers */
#define LIBERO_SETTING_DDR_PLL_DIV_2_3 0x01000100UL
/* VCO2PH_SEL [0:3] RO */
/* DIV2_START [3:3] RW value= 0x0 */
/* RESERVE22 [6:2] RSVD */
/* POST2DIV [8:7] RW value= 0x1 */
/* RESERVE23 [15:1] RSVD */
/* VCO3PH_SEL [16:3] RO */
/* DIV3_START [19:3] RW value= 0x0 */
/* RESERVE24 [22:2] RSVD */
/* POST3DIV [24:7] RW value= 0x1 */
/* CKPOST3_SEL [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_CTRL2)
/*PLL control register */
#define LIBERO_SETTING_DDR_PLL_CTRL2 0x00001020UL
/* BWI [0:2] RW value= 0x0 */
/* BWP [2:2] RW value= 0x0 */
/* IREF_EN [4:1] RW value= 0x0 */
/* IREF_TOGGLE [5:1] RW value= 0x1 */
/* RESERVE25 [6:3] RSVD */
/* LOCKCNT [9:4] RW value= 0x8 */
/* RESERVE26 [13:4] RSVD */
/* ATEST_EN [17:1] RW value= 0x0 */
/* ATEST_SEL [18:3] RW value= 0x0 */
/* RESERVE27 [21:11] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_CAL)
/*PLL calibration register */
#define LIBERO_SETTING_DDR_PLL_CAL 0x00000D06UL
/* DSKEWCALCNT [0:3] RW value= 0x6 */
/* DSKEWCAL_EN [3:1] RW value= 0x0 */
/* DSKEWCALBYP [4:1] RW value= 0x0 */
/* RESERVE28 [5:3] RSVD */
/* DSKEWCALIN [8:7] RW value= 0xd */
/* RESERVE29 [15:1] RSVD */
/* DSKEWCALOUT [16:7] RO */
/* RESERVE30 [23:9] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_PHADJ)
/*PLL phase registers */
#define LIBERO_SETTING_DDR_PLL_PHADJ 0x00005003UL
/* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */
/* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */
/* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */
/* REG_OUT1_PHSINIT [5:3] RW value= 0x0 */
/* REG_OUT2_PHSINIT [8:3] RW value= 0x0 */
/* REG_OUT3_PHSINIT [11:3] RW value= 0x2 */
/* REG_LOADPHS_B [14:1] RW value= 0x1 */
/* RESERVE31 [15:17] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_SSCG_REG_0)
/*SSCG registers 0 */
#define LIBERO_SETTING_DDR_SSCG_REG_0 0x00000000UL
/* DIVVAL [0:6] RW value= 0x0 */
/* FRACIN [6:24] RW value= 0x0 */
/* RESERVE00 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_SSCG_REG_1)
/*SSCG registers 1 */
#define LIBERO_SETTING_DDR_SSCG_REG_1 0x00000000UL
/* DOWNSPREAD [0:1] RW value= 0x0 */
/* SSMD [1:5] RW value= 0x0 */
/* FRACMOD [6:24] RO */
/* RESERVE01 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_SSCG_REG_2)
/*SSCG registers 2 */
#define LIBERO_SETTING_DDR_SSCG_REG_2 0x00000080UL
/* INTIN [0:12] RW value= 0x80 */
/* INTMOD [12:12] RO */
/* RESERVE02 [24:8] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_SSCG_REG_3)
/*SSCG registers 3 */
#define LIBERO_SETTING_DDR_SSCG_REG_3 0x00000001UL
/* SSE_B [0:1] RW value= 0x1 */
/* SEL_EXTWAVE [1:2] RW value= 0x0 */
/* EXT_MAXADDR [3:8] RW value= 0x0 */
/* TBLADDR [11:8] RO */
/* RANDOM_FILTER [19:1] RW value= 0x0 */
/* RANDOM_SEL [20:2] RW value= 0x0 */
/* RESERVE03 [22:1] RSVD */
/* RESERVE04 [23:9] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_DDR_PLL_H_ */

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mpfs/boards/icicle-kit-es/fpga_design_config/clocks/hw_clk_mss_cfm.h Normal file
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_mss_cfm.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_MSS_CFM_H_
#define HW_CLK_MSS_CFM_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_MSS_BCLKMUX)
/*Input mux selections */
#define LIBERO_SETTING_MSS_BCLKMUX 0x00000208UL
/* BCLK0_SEL [0:5] RW value= 0x8 */
/* BCLK1_SEL [5:5] RW value= 0x10 */
/* BCLK2_SEL [10:5] RW value= 0x0 */
/* BCLK3_SEL [15:5] RW value= 0x0 */
/* BCLK4_SEL [20:5] RW value= 0x0 */
/* BCLK5_SEL [25:5] RW value= 0x0 */
/* RESERVED [30:2] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_CKMUX)
/*Input mux selections */
#define LIBERO_SETTING_MSS_PLL_CKMUX 0x00000155UL
/* CLK_IN_MAC_TSU_SEL [0:2] RW value= 0x1 */
/* PLL0_RFCLK0_SEL [2:2] RW value= 0x1 */
/* PLL0_RFCLK1_SEL [4:2] RW value= 0x1 */
/* PLL1_RFCLK0_SEL [6:2] RW value= 0x1 */
/* PLL1_RFCLK1_SEL [8:2] RW value= 0x1 */
/* PLL1_FDR_SEL [10:5] RW value= 0x0 */
/* RESERVED [15:17] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSS_MSSCLKMUX)
/*MSS Clock mux selections */
#define LIBERO_SETTING_MSS_MSSCLKMUX 0x00000003UL
/* MSSCLK_MUX_SEL [0:2] RW value= 0x3 */
/* MSSCLK_MUX_MD [2:2] RW value= 0x0 */
/* CLK_STANDBY_SEL [4:1] RW value= 0x0 */
/* RESERVED [5:27] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSS_SPARE0)
/*spare logic */
#define LIBERO_SETTING_MSS_SPARE0 0x00000000UL
/* SPARE0 [0:32] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSS_FMETER_ADDR)
/*Frequency_meter_address_selections */
#define LIBERO_SETTING_MSS_FMETER_ADDR 0x00000000UL
/* ADDR10 [0:2] RSVD */
/* ADDR [2:4] RW value= 0x0 */
/* RESERVE18 [6:26] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_FMETER_DATAW)
/*Frequency_meter_data_write */
#define LIBERO_SETTING_MSS_FMETER_DATAW 0x00000000UL
/* DATA [0:24] RW value= 0x0 */
/* STROBE [24:1] W1P */
/* RESERVE19 [25:7] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_FMETER_DATAR)
/*Frequency_meter_data_read */
#define LIBERO_SETTING_MSS_FMETER_DATAR 0x00000000UL
/* DATA [0:24] RO */
/* RESERVE20 [24:8] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_IMIRROR_TRIM)
/*Imirror TRIM Bits */
#define LIBERO_SETTING_MSS_IMIRROR_TRIM 0x00000000UL
/* BG_CODE [0:3] RW value= 0x0 */
/* CC_CODE [3:8] RW value= 0x0 */
/* RESERVE21 [11:21] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_TEST_CTRL)
/*Test MUX Controls */
#define LIBERO_SETTING_MSS_TEST_CTRL 0x00000000UL
/* OSC_ENABLE [0:4] RW value= 0x0 */
/* ATEST_EN [4:1] RW value= 0x0 */
/* ATEST_SEL [5:5] RW value= 0x0 */
/* DTEST_EN [10:1] RW value= 0x0 */
/* DTEST_SEL [11:5] RW value= 0x0 */
/* RESERVE22 [16:16] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_MSS_CFM_H_ */

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mpfs/boards/icicle-kit-es/fpga_design_config/clocks/hw_clk_mss_pll.h Normal file
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_mss_pll.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_MSS_PLL_H_
#define HW_CLK_MSS_PLL_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_CTRL)
/*PLL control register */
#define LIBERO_SETTING_MSS_PLL_CTRL 0x01000037UL
/* REG_POWERDOWN_B [0:1] RW value= 0x1 */
/* REG_RFDIV_EN [1:1] RW value= 0x1 */
/* REG_DIVQ0_EN [2:1] RW value= 0x1 */
/* REG_DIVQ1_EN [3:1] RW value= 0x0 */
/* REG_DIVQ2_EN [4:1] RW value= 0x1 */
/* REG_DIVQ3_EN [5:1] RW value= 0x1 */
/* REG_RFCLK_SEL [6:1] RW value= 0x0 */
/* RESETONLOCK [7:1] RW value= 0x0 */
/* BYPCK_SEL [8:4] RW value= 0x0 */
/* REG_BYPASS_GO_B [12:1] RW value= 0x0 */
/* RESERVE10 [13:3] RSVD */
/* REG_BYPASSPRE [16:4] RW value= 0x0 */
/* REG_BYPASSPOST [20:4] RW value= 0x0 */
/* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */
/* LOCK [25:1] RO */
/* LOCK_INT_EN [26:1] RW value= 0x0 */
/* UNLOCK_INT_EN [27:1] RW value= 0x0 */
/* LOCK_INT [28:1] SW1C */
/* UNLOCK_INT [29:1] SW1C */
/* RESERVE11 [30:1] RSVD */
/* LOCK_B [31:1] RO */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_REF_FB)
/*PLL reference and feedback registers */
#define LIBERO_SETTING_MSS_PLL_REF_FB 0x00000500UL
/* FSE_B [0:1] RW value= 0x0 */
/* FBCK_SEL [1:2] RW value= 0x0 */
/* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */
/* RESERVE12 [4:4] RSVD */
/* RFDIV [8:6] RW value= 0x5 */
/* RESERVE13 [14:2] RSVD */
/* RESERVE14 [16:12] RSVD */
/* RESERVE15 [28:4] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_FRACN)
/*PLL fractional register */
#define LIBERO_SETTING_MSS_PLL_FRACN 0x00000000UL
/* FRACN_EN [0:1] RW value= 0x0 */
/* FRACN_DAC_EN [1:1] RW value= 0x0 */
/* RESERVE16 [2:6] RSVD */
/* RESERVE17 [8:24] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_DIV_0_1)
/*PLL 0/1 division registers */
#define LIBERO_SETTING_MSS_PLL_DIV_0_1 0x01000200UL
/* VCO0PH_SEL [0:3] RO */
/* DIV0_START [3:3] RW value= 0x0 */
/* RESERVE18 [6:2] RSVD */
/* POST0DIV [8:7] RW value= 0x2 */
/* RESERVE19 [15:1] RSVD */
/* VCO1PH_SEL [16:3] RO */
/* DIV1_START [19:3] RW value= 0x0 */
/* RESERVE20 [22:2] RSVD */
/* POST1DIV [24:7] RW value= 0x1 */
/* RESERVE21 [31:1] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_DIV_2_3)
/*PLL 2/3 division registers */
#define LIBERO_SETTING_MSS_PLL_DIV_2_3 0x0F000600UL
/* VCO2PH_SEL [0:3] RO */
/* DIV2_START [3:3] RW value= 0x0 */
/* RESERVE22 [6:2] RSVD */
/* POST2DIV [8:7] RW value= 0x6 */
/* RESERVE23 [15:1] RSVD */
/* VCO3PH_SEL [16:3] RO */
/* DIV3_START [19:3] RW value= 0x0 */
/* RESERVE24 [22:2] RSVD */
/* POST3DIV [24:7] RW value= 0xF */
/* CKPOST3_SEL [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_CTRL2)
/*PLL control register */
#define LIBERO_SETTING_MSS_PLL_CTRL2 0x00001020UL
/* BWI [0:2] RW value= 0x0 */
/* BWP [2:2] RW value= 0x0 */
/* IREF_EN [4:1] RW value= 0x0 */
/* IREF_TOGGLE [5:1] RW value= 0x1 */
/* RESERVE25 [6:3] RSVD */
/* LOCKCNT [9:4] RW value= 0x8 */
/* RESERVE26 [13:4] RSVD */
/* ATEST_EN [17:1] RW value= 0x0 */
/* ATEST_SEL [18:3] RW value= 0x0 */
/* RESERVE27 [21:11] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_CAL)
/*PLL calibration register */
#define LIBERO_SETTING_MSS_PLL_CAL 0x00000D06UL
/* DSKEWCALCNT [0:3] RW value= 0x6 */
/* DSKEWCAL_EN [3:1] RW value= 0x0 */
/* DSKEWCALBYP [4:1] RW value= 0x0 */
/* RESERVE28 [5:3] RSVD */
/* DSKEWCALIN [8:7] RW value= 0xd */
/* RESERVE29 [15:1] RSVD */
/* DSKEWCALOUT [16:7] RO */
/* RESERVE30 [23:9] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_PHADJ)
/*PLL phase registers */
#define LIBERO_SETTING_MSS_PLL_PHADJ 0x00004003UL
/* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */
/* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */
/* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */
/* REG_OUT1_PHSINIT [5:3] RW value= 0x0 */
/* REG_OUT2_PHSINIT [8:3] RW value= 0x0 */
/* REG_OUT3_PHSINIT [11:3] RW value= 0x8 */
/* REG_LOADPHS_B [14:1] RW value= 0x0 */
/* RESERVE31 [15:17] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_SSCG_REG_0)
/*SSCG registers 0 */
#define LIBERO_SETTING_MSS_SSCG_REG_0 0x00000000UL
/* DIVVAL [0:6] RW value= 0x0 */
/* FRACIN [6:24] RW value= 0x0 */
/* RESERVE00 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_SSCG_REG_1)
/*SSCG registers 1 */
#define LIBERO_SETTING_MSS_SSCG_REG_1 0x00000000UL
/* DOWNSPREAD [0:1] RW value= 0x0 */
/* SSMD [1:5] RW value= 0x0 */
/* FRACMOD [6:24] RO */
/* RESERVE01 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_SSCG_REG_2)
/*SSCG registers 2 */
#define LIBERO_SETTING_MSS_SSCG_REG_2 0x000000C0UL
/* INTIN [0:12] RW value= 0xC0 */
/* INTMOD [12:12] RO */
/* RESERVE02 [24:8] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_SSCG_REG_3)
/*SSCG registers 3 */
#define LIBERO_SETTING_MSS_SSCG_REG_3 0x00000001UL
/* SSE_B [0:1] RW value= 0x1 */
/* SEL_EXTWAVE [1:2] RW value= 0x0 */
/* EXT_MAXADDR [3:8] RW value= 0x0 */
/* TBLADDR [11:8] RO */
/* RANDOM_FILTER [19:1] RW value= 0x0 */
/* RANDOM_SEL [20:2] RW value= 0x0 */
/* RESERVE03 [22:1] RSVD */
/* RESERVE04 [23:9] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_MSS_PLL_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_sgmii_cfm.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_SGMII_CFM_H_
#define HW_CLK_SGMII_CFM_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_SGMII_REFCLKMUX)
/*Input mux selections */
#define LIBERO_SETTING_SGMII_REFCLKMUX 0x00000005UL
/* PLL0_RFCLK0_SEL [0:2] RW value= 0x1 */
/* PLL0_RFCLK1_SEL [2:2] RW value= 0x1 */
/* RESERVED [4:28] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SGMII_SGMII_CLKMUX)
/*sgmii clk mux */
#define LIBERO_SETTING_SGMII_SGMII_CLKMUX 0x00000005UL
/* SGMII_CLKMUX [0:32] RW value= 0x5 */
#endif
#if !defined (LIBERO_SETTING_SGMII_SPARE0)
/*spare logic */
#define LIBERO_SETTING_SGMII_SPARE0 0x00000000UL
/* RESERVED [0:32] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SGMII_CLK_XCVR)
/*Clock_Receiver */
#define LIBERO_SETTING_SGMII_CLK_XCVR 0x00002C30UL
/* EN_UDRIVE_P [0:1] RW value= 0x0 */
/* EN_INS_HYST_P [1:1] RW value= 0x0 */
/* EN_TERM_P [2:2] RW value= 0x0 */
/* EN_RXMODE_P [4:2] RW value= 0x3 */
/* EN_UDRIVE_N [6:1] RW value= 0x0 */
/* EN_INS_HYST_N [7:1] RW value= 0x0 */
/* EN_TERM_N [8:2] RW value= 0x0 */
/* EN_RXMODE_N [10:2] RW value= 0x3 */
/* CLKBUF_EN_PULLUP [12:1] RW value= 0x0 */
/* EN_RDIFF [13:1] RW value= 0x1 */
/* RESERVED [14:18] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SGMII_TEST_CTRL)
/*Test MUX Controls */
#define LIBERO_SETTING_SGMII_TEST_CTRL 0x00000000UL
/* OSC_ENABLE [0:4] RW value= 0x0 */
/* ATEST_EN [4:1] RW value= 0x0 */
/* ATEST_SEL [5:5] RW value= 0x0 */
/* DTEST_EN [10:1] RW value= 0x0 */
/* DTEST_SEL [11:5] RW value= 0x0 */
/* RESERVE22 [16:16] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_SGMII_CFM_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_sgmii_pll.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_SGMII_PLL_H_
#define HW_CLK_SGMII_PLL_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_SGMII_SOFT_RESET)
/*This is a compulsory register for all SCB slaves and must be at the same
offset in all slaves to facilitate global soft reset of all SCB registers with
a single broadcast write from the SCB master. */
#define LIBERO_SETTING_SGMII_SOFT_RESET 0x00000000UL
/* NV_MAP [0:1] RST */
/* V_MAP [1:1] RST */
/* PERIPH [8:1] RST */
/* BLOCKID [16:16] ID */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_CTRL)
/*PLL control register */
#define LIBERO_SETTING_SGMII_PLL_CTRL 0x0100003FUL
/* REG_POWERDOWN_B [0:1] RW value= 0x1 */
/* REG_RFDIV_EN [1:1] RW value= 0x1 */
/* REG_DIVQ0_EN [2:1] RW value= 0x1 */
/* REG_DIVQ1_EN [3:1] RW value= 0x1 */
/* REG_DIVQ2_EN [4:1] RW value= 0x1 */
/* REG_DIVQ3_EN [5:1] RW value= 0x1 */
/* REG_RFCLK_SEL [6:1] RW value= 0x0 */
/* RESETONLOCK [7:1] RW value= 0x0 */
/* BYPCK_SEL [8:4] RW value= 0x0 */
/* REG_BYPASS_GO_B [12:1] RW value= 0x0 */
/* RESERVE10 [13:3] RSVD */
/* REG_BYPASSPRE [16:4] RW value= 0x0 */
/* REG_BYPASSPOST [20:4] RW value= 0x0 */
/* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */
/* LOCK [25:1] RO */
/* LOCK_INT_EN [26:1] RW value= 0x0 */
/* UNLOCK_INT_EN [27:1] RW value= 0x0 */
/* LOCK_INT [28:1] SW1C */
/* UNLOCK_INT [29:1] SW1C */
/* RESERVE11 [30:1] RSVD */
/* LOCK_B [31:1] RO */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_REF_FB)
/*PLL reference and feedback registers */
#define LIBERO_SETTING_SGMII_PLL_REF_FB 0x00000100UL
/* FSE_B [0:1] RW value= 0x0 */
/* FBCK_SEL [1:2] RW value= 0x0 */
/* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */
/* RESERVE12 [4:4] RSVD */
/* RFDIV [8:6] RW value= 0x1 */
/* RESERVE13 [14:2] RSVD */
/* RESERVE14 [16:12] RSVD */
/* RESERVE15 [28:4] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_FRACN)
/*PLL fractional register */
#define LIBERO_SETTING_SGMII_PLL_FRACN 0x00000000UL
/* FRACN_EN [0:1] RW value= 0x0 */
/* FRACN_DAC_EN [1:1] RW value= 0x0 */
/* RESERVE16 [2:6] RSVD */
/* RESERVE17 [8:24] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_DIV_0_1)
/*PLL 0/1 division registers */
#define LIBERO_SETTING_SGMII_PLL_DIV_0_1 0x01000100UL
/* VCO0PH_SEL [0:3] RO */
/* DIV0_START [3:3] RW value= 0x0 */
/* RESERVE18 [6:2] RSVD */
/* POST0DIV [8:7] RW value= 0x1 */
/* RESERVE19 [15:1] RSVD */
/* VCO1PH_SEL [16:3] RO */
/* DIV1_START [19:3] RW value= 0x0 */
/* RESERVE20 [22:2] RSVD */
/* POST1DIV [24:7] RW value= 0x1 */
/* RESERVE21 [31:1] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_DIV_2_3)
/*PLL 2/3 division registers */
#define LIBERO_SETTING_SGMII_PLL_DIV_2_3 0x01000100UL
/* VCO2PH_SEL [0:3] RO */
/* DIV2_START [3:3] RW value= 0x0 */
/* RESERVE22 [6:2] RSVD */
/* POST2DIV [8:7] RW value= 0x1 */
/* RESERVE23 [15:1] RSVD */
/* VCO3PH_SEL [16:3] RO */
/* DIV3_START [19:3] RW value= 0x0 */
/* RESERVE24 [22:2] RSVD */
/* POST3DIV [24:7] RW value= 0x1 */
/* CKPOST3_SEL [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_CTRL2)
/*PLL control register */
#define LIBERO_SETTING_SGMII_PLL_CTRL2 0x00001020UL
/* BWI [0:2] RW value= 0x0 */
/* BWP [2:2] RW value= 0x0 */
/* IREF_EN [4:1] RW value= 0x0 */
/* IREF_TOGGLE [5:1] RW value= 0x1 */
/* RESERVE25 [6:3] RSVD */
/* LOCKCNT [9:4] RW value= 0x8 */
/* RESERVE26 [13:4] RSVD */
/* ATEST_EN [17:1] RW value= 0x0 */
/* ATEST_SEL [18:3] RW value= 0x0 */
/* RESERVE27 [21:11] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_CAL)
/*PLL calibration register */
#define LIBERO_SETTING_SGMII_PLL_CAL 0x00000D06UL
/* DSKEWCALCNT [0:3] RW value= 0x6 */
/* DSKEWCAL_EN [3:1] RW value= 0x0 */
/* DSKEWCALBYP [4:1] RW value= 0x0 */
/* RESERVE28 [5:3] RSVD */
/* DSKEWCALIN [8:7] RW value= 0xd */
/* RESERVE29 [15:1] RSVD */
/* DSKEWCALOUT [16:7] RO */
/* RESERVE30 [23:9] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_PHADJ)
/*PLL phase registers */
#define LIBERO_SETTING_SGMII_PLL_PHADJ 0x00007443UL
/* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */
/* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */
/* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */
/* REG_OUT1_PHSINIT [5:3] RW value= 0x2 */
/* REG_OUT2_PHSINIT [8:3] RW value= 0x4 */
/* REG_OUT3_PHSINIT [11:3] RW value= 0x6 */
/* REG_LOADPHS_B [14:1] RW value= 0x1 */
/* RESERVE31 [15:17] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_0)
/*SSCG registers 0 */
#define LIBERO_SETTING_SGMII_SSCG_REG_0 0x00000000UL
/* DIVVAL [0:6] RW value= 0x0 */
/* FRACIN [6:24] RW value= 0x0 */
/* RESERVE00 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_1)
/*SSCG registers 1 */
#define LIBERO_SETTING_SGMII_SSCG_REG_1 0x00000000UL
/* DOWNSPREAD [0:1] RW value= 0x0 */
/* SSMD [1:5] RW value= 0x0 */
/* FRACMOD [6:24] RO */
/* RESERVE01 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_2)
/*SSCG registers 2 */
#define LIBERO_SETTING_SGMII_SSCG_REG_2 0x00000014UL
/* INTIN [0:12] RW value= 0x14 */
/* INTMOD [12:12] RO */
/* RESERVE02 [24:8] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_3)
/*SSCG registers 3 */
#define LIBERO_SETTING_SGMII_SSCG_REG_3 0x00000001UL
/* SSE_B [0:1] RW value= 0x1 */
/* SEL_EXTWAVE [1:2] RW value= 0x0 */
/* EXT_MAXADDR [3:8] RW value= 0x0 */
/* TBLADDR [11:8] RO */
/* RANDOM_FILTER [19:1] RW value= 0x0 */
/* RANDOM_SEL [20:2] RW value= 0x0 */
/* RESERVE03 [22:1] RSVD */
/* RESERVE04 [23:9] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_SGMII_PLL_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_sysreg.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_SYSREG_H_
#define HW_CLK_SYSREG_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_MSS_CLOCK_CONFIG_CR)
/*Master clock config (00=/1 01=/2 10=/4 11=/8 ) */
#define LIBERO_SETTING_MSS_CLOCK_CONFIG_CR 0x00000024UL
/* DIVIDER_CPU [0:2] RW value= 0x0 */
/* DIVIDER_AXI [2:2] RW value= 0x1 */
/* DIVIDER_APB_AHB [4:2] RW value= 0x2 */
#endif
#if !defined (LIBERO_SETTING_MSS_RTC_CLOCK_CR)
/*RTC clock divider */
#define LIBERO_SETTING_MSS_RTC_CLOCK_CR 0x0000007DUL
/* PERIOD [0:12] RW value= 0x7D */
#endif
#if !defined (LIBERO_SETTING_MSS_ENVM_CR)
/*ENVM AHB Controller setup - - Clock period = (Value+1) * (1000/AHBFREQMHZ)
e.g. 7 will generate a 40ns period 25MHz clock if the AHB clock is 200MHz */
#define LIBERO_SETTING_MSS_ENVM_CR 0x40050006UL
/* CLOCK_PERIOD [0:6] RW value= 0x6 */
/* CLOCK_CONTINUOUS [8:1] RW value= 0x0 */
/* CLOCK_SUPPRESS [9:1] RW value= 0x0 */
/* READAHEAD [16:1] RW value= 0x1 */
/* SLOWREAD [17:1] RW value= 0x0 */
/* INTERRUPT_ENABLE [18:1] RW value= 0x1 */
/* TIMER [24:8] RW value= 0x40 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_SYSREG_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mss_clks.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MSS_CLKS_H_
#define HW_MSS_CLKS_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_MSS_EXT_SGMII_REF_CLK)
/*Ref Clock rate in MHz */
#define LIBERO_SETTING_MSS_EXT_SGMII_REF_CLK 125000000
/* MSS_EXT_SGMII_REF_CLK [0:32] RW value= 125000000 */
#endif
#if !defined (LIBERO_SETTING_MSS_COREPLEX_CPU_CLK)
/*CPU Clock rate in MHz */
#define LIBERO_SETTING_MSS_COREPLEX_CPU_CLK 600000000
/* MSS_COREPLEX_CPU_CLK [0:32] RW value= 600000000 */
#endif
#if !defined (LIBERO_SETTING_MSS_SYSTEM_CLK)
/*System Clock rate in MHz static power. */
#define LIBERO_SETTING_MSS_SYSTEM_CLK 600000000
/* MSS_SYSTEM_CLK [0:32] RW value= 600000000 */
#endif
#if !defined (LIBERO_SETTING_MSS_RTC_TOGGLE_CLK)
/*RTC toggle Clock rate in MHz static power. */
#define LIBERO_SETTING_MSS_RTC_TOGGLE_CLK 1000000
/* MSS_RTC_TOGGLE_CLK [0:32] RW value= 1000000 */
#endif
#if !defined (LIBERO_SETTING_MSS_AXI_CLK)
/*AXI Clock rate in MHz static power. */
#define LIBERO_SETTING_MSS_AXI_CLK 300000000
/* MSS_AXI_CLK [0:32] RW value= 300000000 */
#endif
#if !defined (LIBERO_SETTING_MSS_APB_AHB_CLK)
/*AXI Clock rate in MHz static power. */
#define LIBERO_SETTING_MSS_APB_AHB_CLK 150000000
/* MSS_APB_AHB_CLK [0:32] RW value= 150000000 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MSS_CLKS_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_ddr_io_bank.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_DDR_IO_BANK_H_
#define HW_DDR_IO_BANK_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_DPC_BITS)
/*DPC Bits Register */
#define LIBERO_SETTING_DPC_BITS 0x0004C422UL
/* DPC_VS [0:4] RW value= 0x2 */
/* DPC_VRGEN_H [4:6] RW value= 0x2 */
/* DPC_VRGEN_EN_H [10:1] RW value= 0x1 */
/* DPC_MOVE_EN_H [11:1] RW value= 0x0 */
/* DPC_VRGEN_V [12:6] RW value= 0xC */
/* DPC_VRGEN_EN_V [18:1] RW value= 0x1 */
/* DPC_MOVE_EN_V [19:1] RW value= 0x0 */
/* RESERVE01 [20:12] RSVD */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_DQ)
/*Need to be set by software in all modes but OFF mode. Decoding options should
follow ODT_STR table, depends on drive STR setting */
#define LIBERO_SETTING_RPC_ODT_DQ 0x00000006UL
/* RPC_ODT_DQ [0:32] RW value= 0x6 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_DQS)
/*Need to be set by software in all modes but OFF mode. Decoding options should
follow ODT_STR table, depends on drive STR setting */
#define LIBERO_SETTING_RPC_ODT_DQS 0x00000006UL
/* RPC_ODT_DQS [0:32] RW value= 0x6 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_ADDCMD)
/*Need to be set by software in all modes but OFF mode. Decoding options should
follow ODT_STR table, depends on drive STR setting */
#define LIBERO_SETTING_RPC_ODT_ADDCMD 0x00000002UL
/* RPC_ODT_ADDCMD [0:32] RW value= 0x2 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_CLK)
/*Need to be set by software in all modes but OFF mode. Decoding options should
follow ODT_STR table, depends on drive STR setting */
#define LIBERO_SETTING_RPC_ODT_CLK 0x00000002UL
/* RPC_ODT_CLK [0:32] RW value= 0x2 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_DQ)
/*0x2000 73A8 (rpc10_ODT) */
#define LIBERO_SETTING_RPC_ODT_STATIC_DQ 0x00000005UL
/* RPC_ODT_STATIC_DQ [0:32] RW value= 0x5 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_DQS)
/*0x2000 73AC (rpc11_ODT) */
#define LIBERO_SETTING_RPC_ODT_STATIC_DQS 0x00000005UL
/* RPC_ODT_STATIC_DQS [0:32] RW value= 0x5 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_ADDCMD)
/*0x2000 739C (rpc7_ODT) */
#define LIBERO_SETTING_RPC_ODT_STATIC_ADDCMD 0x00000007UL
/* RPC_ODT_STATIC_ADDCMD [0:32] RW value= 0x7 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_CLKP)
/*0x2000 73A4 (rpc9_ODT) */
#define LIBERO_SETTING_RPC_ODT_STATIC_CLKP 0x00000007UL
/* RPC_ODT_STATIC_CLKP [0:32] RW value= 0x7 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_CLKN)
/*0x2000 73A0 (rpc8_ODT) */
#define LIBERO_SETTING_RPC_ODT_STATIC_CLKN 0x00000007UL
/* RPC_ODT_STATIC_CLKN [0:32] RW value= 0x7 */
#endif
#if !defined (LIBERO_SETTING_RPC_IBUFMD_ADDCMD)
/*0x2000 757C (rpc95) */
#define LIBERO_SETTING_RPC_IBUFMD_ADDCMD 0x00000003UL
/* RPC_IBUFMD_ADDCMD [0:32] RW value= 0x3 */
#endif
#if !defined (LIBERO_SETTING_RPC_IBUFMD_CLK)
/*0x2000 7580 (rpc96) */
#define LIBERO_SETTING_RPC_IBUFMD_CLK 0x00000004UL
/* RPC_IBUFMD_CLK [0:32] RW value= 0x4 */
#endif
#if !defined (LIBERO_SETTING_RPC_IBUFMD_DQ)
/*0x2000 7584 (rpc97) */
#define LIBERO_SETTING_RPC_IBUFMD_DQ 0x00000003UL
/* RPC_IBUFMD_DQ [0:32] RW value= 0x3 */
#endif
#if !defined (LIBERO_SETTING_RPC_IBUFMD_DQS)
/*0x2000 7588 (rpc98) */
#define LIBERO_SETTING_RPC_IBUFMD_DQS 0x00000004UL
/* RPC_IBUFMD_DQS [0:32] RW value= 0x4 */
#endif
#if !defined (LIBERO_SETTING_RPC_SPARE0_DQ)
/*bits 15:14 connect to pc_ibufmx DQ/DQS/DM bits 13:12 connect to pc_ibufmx
CA/CK Check at ioa pc bit */
#define LIBERO_SETTING_RPC_SPARE0_DQ 0x00008000UL
/* RPC_SPARE0_DQ [0:32] RW value= 0x8000 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9 0x00000F00UL
/* MSS_DDR_CK0 [0:1] RW value= 0x0 */
/* MSS_DDR_CK_N0 [1:1] RW value= 0x0 */
/* MSS_DDR_A0 [2:1] RW value= 0x0 */
/* MSS_DDR_A1 [3:1] RW value= 0x0 */
/* MSS_DDR_A2 [4:1] RW value= 0x0 */
/* MSS_DDR_A3 [5:1] RW value= 0x0 */
/* MSS_DDR_A4 [6:1] RW value= 0x0 */
/* MSS_DDR_A5 [7:1] RW value= 0x0 */
/* MSS_DDR_A6 [8:1] RW value= 0x1 */
/* MSS_DDR_A7 [9:1] RW value= 0x1 */
/* MSS_DDR_A8 [10:1] RW value= 0x1 */
/* MSS_DDR_A9 [11:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000FFFUL
/* MSS_DDR_CK1 [0:1] RW value= 0x1 */
/* MSS_DDR_CK_N1 [1:1] RW value= 0x1 */
/* MSS_DDR_A10 [2:1] RW value= 0x1 */
/* MSS_DDR_A11 [3:1] RW value= 0x1 */
/* MSS_DDR_A12 [4:1] RW value= 0x1 */
/* MSS_DDR_A13 [5:1] RW value= 0x1 */
/* MSS_DDR_A14 [6:1] RW value= 0x1 */
/* MSS_DDR_A15 [7:1] RW value= 0x1 */
/* MSS_DDR_A16 [8:1] RW value= 0x1 */
/* MSS_DDR3_WE_N [9:1] RW value= 0x1 */
/* MSS_DDR_BA0 [10:1] RW value= 0x1 */
/* MSS_DDR_BA1 [11:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000FE6UL
/* MSS_DDR_RAM_RST_N [0:1] RW value= 0x0 */
/* MSS_DDR_BG0 [1:1] RW value= 0x1 */
/* MSS_DDR_BG1 [2:1] RW value= 0x1 */
/* MSS_DDR_CS0 [3:1] RW value= 0x0 */
/* MSS_DDR_CKE0 [4:1] RW value= 0x0 */
/* MSS_DDR_ODT0 [5:1] RW value= 0x1 */
/* MSS_DDR_CS1 [6:1] RW value= 0x1 */
/* MSS_DDR_CKE1 [7:1] RW value= 0x1 */
/* MSS_DDR_ODT1 [8:1] RW value= 0x1 */
/* MSS_DDR_ACT_N [9:1] RW value= 0x1 */
/* MSS_DDR_PARITY [10:1] RW value= 0x1 */
/* MSS_DDR_ALERT_N [11:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_DATA0_OVRT12)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_DATA0_OVRT12 0x00000000UL
/* MSS_DDR_DQ0 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ1 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ2 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ3 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P0 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N0 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ4 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ5 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ6 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ7 [9:1] RW value= 0x0 */
/* MSS_DDR_DM0 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_DATA1_OVRT13)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_DATA1_OVRT13 0x00000000UL
/* MSS_DDR_DQ8 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ9 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ10 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ11 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P1 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N1 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ12 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ13 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ14 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ15 [9:1] RW value= 0x0 */
/* MSS_DDR_DM1 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_DATA2_OVRT14)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_DATA2_OVRT14 0x00000000UL
/* MSS_DDR_DQ16 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ17 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ18 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ19 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P2 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N2 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ20 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ21 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ22 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ23 [9:1] RW value= 0x0 */
/* MSS_DDR_DM2 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_DATA3_OVRT15)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_DATA3_OVRT15 0x00000000UL
/* MSS_DDR_DQ24 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ25 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ26 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ27 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P3 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N3 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ28 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ29 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ30 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ31 [9:1] RW value= 0x0 */
/* MSS_DDR_DM3 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_ECC_OVRT16)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_ECC_OVRT16 0x0000007FUL
/* MSS_DDR_DQ32 [0:1] RW value= 0x1 */
/* MSS_DDR_DQ33 [1:1] RW value= 0x1 */
/* MSS_DDR_DQ34 [2:1] RW value= 0x1 */
/* MSS_DDR_DQ35 [3:1] RW value= 0x1 */
/* MSS_DDR_DQS_P4 [4:1] RW value= 0x1 */
/* MSS_DDR_DQS_N4 [5:1] RW value= 0x1 */
/* MSS_DDR_DM4 [6:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC235_WPD_ADD_CMD0)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC235_WPD_ADD_CMD0 0x00000000UL
/* MSS_DDR_CK0 [0:1] RW value= 0x0 */
/* MSS_DDR_CK_N0 [1:1] RW value= 0x0 */
/* MSS_DDR_A0 [2:1] RW value= 0x0 */
/* MSS_DDR_A1 [3:1] RW value= 0x0 */
/* MSS_DDR_A2 [4:1] RW value= 0x0 */
/* MSS_DDR_A3 [5:1] RW value= 0x0 */
/* MSS_DDR_A4 [6:1] RW value= 0x0 */
/* MSS_DDR_A5 [7:1] RW value= 0x0 */
/* MSS_DDR_A6 [8:1] RW value= 0x0 */
/* MSS_DDR_A7 [9:1] RW value= 0x0 */
/* MSS_DDR_A8 [10:1] RW value= 0x0 */
/* MSS_DDR_A9 [11:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC236_WPD_ADD_CMD1)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC236_WPD_ADD_CMD1 0x00000000UL
/* MSS_DDR_CK1 [0:1] RW value= 0x0 */
/* MSS_DDR_CK_N1 [1:1] RW value= 0x0 */
/* MSS_DDR_A10 [2:1] RW value= 0x0 */
/* MSS_DDR_A11 [3:1] RW value= 0x0 */
/* MSS_DDR_A12 [4:1] RW value= 0x0 */
/* MSS_DDR_A13 [5:1] RW value= 0x0 */
/* MSS_DDR_A14 [6:1] RW value= 0x0 */
/* MSS_DDR_A15 [7:1] RW value= 0x0 */
/* MSS_DDR_A16 [8:1] RW value= 0x0 */
/* MSS_DDR3_WE_N [9:1] RW value= 0x0 */
/* MSS_DDR_BA0 [10:1] RW value= 0x0 */
/* MSS_DDR_BA1 [11:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC237_WPD_ADD_CMD2)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. Note: For LPDDR4 need
to over-ride MSS_DDR_ODT0 and MSS_DDR_ODT1 and eanble PU i.e. (set OVR_EN ==1 ,
wpu == 0 , wpd == 1 ) */
#define LIBERO_SETTING_RPC237_WPD_ADD_CMD2 0x00000120UL
/* MSS_DDR_RAM_RST_N [0:1] RW value= 0x0 */
/* MSS_DDR_BG0 [1:1] RW value= 0x0 */
/* MSS_DDR_BG1 [2:1] RW value= 0x0 */
/* MSS_DDR_CS0 [3:1] RW value= 0x0 */
/* MSS_DDR_CKE0 [4:1] RW value= 0x0 */
/* MSS_DDR_ODT0 [5:1] RW value= 0x1 */
/* MSS_DDR_CS1 [6:1] RW value= 0x0 */
/* MSS_DDR_CKE1 [7:1] RW value= 0x0 */
/* MSS_DDR_ODT1 [8:1] RW value= 0x1 */
/* MSS_DDR_ACT_N [9:1] RW value= 0x0 */
/* MSS_DDR_PARITY [10:1] RW value= 0x0 */
/* MSS_DDR_ALERT_N [11:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC238_WPD_DATA0)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC238_WPD_DATA0 0x00000000UL
/* MSS_DDR_DQ0 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ1 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ2 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ3 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P0 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N0 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ4 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ5 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ6 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ7 [9:1] RW value= 0x0 */
/* MSS_DDR_DM0 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC239_WPD_DATA1)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC239_WPD_DATA1 0x00000000UL
/* MSS_DDR_DQ8 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ9 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ10 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ11 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P1 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N1 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ12 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ13 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ14 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ15 [9:1] RW value= 0x0 */
/* MSS_DDR_DM1 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC240_WPD_DATA2)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC240_WPD_DATA2 0x00000000UL
/* MSS_DDR_DQ16 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ17 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ18 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ19 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P2 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N2 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ20 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ21 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ22 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ23 [9:1] RW value= 0x0 */
/* MSS_DDR_DM2 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC241_WPD_DATA3)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC241_WPD_DATA3 0x00000000UL
/* MSS_DDR_DQ24 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ25 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ26 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ27 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P3 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N3 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ28 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ29 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ30 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ31 [9:1] RW value= 0x0 */
/* MSS_DDR_DM3 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC242_WPD_ECC)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC242_WPD_ECC 0x00000000UL
/* MSS_DDR_DQ32 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ33 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ34 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ35 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P4 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N4 [5:1] RW value= 0x0 */
/* MSS_DDR_DM4 [6:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC243_WPU_ADD_CMD0)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC243_WPU_ADD_CMD0 0x00000FFFUL
/* MSS_DDR_CK0 [0:1] RW value= 0x1 */
/* MSS_DDR_CK_N0 [1:1] RW value= 0x1 */
/* MSS_DDR_A0 [2:1] RW value= 0x1 */
/* MSS_DDR_A1 [3:1] RW value= 0x1 */
/* MSS_DDR_A2 [4:1] RW value= 0x1 */
/* MSS_DDR_A3 [5:1] RW value= 0x1 */
/* MSS_DDR_A4 [6:1] RW value= 0x1 */
/* MSS_DDR_A5 [7:1] RW value= 0x1 */
/* MSS_DDR_A6 [8:1] RW value= 0x1 */
/* MSS_DDR_A7 [9:1] RW value= 0x1 */
/* MSS_DDR_A8 [10:1] RW value= 0x1 */
/* MSS_DDR_A9 [11:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC244_WPU_ADD_CMD1)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC244_WPU_ADD_CMD1 0x00000FFFUL
/* MSS_DDR_CK1 [0:1] RW value= 0x1 */
/* MSS_DDR_CK_N1 [1:1] RW value= 0x1 */
/* MSS_DDR_A10 [2:1] RW value= 0x1 */
/* MSS_DDR_A11 [3:1] RW value= 0x1 */
/* MSS_DDR_A12 [4:1] RW value= 0x1 */
/* MSS_DDR_A13 [5:1] RW value= 0x1 */
/* MSS_DDR_A14 [6:1] RW value= 0x1 */
/* MSS_DDR_A15 [7:1] RW value= 0x1 */
/* MSS_DDR_A16 [8:1] RW value= 0x1 */
/* MSS_DDR3_WE_N [9:1] RW value= 0x1 */
/* MSS_DDR_BA0 [10:1] RW value= 0x1 */
/* MSS_DDR_BA1 [11:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC245_WPU_ADD_CMD2)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC245_WPU_ADD_CMD2 0x00000EDFUL
/* MSS_DDR_RAM_RST_N [0:1] RW value= 0x1 */
/* MSS_DDR_BG0 [1:1] RW value= 0x1 */
/* MSS_DDR_BG1 [2:1] RW value= 0x1 */
/* MSS_DDR_CS0 [3:1] RW value= 0x1 */
/* MSS_DDR_CKE0 [4:1] RW value= 0x1 */
/* MSS_DDR_ODT0 [5:1] RW value= 0x0 */
/* MSS_DDR_CS1 [6:1] RW value= 0x1 */
/* MSS_DDR_CKE1 [7:1] RW value= 0x1 */
/* MSS_DDR_ODT1 [8:1] RW value= 0x0 */
/* MSS_DDR_ACT_N [9:1] RW value= 0x1 */
/* MSS_DDR_PARITY [10:1] RW value= 0x1 */
/* MSS_DDR_ALERT_N [11:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC246_WPU_DATA0)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC246_WPU_DATA0 0x000007FFUL
/* MSS_DDR_DQ0 [0:1] RW value= 0x1 */
/* MSS_DDR_DQ1 [1:1] RW value= 0x1 */
/* MSS_DDR_DQ2 [2:1] RW value= 0x1 */
/* MSS_DDR_DQ3 [3:1] RW value= 0x1 */
/* MSS_DDR_DQS_P0 [4:1] RW value= 0x1 */
/* MSS_DDR_DQS_N0 [5:1] RW value= 0x1 */
/* MSS_DDR_DQ4 [6:1] RW value= 0x1 */
/* MSS_DDR_DQ5 [7:1] RW value= 0x1 */
/* MSS_DDR_DQ6 [8:1] RW value= 0x1 */
/* MSS_DDR_DQ7 [9:1] RW value= 0x1 */
/* MSS_DDR_DM0 [10:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC247_WPU_DATA1)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC247_WPU_DATA1 0x000007FFUL
/* MSS_DDR_DQ8 [0:1] RW value= 0x1 */
/* MSS_DDR_DQ9 [1:1] RW value= 0x1 */
/* MSS_DDR_DQ10 [2:1] RW value= 0x1 */
/* MSS_DDR_DQ11 [3:1] RW value= 0x1 */
/* MSS_DDR_DQS_P1 [4:1] RW value= 0x1 */
/* MSS_DDR_DQS_N1 [5:1] RW value= 0x1 */
/* MSS_DDR_DQ12 [6:1] RW value= 0x1 */
/* MSS_DDR_DQ13 [7:1] RW value= 0x1 */
/* MSS_DDR_DQ14 [8:1] RW value= 0x1 */
/* MSS_DDR_DQ15 [9:1] RW value= 0x1 */
/* MSS_DDR_DM1 [10:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC248_WPU_DATA2)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC248_WPU_DATA2 0x000007FFUL
/* MSS_DDR_DQ16 [0:1] RW value= 0x1 */
/* MSS_DDR_DQ17 [1:1] RW value= 0x1 */
/* MSS_DDR_DQ18 [2:1] RW value= 0x1 */
/* MSS_DDR_DQ19 [3:1] RW value= 0x1 */
/* MSS_DDR_DQS_P2 [4:1] RW value= 0x1 */
/* MSS_DDR_DQS_N2 [5:1] RW value= 0x1 */
/* MSS_DDR_DQ20 [6:1] RW value= 0x1 */
/* MSS_DDR_DQ21 [7:1] RW value= 0x1 */
/* MSS_DDR_DQ22 [8:1] RW value= 0x1 */
/* MSS_DDR_DQ23 [9:1] RW value= 0x1 */
/* MSS_DDR_DM2 [10:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC249_WPU_DATA3)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC249_WPU_DATA3 0x000007FFUL
/* MSS_DDR_DQ24 [0:1] RW value= 0x1 */
/* MSS_DDR_DQ25 [1:1] RW value= 0x1 */
/* MSS_DDR_DQ26 [2:1] RW value= 0x1 */
/* MSS_DDR_DQ27 [3:1] RW value= 0x1 */
/* MSS_DDR_DQS_P3 [4:1] RW value= 0x1 */
/* MSS_DDR_DQS_N3 [5:1] RW value= 0x1 */
/* MSS_DDR_DQ28 [6:1] RW value= 0x1 */
/* MSS_DDR_DQ29 [7:1] RW value= 0x1 */
/* MSS_DDR_DQ30 [8:1] RW value= 0x1 */
/* MSS_DDR_DQ31 [9:1] RW value= 0x1 */
/* MSS_DDR_DM3 [10:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC250_WPU_ECC)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC250_WPU_ECC 0x0000007FUL
/* MSS_DDR_DQ32 [0:1] RW value= 0x1 */
/* MSS_DDR_DQ33 [1:1] RW value= 0x1 */
/* MSS_DDR_DQ34 [2:1] RW value= 0x1 */
/* MSS_DDR_DQ35 [3:1] RW value= 0x1 */
/* MSS_DDR_DQS_P4 [4:1] RW value= 0x1 */
/* MSS_DDR_DQS_N4 [5:1] RW value= 0x1 */
/* MSS_DDR_DM4 [6:1] RW value= 0x1 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_DDR_IO_BANK_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_ddr_mode.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_DDR_MODE_H_
#define HW_DDR_MODE_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_DDRPHY_MODE)
/*DDRPHY MODE (binary)- 000 ddr3, 001 ddr33L, 010 ddr4, 011 LPDDR3, 100 LPDDR4,
111 OFF_MODE */
#define LIBERO_SETTING_DDRPHY_MODE 0x00014B24UL
/* DDRMODE [0:3] RW value= 0x4 */
/* ECC [3:1] RW value= 0x0 */
/* CRC [4:1] RW value= 0x0 */
/* BUS_WIDTH [5:3] RW value= 0x1 */
/* DMI_DBI [8:1] RW value= 0x1 */
/* DQ_DRIVE [9:2] RW value= 0x1 */
/* DQS_DRIVE [11:2] RW value= 0x1 */
/* ADD_CMD_DRIVE [13:2] RW value= 0x2 */
/* CLOCK_OUT_DRIVE [15:2] RW value= 0x2 */
/* DQ_TERMINATION [17:2] RW value= 0x0 */
/* DQS_TERMINATION [19:2] RW value= 0x0 */
/* ADD_CMD_INPUT_PIN_TERMINATION [21:2] RW value= 0x0 */
/* PRESET_ODT_CLK [23:2] RW value= 0x0 */
/* POWER_DOWN [25:1] RW value= 0x0 */
/* RANK [26:1] RW value= 0x0 */
/* RESERVED [27:5] RSVD */
#endif
#if !defined (LIBERO_SETTING_DATA_LANES_USED)
/*number of lanes used for data- does not include ECC, infer from mode register
*/
#define LIBERO_SETTING_DATA_LANES_USED 0x00000004UL
/* DATA_LANES [0:3] RW value= 0x4 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_DDR_MODE_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_ddr_off_mode.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_DDR_OFF_MODE_H_
#define HW_DDR_OFF_MODE_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_DDRPHY_MODE_OFF)
/*DDRPHY MODE Register, ddr off */
#define LIBERO_SETTING_DDRPHY_MODE_OFF 0x00000000UL
/* DDRMODE [0:3] RW value= 0x0 */
/* ECC [3:1] RW value= 0x0 */
/* CRC [4:1] RW value= 0x0 */
/* BUS_WIDTH [5:3] RW value= 0x0 */
/* DMI_DBI [8:1] RW value= 0x0 */
/* DQ_DRIVE [9:2] RW value= 0x0 */