ext: hal: mchp: Fix compilation for MEC1501 HAL macros
Correct HAL macros related to eSPI block Add GIRQ bit definitions for VWires and some peripherals Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
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@ -122,14 +122,14 @@
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#define MCHP_GIRQ17_ZID 9u
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#define MCHP_GIRQ18_ZID 10u
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#define MCHP_GIRQ19_ZID 11u
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#define MCHP_GIRQ20_ZID 12u
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#define MCHP_GIRQ20_ZID 12u /* Nothing in datasheet */
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#define MCHP_GIRQ21_ZID 13u
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#define MCHP_GIRQ22_ZID 14u
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#define MCHP_GIRQ23_ZID 15u
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#define MCHP_GIRQ24_ZID 16u
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#define MCHP_GIRQ25_ZID 17u
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#define MCHP_GIRQ26_ZID 18u
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#define MCHP_GIRQ_ZID_MAX 19u
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#define MCHP_GIRQ23_ZID 14u /* Adjust per datasheet */
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#define MCHP_GIRQ24_ZID 15u
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#define MCHP_GIRQ25_ZID 16u
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#define MCHP_GIRQ26_ZID 17u
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#define MCHP_GIRQ_ZID_MAX 18u
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#define MCHP_ECIA_BLK_ENSET_OFS 0x200ul
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#define MCHP_ECIA_BLK_ENCLR_OFS 0x204ul
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@ -321,7 +321,7 @@ enum MCHP_GIRQ_IDS {
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MCHP_GIRQ19_ID,
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MCHP_GIRQ20_ID,
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MCHP_GIRQ21_ID,
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MCHP_GIRQ22_ID,
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MCHP_GIRQ23_ID,
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MCHP_GIRQ24_ID,
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MCHP_GIRQ25_ID,
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@ -329,6 +329,10 @@ enum MCHP_GIRQ_IDS {
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MCHP_GIRQ_ID_MAX,
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};
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/* GIRQ Source, Enable_Set/Clr, Result registers bit positions */
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#define MCHP_PORT80_DEBUG0_GIRQ_VAL (1ul << 22)
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#define MCHP_PORT80_DEBUG1_GIRQ_VAL (1ul << 23)
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/**
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* @brief EC Interrupt Aggregator (ECIA)
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*/
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@ -198,6 +198,35 @@
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#define MEC_ESPI_MSVW06_SRC2_POS 26u
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#define MEC_ESPI_MSVW06_SRC3_POS 27u
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#define MEC_ESPI_MSVW00_SRC0_VAL (1 << MEC_ESPI_MSVW00_SRC0_POS)
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#define MEC_ESPI_MSVW00_SRC1_VAL (1 << MEC_ESPI_MSVW00_SRC1_POS)
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#define MEC_ESPI_MSVW00_SRC2_VAL (1 << MEC_ESPI_MSVW00_SRC2_POS)
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#define MEC_ESPI_MSVW00_SRC3_VAL (1 << MEC_ESPI_MSVW00_SRC3_POS)
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#define MEC_ESPI_MSVW01_SRC0_VAL (1 << MEC_ESPI_MSVW01_SRC0_POS)
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#define MEC_ESPI_MSVW01_SRC1_VAL (1 << MEC_ESPI_MSVW01_SRC1_POS)
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#define MEC_ESPI_MSVW01_SRC2_VAL (1 << MEC_ESPI_MSVW01_SRC2_POS)
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#define MEC_ESPI_MSVW01_SRC3_VAL (1 << MEC_ESPI_MSVW01_SRC3_POS)
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#define MEC_ESPI_MSVW02_SRC0_VAL (1 << MEC_ESPI_MSVW02_SRC0_POS)
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#define MEC_ESPI_MSVW02_SRC1_VAL (1 << MEC_ESPI_MSVW02_SRC1_POS)
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#define MEC_ESPI_MSVW02_SRC2_VAL (1 << MEC_ESPI_MSVW02_SRC2_POS)
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#define MEC_ESPI_MSVW02_SRC3_VAL (1 << MEC_ESPI_MSVW02_SRC3_POS)
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#define MEC_ESPI_MSVW03_SRC0_VAL (1 << MEC_ESPI_MSVW03_SRC0_POS)
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#define MEC_ESPI_MSVW03_SRC1_VAL (1 << MEC_ESPI_MSVW03_SRC1_POS)
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#define MEC_ESPI_MSVW03_SRC2_VAL (1 << MEC_ESPI_MSVW03_SRC2_POS)
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#define MEC_ESPI_MSVW03_SRC3_VAL (1 << MEC_ESPI_MSVW03_SRC3_POS)
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#define MEC_ESPI_MSVW04_SRC0_VAL (1 << MEC_ESPI_MSVW04_SRC0_POS)
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#define MEC_ESPI_MSVW04_SRC1_VAL (1 << MEC_ESPI_MSVW04_SRC1_POS)
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#define MEC_ESPI_MSVW04_SRC2_VAL (1 << MEC_ESPI_MSVW04_SRC2_POS)
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#define MEC_ESPI_MSVW04_SRC3_VAL (1 << MEC_ESPI_MSVW04_SRC3_POS)
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#define MEC_ESPI_MSVW05_SRC0_VAL (1 << MEC_ESPI_MSVW05_SRC0_POS)
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#define MEC_ESPI_MSVW05_SRC1_VAL (1 << MEC_ESPI_MSVW05_SRC1_POS)
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#define MEC_ESPI_MSVW05_SRC2_VAL (1 << MEC_ESPI_MSVW05_SRC2_POS)
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#define MEC_ESPI_MSVW05_SRC3_VAL (1 << MEC_ESPI_MSVW05_SRC3_POS)
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#define MEC_ESPI_MSVW06_SRC0_VAL (1 << MEC_ESPI_MSVW06_SRC0_POS)
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#define MEC_ESPI_MSVW06_SRC1_VAL (1 << MEC_ESPI_MSVW06_SRC1_POS)
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#define MEC_ESPI_MSVW06_SRC2_VAL (1 << MEC_ESPI_MSVW06_SRC2_POS)
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#define MEC_ESPI_MSVW06_SRC3_VAL (1 << MEC_ESPI_MSVW06_SRC3_POS)
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/*
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* 0 <= v <= 6
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* 0 <= s <= 3
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@ -121,7 +121,9 @@ typedef struct vbatr_regs
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__IOM uint32_t PFRS; /*! (@ 0x00000000) VBATR Power Fail Reset Status */
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uint8_t RSVD1[4];
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__IOM uint32_t CLK32_EN; /*! (@ 0x00000008) VBATR 32K clock enable */
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uint8_t RSVD2[20];
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__IOM uint32_t SHDN_EN; /*! (@ 0x0000000C) VBATR SHD pin enable */
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uint8_t RSVD2[12];
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__IOM uint32_t CKK32_TRIM; /*! (@ 0x0000001C) VBATR 32 clock override */
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__IOM uint32_t MCNT_LO; /*! (@ 0x00000020) VBATR monotonic count lo */
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__IOM uint32_t MCNT_HI; /*! (@ 0x00000024) VBATR monotonic count hi */
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} VBATR_Type;
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