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hal_atmel/include/dt-bindings/pinctrl/same54p-pinctrl.h

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/*
* Autogenerated file
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <dt-bindings/pinctrl/atmel_sam_pinctrl.h>
/*
* WARNING: this variant has package exception.
*
* Read datasheet topics related to I/O Multiplexing and Considerations or
* Peripheral Signal Multiplexing on I/O Lines for more information.
*/
/* pa0_gpio */
#define PA0_GPIO \
SAM_PINMUX(a, 0, gpio, gpio)
/* pa0a_eic_extint0 */
#define PA0A_EIC_EXTINT0 \
SAM_PINMUX(a, 0, a, periph)
/* pa0d_sercom1_pad0 */
#define PA0D_SERCOM1_PAD0 \
SAM_PINMUX(a, 0, d, periph)
/* pa0e_tc2_wo0 */
#define PA0E_TC2_WO0 \
SAM_PINMUX(a, 0, e, periph)
/* pa1_gpio */
#define PA1_GPIO \
SAM_PINMUX(a, 1, gpio, gpio)
/* pa1a_eic_extint1 */
#define PA1A_EIC_EXTINT1 \
SAM_PINMUX(a, 1, a, periph)
/* pa1d_sercom1_pad1 */
#define PA1D_SERCOM1_PAD1 \
SAM_PINMUX(a, 1, d, periph)
/* pa1e_tc2_wo1 */
#define PA1E_TC2_WO1 \
SAM_PINMUX(a, 1, e, periph)
/* pa2_gpio */
#define PA2_GPIO \
SAM_PINMUX(a, 2, gpio, gpio)
/* pa2a_eic_extint2 */
#define PA2A_EIC_EXTINT2 \
SAM_PINMUX(a, 2, a, periph)
/* pa2b_adc0_ain0 */
#define PA2B_ADC0_AIN0 \
SAM_PINMUX(a, 2, b, periph)
/* pa2b_dac_vout0 */
#define PA2B_DAC_VOUT0 \
SAM_PINMUX(a, 2, b, periph)
/* pa3_gpio */
#define PA3_GPIO \
SAM_PINMUX(a, 3, gpio, gpio)
/* pa3a_eic_extint3 */
#define PA3A_EIC_EXTINT3 \
SAM_PINMUX(a, 3, a, periph)
/* pa3b_anaref_vrefa */
#define PA3B_ANAREF_VREFA \
SAM_PINMUX(a, 3, b, periph)
/* pa3b_adc0_ain1 */
#define PA3B_ADC0_AIN1 \
SAM_PINMUX(a, 3, b, periph)
/* pa3b_ptc_xy0 */
#define PA3B_PTC_XY0 \
SAM_PINMUX(a, 3, b, periph)
/* pa4_gpio */
#define PA4_GPIO \
SAM_PINMUX(a, 4, gpio, gpio)
/* pa4a_eic_extint4 */
#define PA4A_EIC_EXTINT4 \
SAM_PINMUX(a, 4, a, periph)
/* pa4b_anaref_vrefb */
#define PA4B_ANAREF_VREFB \
SAM_PINMUX(a, 4, b, periph)
/* pa4b_adc0_ain4 */
#define PA4B_ADC0_AIN4 \
SAM_PINMUX(a, 4, b, periph)
/* pa4b_ac_ain0 */
#define PA4B_AC_AIN0 \
SAM_PINMUX(a, 4, b, periph)
/* pa4b_ptc_xy3 */
#define PA4B_PTC_XY3 \
SAM_PINMUX(a, 4, b, periph)
/* pa4d_sercom0_pad0 */
#define PA4D_SERCOM0_PAD0 \
SAM_PINMUX(a, 4, d, periph)
/* pa4e_tc0_wo0 */
#define PA4E_TC0_WO0 \
SAM_PINMUX(a, 4, e, periph)
/* pa4n_ccl_in0 */
#define PA4N_CCL_IN0 \
SAM_PINMUX(a, 4, n, periph)
/* pa5_gpio */
#define PA5_GPIO \
SAM_PINMUX(a, 5, gpio, gpio)
/* pa5a_eic_extint5 */
#define PA5A_EIC_EXTINT5 \
SAM_PINMUX(a, 5, a, periph)
/* pa5b_adc0_ain5 */
#define PA5B_ADC0_AIN5 \
SAM_PINMUX(a, 5, b, periph)
/* pa5b_ac_ain1 */
#define PA5B_AC_AIN1 \
SAM_PINMUX(a, 5, b, periph)
/* pa5b_dac_vout1 */
#define PA5B_DAC_VOUT1 \
SAM_PINMUX(a, 5, b, periph)
/* pa5d_sercom0_pad1 */
#define PA5D_SERCOM0_PAD1 \
SAM_PINMUX(a, 5, d, periph)
/* pa5e_tc0_wo1 */
#define PA5E_TC0_WO1 \
SAM_PINMUX(a, 5, e, periph)
/* pa5n_ccl_in1 */
#define PA5N_CCL_IN1 \
SAM_PINMUX(a, 5, n, periph)
/* pa6_gpio */
#define PA6_GPIO \
SAM_PINMUX(a, 6, gpio, gpio)
/* pa6a_eic_extint6 */
#define PA6A_EIC_EXTINT6 \
SAM_PINMUX(a, 6, a, periph)
/* pa6b_anaref_vrefc */
#define PA6B_ANAREF_VREFC \
SAM_PINMUX(a, 6, b, periph)
/* pa6b_adc0_ain6 */
#define PA6B_ADC0_AIN6 \
SAM_PINMUX(a, 6, b, periph)
/* pa6b_ac_ain2 */
#define PA6B_AC_AIN2 \
SAM_PINMUX(a, 6, b, periph)
/* pa6b_ptc_xy4 */
#define PA6B_PTC_XY4 \
SAM_PINMUX(a, 6, b, periph)
/* pa6d_sercom0_pad2 */
#define PA6D_SERCOM0_PAD2 \
SAM_PINMUX(a, 6, d, periph)
/* pa6e_tc1_wo0 */
#define PA6E_TC1_WO0 \
SAM_PINMUX(a, 6, e, periph)
/* pa6i_sdhc0_cd */
#define PA6I_SDHC0_CD \
SAM_PINMUX(a, 6, i, periph)
/* pa6n_ccl_in2 */
#define PA6N_CCL_IN2 \
SAM_PINMUX(a, 6, n, periph)
/* pa7_gpio */
#define PA7_GPIO \
SAM_PINMUX(a, 7, gpio, gpio)
/* pa7a_eic_extint7 */
#define PA7A_EIC_EXTINT7 \
SAM_PINMUX(a, 7, a, periph)
/* pa7b_adc0_ain7 */
#define PA7B_ADC0_AIN7 \
SAM_PINMUX(a, 7, b, periph)
/* pa7b_ac_ain3 */
#define PA7B_AC_AIN3 \
SAM_PINMUX(a, 7, b, periph)
/* pa7b_ptc_xy5 */
#define PA7B_PTC_XY5 \
SAM_PINMUX(a, 7, b, periph)
/* pa7d_sercom0_pad3 */
#define PA7D_SERCOM0_PAD3 \
SAM_PINMUX(a, 7, d, periph)
/* pa7e_tc1_wo1 */
#define PA7E_TC1_WO1 \
SAM_PINMUX(a, 7, e, periph)
/* pa7i_sdhc0_wp */
#define PA7I_SDHC0_WP \
SAM_PINMUX(a, 7, i, periph)
/* pa7n_ccl_out0 */
#define PA7N_CCL_OUT0 \
SAM_PINMUX(a, 7, n, periph)
/* pa8_gpio */
#define PA8_GPIO \
SAM_PINMUX(a, 8, gpio, gpio)
/* pa8a_eic_nmi */
#define PA8A_EIC_NMI \
SAM_PINMUX(a, 8, a, periph)
/* pa8b_adc0_ain8 */
#define PA8B_ADC0_AIN8 \
SAM_PINMUX(a, 8, b, periph)
/* pa8b_adc1_ain2 */
#define PA8B_ADC1_AIN2 \
SAM_PINMUX(a, 8, b, periph)
/* pa8b_ptc_xy6 */
#define PA8B_PTC_XY6 \
SAM_PINMUX(a, 8, b, periph)
/* pa8c_sercom0_pad0 */
#define PA8C_SERCOM0_PAD0 \
SAM_PINMUX(a, 8, c, periph)
/* pa8d_sercom2_pad1 */
#define PA8D_SERCOM2_PAD1 \
SAM_PINMUX(a, 8, d, periph)
/* pa8e_tc0_wo0 */
#define PA8E_TC0_WO0 \
SAM_PINMUX(a, 8, e, periph)
/* pa8f_tcc0_wo0 */
#define PA8F_TCC0_WO0 \
SAM_PINMUX(a, 8, f, periph)
/* pa8g_tcc1_wo4 */
#define PA8G_TCC1_WO4 \
SAM_PINMUX(a, 8, g, periph)
/* pa8h_qspi_data0 */
#define PA8H_QSPI_DATA0 \
SAM_PINMUX(a, 8, h, periph)
/* pa8i_sdhc0_cmd */
#define PA8I_SDHC0_CMD \
SAM_PINMUX(a, 8, i, periph)
/* pa8j_iis_mck0 */
#define PA8J_IIS_MCK0 \
SAM_PINMUX(a, 8, j, periph)
/* pa8n_ccl_in3 */
#define PA8N_CCL_IN3 \
SAM_PINMUX(a, 8, n, periph)
/* pa9_gpio */
#define PA9_GPIO \
SAM_PINMUX(a, 9, gpio, gpio)
/* pa9a_eic_extint9 */
#define PA9A_EIC_EXTINT9 \
SAM_PINMUX(a, 9, a, periph)
/* pa9b_adc0_ain9 */
#define PA9B_ADC0_AIN9 \
SAM_PINMUX(a, 9, b, periph)
/* pa9b_adc1_ain3 */
#define PA9B_ADC1_AIN3 \
SAM_PINMUX(a, 9, b, periph)
/* pa9b_ptc_xy7 */
#define PA9B_PTC_XY7 \
SAM_PINMUX(a, 9, b, periph)
/* pa9c_sercom0_pad1 */
#define PA9C_SERCOM0_PAD1 \
SAM_PINMUX(a, 9, c, periph)
/* pa9d_sercom2_pad0 */
#define PA9D_SERCOM2_PAD0 \
SAM_PINMUX(a, 9, d, periph)
/* pa9e_tc0_wo1 */
#define PA9E_TC0_WO1 \
SAM_PINMUX(a, 9, e, periph)
/* pa9f_tcc0_wo1 */
#define PA9F_TCC0_WO1 \
SAM_PINMUX(a, 9, f, periph)
/* pa9g_tcc1_wo5 */
#define PA9G_TCC1_WO5 \
SAM_PINMUX(a, 9, g, periph)
/* pa9h_qspi_data1 */
#define PA9H_QSPI_DATA1 \
SAM_PINMUX(a, 9, h, periph)
/* pa9i_sdhc0_dat0 */
#define PA9I_SDHC0_DAT0 \
SAM_PINMUX(a, 9, i, periph)
/* pa9j_iis_fs0 */
#define PA9J_IIS_FS0 \
SAM_PINMUX(a, 9, j, periph)
/* pa9n_ccl_in4 */
#define PA9N_CCL_IN4 \
SAM_PINMUX(a, 9, n, periph)
/* pa10_gpio */
#define PA10_GPIO \
SAM_PINMUX(a, 10, gpio, gpio)
/* pa10a_eic_extint10 */
#define PA10A_EIC_EXTINT10 \
SAM_PINMUX(a, 10, a, periph)
/* pa10b_adc0_ain10 */
#define PA10B_ADC0_AIN10 \
SAM_PINMUX(a, 10, b, periph)
/* pa10b_ptc_xy8 */
#define PA10B_PTC_XY8 \
SAM_PINMUX(a, 10, b, periph)
/* pa10c_sercom0_pad2 */
#define PA10C_SERCOM0_PAD2 \
SAM_PINMUX(a, 10, c, periph)
/* pa10d_sercom2_pad2 */
#define PA10D_SERCOM2_PAD2 \
SAM_PINMUX(a, 10, d, periph)
/* pa10e_tc1_wo0 */
#define PA10E_TC1_WO0 \
SAM_PINMUX(a, 10, e, periph)
/* pa10f_tcc0_wo2 */
#define PA10F_TCC0_WO2 \
SAM_PINMUX(a, 10, f, periph)
/* pa10g_tcc1_wo6 */
#define PA10G_TCC1_WO6 \
SAM_PINMUX(a, 10, g, periph)
/* pa10h_qspi_data2 */
#define PA10H_QSPI_DATA2 \
SAM_PINMUX(a, 10, h, periph)
/* pa10i_sdhc0_dat1 */
#define PA10I_SDHC0_DAT1 \
SAM_PINMUX(a, 10, i, periph)
/* pa10j_iis_sck0 */
#define PA10J_IIS_SCK0 \
SAM_PINMUX(a, 10, j, periph)
/* pa10m_gclk_io4 */
#define PA10M_GCLK_IO4 \
SAM_PINMUX(a, 10, m, periph)
/* pa10n_ccl_in5 */
#define PA10N_CCL_IN5 \
SAM_PINMUX(a, 10, n, periph)
/* pa11_gpio */
#define PA11_GPIO \
SAM_PINMUX(a, 11, gpio, gpio)
/* pa11a_eic_extint11 */
#define PA11A_EIC_EXTINT11 \
SAM_PINMUX(a, 11, a, periph)
/* pa11b_adc0_ain11 */
#define PA11B_ADC0_AIN11 \
SAM_PINMUX(a, 11, b, periph)
/* pa11b_ptc_xy9 */
#define PA11B_PTC_XY9 \
SAM_PINMUX(a, 11, b, periph)
/* pa11c_sercom0_pad3 */
#define PA11C_SERCOM0_PAD3 \
SAM_PINMUX(a, 11, c, periph)
/* pa11d_sercom2_pad3 */
#define PA11D_SERCOM2_PAD3 \
SAM_PINMUX(a, 11, d, periph)
/* pa11e_tc1_wo1 */
#define PA11E_TC1_WO1 \
SAM_PINMUX(a, 11, e, periph)
/* pa11f_tcc0_wo3 */
#define PA11F_TCC0_WO3 \
SAM_PINMUX(a, 11, f, periph)
/* pa11g_tcc1_wo7 */
#define PA11G_TCC1_WO7 \
SAM_PINMUX(a, 11, g, periph)
/* pa11h_qspi_data3 */
#define PA11H_QSPI_DATA3 \
SAM_PINMUX(a, 11, h, periph)
/* pa11i_sdhc0_dat2 */
#define PA11I_SDHC0_DAT2 \
SAM_PINMUX(a, 11, i, periph)
/* pa11j_iis_sdo */
#define PA11J_IIS_SDO \
SAM_PINMUX(a, 11, j, periph)
/* pa11m_gclk_io5 */
#define PA11M_GCLK_IO5 \
SAM_PINMUX(a, 11, m, periph)
/* pa11n_ccl_out1 */
#define PA11N_CCL_OUT1 \
SAM_PINMUX(a, 11, n, periph)
/* pa12_gpio */
#define PA12_GPIO \
SAM_PINMUX(a, 12, gpio, gpio)
/* pa12a_eic_extint12 */
#define PA12A_EIC_EXTINT12 \
SAM_PINMUX(a, 12, a, periph)
/* pa12c_sercom2_pad0 */
#define PA12C_SERCOM2_PAD0 \
SAM_PINMUX(a, 12, c, periph)
/* pa12d_sercom4_pad1 */
#define PA12D_SERCOM4_PAD1 \
SAM_PINMUX(a, 12, d, periph)
/* pa12e_tc2_wo0 */
#define PA12E_TC2_WO0 \
SAM_PINMUX(a, 12, e, periph)
/* pa12f_tcc0_wo6 */
#define PA12F_TCC0_WO6 \
SAM_PINMUX(a, 12, f, periph)
/* pa12g_tcc1_wo2 */
#define PA12G_TCC1_WO2 \
SAM_PINMUX(a, 12, g, periph)
/* pa12i_sdhc0_cd */
#define PA12I_SDHC0_CD \
SAM_PINMUX(a, 12, i, periph)
/* pa12k_pcc_den1 */
#define PA12K_PCC_DEN1 \
SAM_PINMUX(a, 12, k, periph)
/* pa12l_gmac_grx1 */
#define PA12L_GMAC_GRX1 \
SAM_PINMUX(a, 12, l, periph)
/* pa12m_ac_cmp0 */
#define PA12M_AC_CMP0 \
SAM_PINMUX(a, 12, m, periph)
/* pa13_gpio */
#define PA13_GPIO \
SAM_PINMUX(a, 13, gpio, gpio)
/* pa13a_eic_extint13 */
#define PA13A_EIC_EXTINT13 \
SAM_PINMUX(a, 13, a, periph)
/* pa13c_sercom2_pad1 */
#define PA13C_SERCOM2_PAD1 \
SAM_PINMUX(a, 13, c, periph)
/* pa13d_sercom4_pad0 */
#define PA13D_SERCOM4_PAD0 \
SAM_PINMUX(a, 13, d, periph)
/* pa13e_tc2_wo1 */
#define PA13E_TC2_WO1 \
SAM_PINMUX(a, 13, e, periph)
/* pa13f_tcc0_wo7 */
#define PA13F_TCC0_WO7 \
SAM_PINMUX(a, 13, f, periph)
/* pa13g_tcc1_wo3 */
#define PA13G_TCC1_WO3 \
SAM_PINMUX(a, 13, g, periph)
/* pa13i_sdhc0_wp */
#define PA13I_SDHC0_WP \
SAM_PINMUX(a, 13, i, periph)
/* pa13k_pcc_den2 */
#define PA13K_PCC_DEN2 \
SAM_PINMUX(a, 13, k, periph)
/* pa13l_gmac_grx0 */
#define PA13L_GMAC_GRX0 \
SAM_PINMUX(a, 13, l, periph)
/* pa13m_ac_cmp1 */
#define PA13M_AC_CMP1 \
SAM_PINMUX(a, 13, m, periph)
/* pa14_gpio */
#define PA14_GPIO \
SAM_PINMUX(a, 14, gpio, gpio)
/* pa14a_eic_extint14 */
#define PA14A_EIC_EXTINT14 \
SAM_PINMUX(a, 14, a, periph)
/* pa14c_sercom2_pad2 */
#define PA14C_SERCOM2_PAD2 \
SAM_PINMUX(a, 14, c, periph)
/* pa14d_sercom4_pad2 */
#define PA14D_SERCOM4_PAD2 \
SAM_PINMUX(a, 14, d, periph)
/* pa14e_tc3_wo0 */
#define PA14E_TC3_WO0 \
SAM_PINMUX(a, 14, e, periph)
/* pa14f_tcc2_wo0 */
#define PA14F_TCC2_WO0 \
SAM_PINMUX(a, 14, f, periph)
/* pa14g_tcc1_wo2 */
#define PA14G_TCC1_WO2 \
SAM_PINMUX(a, 14, g, periph)
/* pa14k_pcc_clk */
#define PA14K_PCC_CLK \
SAM_PINMUX(a, 14, k, periph)
/* pa14l_gmac_gtxck */
#define PA14L_GMAC_GTXCK \
SAM_PINMUX(a, 14, l, periph)
/* pa14m_glkc_io0 */
#define PA14M_GLKC_IO0 \
SAM_PINMUX(a, 14, m, periph)
/* pa15_gpio */
#define PA15_GPIO \
SAM_PINMUX(a, 15, gpio, gpio)
/* pa15a_eic_extint15 */
#define PA15A_EIC_EXTINT15 \
SAM_PINMUX(a, 15, a, periph)
/* pa15c_sercom2_pad3 */
#define PA15C_SERCOM2_PAD3 \
SAM_PINMUX(a, 15, c, periph)
/* pa15d_sercom4_pad3 */
#define PA15D_SERCOM4_PAD3 \
SAM_PINMUX(a, 15, d, periph)
/* pa15e_tc3_wo1 */
#define PA15E_TC3_WO1 \
SAM_PINMUX(a, 15, e, periph)
/* pa15f_tcc2_wo1 */
#define PA15F_TCC2_WO1 \
SAM_PINMUX(a, 15, f, periph)
/* pa15g_tcc1_wo3 */
#define PA15G_TCC1_WO3 \
SAM_PINMUX(a, 15, g, periph)
/* pa15l_gmac_grxer */
#define PA15L_GMAC_GRXER \
SAM_PINMUX(a, 15, l, periph)
/* pa15m_glkc_io1 */
#define PA15M_GLKC_IO1 \
SAM_PINMUX(a, 15, m, periph)
/* pa16_gpio */
#define PA16_GPIO \
SAM_PINMUX(a, 16, gpio, gpio)
/* pa16a_eic_extint0 */
#define PA16A_EIC_EXTINT0 \
SAM_PINMUX(a, 16, a, periph)
/* pa16b_ptc_xy10 */
#define PA16B_PTC_XY10 \
SAM_PINMUX(a, 16, b, periph)
/* pa16c_sercom1_pad0 */
#define PA16C_SERCOM1_PAD0 \
SAM_PINMUX(a, 16, c, periph)
/* pa16d_sercom3_pad1 */
#define PA16D_SERCOM3_PAD1 \
SAM_PINMUX(a, 16, d, periph)
/* pa16e_tc2_wo0 */
#define PA16E_TC2_WO0 \
SAM_PINMUX(a, 16, e, periph)
/* pa16f_tcc1_wo0 */
#define PA16F_TCC1_WO0 \
SAM_PINMUX(a, 16, f, periph)
/* pa16g_tcc0_wo4 */
#define PA16G_TCC0_WO4 \
SAM_PINMUX(a, 16, g, periph)
/* pa16k_pcc_data0 */
#define PA16K_PCC_DATA0 \
SAM_PINMUX(a, 16, k, periph)
/* pa16l_gmac_gcrs_grxdv */
#define PA16L_GMAC_GCRS_GRXDV \
SAM_PINMUX(a, 16, l, periph)
/* pa16m_gclk_io2 */
#define PA16M_GCLK_IO2 \
SAM_PINMUX(a, 16, m, periph)
/* pa16n_ccl_in0 */
#define PA16N_CCL_IN0 \
SAM_PINMUX(a, 16, n, periph)
/* pa17_gpio */
#define PA17_GPIO \
SAM_PINMUX(a, 17, gpio, gpio)
/* pa17a_eic_extint1 */
#define PA17A_EIC_EXTINT1 \
SAM_PINMUX(a, 17, a, periph)
/* pa17b_ptc_xy11 */
#define PA17B_PTC_XY11 \
SAM_PINMUX(a, 17, b, periph)
/* pa17c_sercom1_pad1 */
#define PA17C_SERCOM1_PAD1 \
SAM_PINMUX(a, 17, c, periph)
/* pa17d_sercom3_pad0 */
#define PA17D_SERCOM3_PAD0 \
SAM_PINMUX(a, 17, d, periph)
/* pa17e_tc2_wo1 */
#define PA17E_TC2_WO1 \
SAM_PINMUX(a, 17, e, periph)
/* pa17f_tcc1_wo1 */
#define PA17F_TCC1_WO1 \
SAM_PINMUX(a, 17, f, periph)
/* pa17g_tcc0_wo5 */
#define PA17G_TCC0_WO5 \
SAM_PINMUX(a, 17, g, periph)
/* pa17k_pcc_data1 */
#define PA17K_PCC_DATA1 \
SAM_PINMUX(a, 17, k, periph)
/* pa17l_gmac_gtxen */
#define PA17L_GMAC_GTXEN \
SAM_PINMUX(a, 17, l, periph)
/* pa17m_gclk_io3 */
#define PA17M_GCLK_IO3 \
SAM_PINMUX(a, 17, m, periph)
/* pa17n_ccl_in1 */
#define PA17N_CCL_IN1 \
SAM_PINMUX(a, 17, n, periph)
/* pa18_gpio */
#define PA18_GPIO \
SAM_PINMUX(a, 18, gpio, gpio)
/* pa18a_eic_extint2 */
#define PA18A_EIC_EXTINT2 \
SAM_PINMUX(a, 18, a, periph)
/* pa18b_ptc_xy12 */
#define PA18B_PTC_XY12 \
SAM_PINMUX(a, 18, b, periph)
/* pa18c_sercom1_pad2 */
#define PA18C_SERCOM1_PAD2 \
SAM_PINMUX(a, 18, c, periph)
/* pa18d_sercom3_pad2 */
#define PA18D_SERCOM3_PAD2 \
SAM_PINMUX(a, 18, d, periph)
/* pa18e_tc3_wo0 */
#define PA18E_TC3_WO0 \
SAM_PINMUX(a, 18, e, periph)
/* pa18f_tcc1_wo2 */
#define PA18F_TCC1_WO2 \
SAM_PINMUX(a, 18, f, periph)
/* pa18g_tcc0_wo6 */
#define PA18G_TCC0_WO6 \
SAM_PINMUX(a, 18, g, periph)
/* pa18k_pcc_data2 */
#define PA18K_PCC_DATA2 \
SAM_PINMUX(a, 18, k, periph)
/* pa18l_gmac_gtx0 */
#define PA18L_GMAC_GTX0 \
SAM_PINMUX(a, 18, l, periph)
/* pa18m_ac_cmp0 */
#define PA18M_AC_CMP0 \
SAM_PINMUX(a, 18, m, periph)
/* pa18n_ccl_in2 */
#define PA18N_CCL_IN2 \
SAM_PINMUX(a, 18, n, periph)
/* pa19_gpio */
#define PA19_GPIO \
SAM_PINMUX(a, 19, gpio, gpio)
/* pa19a_eic_extint3 */
#define PA19A_EIC_EXTINT3 \
SAM_PINMUX(a, 19, a, periph)
/* pa19b_ptc_xy13 */
#define PA19B_PTC_XY13 \
SAM_PINMUX(a, 19, b, periph)
/* pa19c_sercom1_pad3 */
#define PA19C_SERCOM1_PAD3 \
SAM_PINMUX(a, 19, c, periph)
/* pa19d_sercom3_pad3 */
#define PA19D_SERCOM3_PAD3 \
SAM_PINMUX(a, 19, d, periph)
/* pa19e_tc3_wo1 */
#define PA19E_TC3_WO1 \
SAM_PINMUX(a, 19, e, periph)
/* pa19f_tcc1_wo3 */
#define PA19F_TCC1_WO3 \
SAM_PINMUX(a, 19, f, periph)
/* pa19g_tcc0_wo7 */
#define PA19G_TCC0_WO7 \
SAM_PINMUX(a, 19, g, periph)
/* pa19k_pcc_data3 */
#define PA19K_PCC_DATA3 \
SAM_PINMUX(a, 19, k, periph)
/* pa19l_gmac_gtx1 */
#define PA19L_GMAC_GTX1 \
SAM_PINMUX(a, 19, l, periph)
/* pa19m_ac_cmp1 */
#define PA19M_AC_CMP1 \
SAM_PINMUX(a, 19, m, periph)
/* pa19n_ccl_out0 */
#define PA19N_CCL_OUT0 \
SAM_PINMUX(a, 19, n, periph)
/* pa20_gpio */
#define PA20_GPIO \
SAM_PINMUX(a, 20, gpio, gpio)
/* pa20a_eic_extint4 */
#define PA20A_EIC_EXTINT4 \
SAM_PINMUX(a, 20, a, periph)
/* pa20b_ptc_xy14 */
#define PA20B_PTC_XY14 \
SAM_PINMUX(a, 20, b, periph)
/* pa20c_sercom5_pad2 */
#define PA20C_SERCOM5_PAD2 \
SAM_PINMUX(a, 20, c, periph)
/* pa20d_sercom3_pad2 */
#define PA20D_SERCOM3_PAD2 \
SAM_PINMUX(a, 20, d, periph)
/* pa20e_tc7_wo0 */
#define PA20E_TC7_WO0 \
SAM_PINMUX(a, 20, e, periph)
/* pa20f_tcc1_wo4 */
#define PA20F_TCC1_WO4 \
SAM_PINMUX(a, 20, f, periph)
/* pa20g_tcc0_wo0 */
#define PA20G_TCC0_WO0 \
SAM_PINMUX(a, 20, g, periph)
/* pa20i_sdhc1_cmd */
#define PA20I_SDHC1_CMD \
SAM_PINMUX(a, 20, i, periph)
/* pa20j_iis_fs0 */
#define PA20J_IIS_FS0 \
SAM_PINMUX(a, 20, j, periph)
/* pa20k_pcc_data4 */
#define PA20K_PCC_DATA4 \
SAM_PINMUX(a, 20, k, periph)
/* pa20l_gmac_gmdc */
#define PA20L_GMAC_GMDC \
SAM_PINMUX(a, 20, l, periph)
/* pa21_gpio */
#define PA21_GPIO \
SAM_PINMUX(a, 21, gpio, gpio)
/* pa21a_eic_extint5 */
#define PA21A_EIC_EXTINT5 \
SAM_PINMUX(a, 21, a, periph)
/* pa21b_ptc_xy15 */
#define PA21B_PTC_XY15 \
SAM_PINMUX(a, 21, b, periph)
/* pa21c_sercom5_pad3 */
#define PA21C_SERCOM5_PAD3 \
SAM_PINMUX(a, 21, c, periph)
/* pa21d_sercom3_pad3 */
#define PA21D_SERCOM3_PAD3 \
SAM_PINMUX(a, 21, d, periph)
/* pa21e_tc7_wo1 */
#define PA21E_TC7_WO1 \
SAM_PINMUX(a, 21, e, periph)
/* pa21f_tcc1_wo5 */
#define PA21F_TCC1_WO5 \
SAM_PINMUX(a, 21, f, periph)
/* pa21g_tcc0_wo1 */
#define PA21G_TCC0_WO1 \
SAM_PINMUX(a, 21, g, periph)
/* pa21i_sdhc1_ck */
#define PA21I_SDHC1_CK \
SAM_PINMUX(a, 21, i, periph)
/* pa21j_iis_sdo */
#define PA21J_IIS_SDO \
SAM_PINMUX(a, 21, j, periph)
/* pa21k_pcc_data5 */
#define PA21K_PCC_DATA5 \
SAM_PINMUX(a, 21, k, periph)
/* pa21l_gmac_gmdio */
#define PA21L_GMAC_GMDIO \
SAM_PINMUX(a, 21, l, periph)
/* pa22_gpio */
#define PA22_GPIO \
SAM_PINMUX(a, 22, gpio, gpio)
/* pa22a_eic_extint6 */
#define PA22A_EIC_EXTINT6 \
SAM_PINMUX(a, 22, a, periph)
/* pa22b_ptc_xy16 */
#define PA22B_PTC_XY16 \
SAM_PINMUX(a, 22, b, periph)
/* pa22c_sercom3_pad0 */
#define PA22C_SERCOM3_PAD0 \
SAM_PINMUX(a, 22, c, periph)
/* pa22d_sercom5_pad1 */
#define PA22D_SERCOM5_PAD1 \
SAM_PINMUX(a, 22, d, periph)
/* pa22e_tc4_wo0 */
#define PA22E_TC4_WO0 \
SAM_PINMUX(a, 22, e, periph)
/* pa22f_tcc1_wo6 */
#define PA22F_TCC1_WO6 \
SAM_PINMUX(a, 22, f, periph)
/* pa22g_tcc0_wo2 */
#define PA22G_TCC0_WO2 \
SAM_PINMUX(a, 22, g, periph)
/* pa22i_can0_tx */
#define PA22I_CAN0_TX \
SAM_PINMUX(a, 22, i, periph)
/* pa22j_iis_sdi */
#define PA22J_IIS_SDI \
SAM_PINMUX(a, 22, j, periph)
/* pa22k_pcc_data6 */
#define PA22K_PCC_DATA6 \
SAM_PINMUX(a, 22, k, periph)
/* pa22n_ccl_in6 */
#define PA22N_CCL_IN6 \
SAM_PINMUX(a, 22, n, periph)
/* pa23_gpio */
#define PA23_GPIO \
SAM_PINMUX(a, 23, gpio, gpio)
/* pa23a_eic_extint7 */
#define PA23A_EIC_EXTINT7 \
SAM_PINMUX(a, 23, a, periph)
/* pa23b_ptc_xy17 */
#define PA23B_PTC_XY17 \
SAM_PINMUX(a, 23, b, periph)
/* pa23c_sercom3_pad1 */
#define PA23C_SERCOM3_PAD1 \
SAM_PINMUX(a, 23, c, periph)
/* pa23d_sercom5_pad0 */
#define PA23D_SERCOM5_PAD0 \
SAM_PINMUX(a, 23, d, periph)
/* pa23e_tc4_wo1 */
#define PA23E_TC4_WO1 \
SAM_PINMUX(a, 23, e, periph)
/* pa23f_tcc1_wo7 */
#define PA23F_TCC1_WO7 \
SAM_PINMUX(a, 23, f, periph)
/* pa23g_tcc0_wo3 */
#define PA23G_TCC0_WO3 \
SAM_PINMUX(a, 23, g, periph)
/* pa23h_usb_sof */
#define PA23H_USB_SOF \
SAM_PINMUX(a, 23, h, periph)
/* pa23i_can0_rx */
#define PA23I_CAN0_RX \
SAM_PINMUX(a, 23, i, periph)
/* pa23j_iis_fs1 */
#define PA23J_IIS_FS1 \
SAM_PINMUX(a, 23, j, periph)
/* pa23k_pcc_data7 */
#define PA23K_PCC_DATA7 \
SAM_PINMUX(a, 23, k, periph)
/* pa23n_ccl_in7 */
#define PA23N_CCL_IN7 \
SAM_PINMUX(a, 23, n, periph)
/* pa24_gpio */
#define PA24_GPIO \
SAM_PINMUX(a, 24, gpio, gpio)
/* pa24a_eic_extint8 */
#define PA24A_EIC_EXTINT8 \
SAM_PINMUX(a, 24, a, periph)
/* pa24c_sercom3_pad2 */
#define PA24C_SERCOM3_PAD2 \
SAM_PINMUX(a, 24, c, periph)
/* pa24d_sercom5_pad2 */
#define PA24D_SERCOM5_PAD2 \
SAM_PINMUX(a, 24, d, periph)
/* pa24e_tc5_wo0 */
#define PA24E_TC5_WO0 \
SAM_PINMUX(a, 24, e, periph)
/* pa24f_tcc2_wo2 */
#define PA24F_TCC2_WO2 \
SAM_PINMUX(a, 24, f, periph)
/* pa24g_pdec_qdi0 */
#define PA24G_PDEC_QDI0 \
SAM_PINMUX(a, 24, g, periph)
/* pa24h_usb_dm */
#define PA24H_USB_DM \
SAM_PINMUX(a, 24, h, periph)
/* pa24i_can0_tx */
#define PA24I_CAN0_TX \
SAM_PINMUX(a, 24, i, periph)
/* pa24n_ccl_in8 */
#define PA24N_CCL_IN8 \
SAM_PINMUX(a, 24, n, periph)
/* pa25_gpio */
#define PA25_GPIO \
SAM_PINMUX(a, 25, gpio, gpio)
/* pa25a_eic_extint9 */
#define PA25A_EIC_EXTINT9 \
SAM_PINMUX(a, 25, a, periph)
/* pa25c_sercom3_pad3 */
#define PA25C_SERCOM3_PAD3 \
SAM_PINMUX(a, 25, c, periph)
/* pa25d_sercom5_pad3 */
#define PA25D_SERCOM5_PAD3 \
SAM_PINMUX(a, 25, d, periph)
/* pa25e_tc5_wo1 */
#define PA25E_TC5_WO1 \
SAM_PINMUX(a, 25, e, periph)
/* pa25g_pdec_qdi1 */
#define PA25G_PDEC_QDI1 \
SAM_PINMUX(a, 25, g, periph)
/* pa25h_usb_dp */
#define PA25H_USB_DP \
SAM_PINMUX(a, 25, h, periph)
/* pa25i_can0_rx */
#define PA25I_CAN0_RX \
SAM_PINMUX(a, 25, i, periph)
/* pa25n_ccl_out2 */
#define PA25N_CCL_OUT2 \
SAM_PINMUX(a, 25, n, periph)
/* pa27_gpio */
#define PA27_GPIO \
SAM_PINMUX(a, 27, gpio, gpio)
/* pa27a_eic_extint11 */
#define PA27A_EIC_EXTINT11 \
SAM_PINMUX(a, 27, a, periph)
/* pa27b_ptc_xy18 */
#define PA27B_PTC_XY18 \
SAM_PINMUX(a, 27, b, periph)
/* pa27m_gclk_io1 */
#define PA27M_GCLK_IO1 \
SAM_PINMUX(a, 27, m, periph)
/* pa30_gpio */
#define PA30_GPIO \
SAM_PINMUX(a, 30, gpio, gpio)
/* pa30a_eic_extint14 */
#define PA30A_EIC_EXTINT14 \
SAM_PINMUX(a, 30, a, periph)
/* pa30b_ptc_xy19 */
#define PA30B_PTC_XY19 \
SAM_PINMUX(a, 30, b, periph)
/* pa30d_sercom1_pad2 */
#define PA30D_SERCOM1_PAD2 \
SAM_PINMUX(a, 30, d, periph)
/* pa30e_tc6_wo0 */
#define PA30E_TC6_WO0 \
SAM_PINMUX(a, 30, e, periph)
/* pa30f_tcc2_wo0 */
#define PA30F_TCC2_WO0 \
SAM_PINMUX(a, 30, f, periph)
/* pa30h_swd_clk */
#define PA30H_SWD_CLK \
SAM_PINMUX(a, 30, h, periph)
/* pa30m_gclk_io0 */
#define PA30M_GCLK_IO0 \
SAM_PINMUX(a, 30, m, periph)
/* pa30n_ccl_in3 */
#define PA30N_CCL_IN3 \
SAM_PINMUX(a, 30, n, periph)
/* pa31_gpio */
#define PA31_GPIO \
SAM_PINMUX(a, 31, gpio, gpio)
/* pa31a_eic_extint15 */
#define PA31A_EIC_EXTINT15 \
SAM_PINMUX(a, 31, a, periph)
/* pa31d_sercom1_pad3 */
#define PA31D_SERCOM1_PAD3 \
SAM_PINMUX(a, 31, d, periph)
/* pa31e_tc6_wo1 */
#define PA31E_TC6_WO1 \
SAM_PINMUX(a, 31, e, periph)
/* pa31f_tcc2_wo1 */
#define PA31F_TCC2_WO1 \
SAM_PINMUX(a, 31, f, periph)
/* pa31h_swd_io */
#define PA31H_SWD_IO \
SAM_PINMUX(a, 31, h, periph)
/* pa31n_ccl_out1 */
#define PA31N_CCL_OUT1 \
SAM_PINMUX(a, 31, n, periph)
/* pb0_gpio */
#define PB0_GPIO \
SAM_PINMUX(b, 0, gpio, gpio)
/* pb0a_eic_extint0 */
#define PB0A_EIC_EXTINT0 \
SAM_PINMUX(b, 0, a, periph)
/* pb0b_adc0_ain12 */
#define PB0B_ADC0_AIN12 \
SAM_PINMUX(b, 0, b, periph)
/* pb0b_ptc_xy30 */
#define PB0B_PTC_XY30 \
SAM_PINMUX(b, 0, b, periph)
/* pb0d_sercom5_pad2 */
#define PB0D_SERCOM5_PAD2 \
SAM_PINMUX(b, 0, d, periph)
/* pb0e_tc7_wo0 */
#define PB0E_TC7_WO0 \
SAM_PINMUX(b, 0, e, periph)
/* pb0n_ccl_in1 */
#define PB0N_CCL_IN1 \
SAM_PINMUX(b, 0, n, periph)
/* pb1_gpio */
#define PB1_GPIO \
SAM_PINMUX(b, 1, gpio, gpio)
/* pb1a_eic_extint1 */
#define PB1A_EIC_EXTINT1 \
SAM_PINMUX(b, 1, a, periph)
/* pb1b_adc0_ain13 */
#define PB1B_ADC0_AIN13 \
SAM_PINMUX(b, 1, b, periph)
/* pb1b_ptc_xy31 */
#define PB1B_PTC_XY31 \
SAM_PINMUX(b, 1, b, periph)
/* pb1d_sercom5_pad3 */
#define PB1D_SERCOM5_PAD3 \
SAM_PINMUX(b, 1, d, periph)
/* pb1e_tc7_wo1 */
#define PB1E_TC7_WO1 \
SAM_PINMUX(b, 1, e, periph)
/* pb1n_ccl_in2 */
#define PB1N_CCL_IN2 \
SAM_PINMUX(b, 1, n, periph)
/* pb2_gpio */
#define PB2_GPIO \
SAM_PINMUX(b, 2, gpio, gpio)
/* pb2a_eic_extint2 */
#define PB2A_EIC_EXTINT2 \
SAM_PINMUX(b, 2, a, periph)
/* pb2b_adc0_ain14 */
#define PB2B_ADC0_AIN14 \
SAM_PINMUX(b, 2, b, periph)
/* pb2b_ptc_xy20 */
#define PB2B_PTC_XY20 \
SAM_PINMUX(b, 2, b, periph)
/* pb2d_sercom5_pad0 */
#define PB2D_SERCOM5_PAD0 \
SAM_PINMUX(b, 2, d, periph)
/* pb2e_tc6_wo0 */
#define PB2E_TC6_WO0 \
SAM_PINMUX(b, 2, e, periph)
/* pb2f_tcc2_wo2 */
#define PB2F_TCC2_WO2 \
SAM_PINMUX(b, 2, f, periph)
/* pb2n_ccl_out0 */
#define PB2N_CCL_OUT0 \
SAM_PINMUX(b, 2, n, periph)
/* pb3_gpio */
#define PB3_GPIO \
SAM_PINMUX(b, 3, gpio, gpio)
/* pb3a_eic_extint3 */
#define PB3A_EIC_EXTINT3 \
SAM_PINMUX(b, 3, a, periph)
/* pb3b_adc0_ain15 */
#define PB3B_ADC0_AIN15 \
SAM_PINMUX(b, 3, b, periph)
/* pb3b_ptc_xy21 */
#define PB3B_PTC_XY21 \
SAM_PINMUX(b, 3, b, periph)
/* pb3d_sercom5_pad1 */
#define PB3D_SERCOM5_PAD1 \
SAM_PINMUX(b, 3, d, periph)
/* pb3e_tc6_wo1 */
#define PB3E_TC6_WO1 \
SAM_PINMUX(b, 3, e, periph)
/* pb4_gpio */
#define PB4_GPIO \
SAM_PINMUX(b, 4, gpio, gpio)
/* pb4a_eic_extint4 */
#define PB4A_EIC_EXTINT4 \
SAM_PINMUX(b, 4, a, periph)
/* pb4b_adc1_ain6 */
#define PB4B_ADC1_AIN6 \
SAM_PINMUX(b, 4, b, periph)
/* pb4b_ptc_xy22 */
#define PB4B_PTC_XY22 \
SAM_PINMUX(b, 4, b, periph)
/* pb5_gpio */
#define PB5_GPIO \
SAM_PINMUX(b, 5, gpio, gpio)
/* pb5a_eic_extint5 */
#define PB5A_EIC_EXTINT5 \
SAM_PINMUX(b, 5, a, periph)
/* pb5b_adc1_ain7 */
#define PB5B_ADC1_AIN7 \
SAM_PINMUX(b, 5, b, periph)
/* pb5b_ptc_xy23 */
#define PB5B_PTC_XY23 \
SAM_PINMUX(b, 5, b, periph)
/* pb6_gpio */
#define PB6_GPIO \
SAM_PINMUX(b, 6, gpio, gpio)
/* pb6a_eic_extint6 */
#define PB6A_EIC_EXTINT6 \
SAM_PINMUX(b, 6, a, periph)
/* pb6b_adc1_ain8 */
#define PB6B_ADC1_AIN8 \
SAM_PINMUX(b, 6, b, periph)
/* pb6b_ptc_xy24 */
#define PB6B_PTC_XY24 \
SAM_PINMUX(b, 6, b, periph)
/* pb6n_ccl_in6 */
#define PB6N_CCL_IN6 \
SAM_PINMUX(b, 6, n, periph)
/* pb7_gpio */
#define PB7_GPIO \
SAM_PINMUX(b, 7, gpio, gpio)
/* pb7a_eic_extint7 */
#define PB7A_EIC_EXTINT7 \
SAM_PINMUX(b, 7, a, periph)
/* pb7b_adc1_ain9 */
#define PB7B_ADC1_AIN9 \
SAM_PINMUX(b, 7, b, periph)
/* pb7b_ptc_xy25 */
#define PB7B_PTC_XY25 \
SAM_PINMUX(b, 7, b, periph)
/* pb7n_ccl_in7 */
#define PB7N_CCL_IN7 \
SAM_PINMUX(b, 7, n, periph)
/* pb8_gpio */
#define PB8_GPIO \
SAM_PINMUX(b, 8, gpio, gpio)
/* pb8a_eic_extint8 */
#define PB8A_EIC_EXTINT8 \
SAM_PINMUX(b, 8, a, periph)
/* pb8b_adc0_ain2 */
#define PB8B_ADC0_AIN2 \
SAM_PINMUX(b, 8, b, periph)
/* pb8b_adc1_ain0 */
#define PB8B_ADC1_AIN0 \
SAM_PINMUX(b, 8, b, periph)
/* pb8b_ptc_xy1 */
#define PB8B_PTC_XY1 \
SAM_PINMUX(b, 8, b, periph)
/* pb8d_sercom4_pad0 */
#define PB8D_SERCOM4_PAD0 \
SAM_PINMUX(b, 8, d, periph)
/* pb8e_tc4_wo0 */
#define PB8E_TC4_WO0 \
SAM_PINMUX(b, 8, e, periph)
/* pb8n_ccl_in8 */
#define PB8N_CCL_IN8 \
SAM_PINMUX(b, 8, n, periph)
/* pb9_gpio */
#define PB9_GPIO \
SAM_PINMUX(b, 9, gpio, gpio)
/* pb9a_eic_extint9 */
#define PB9A_EIC_EXTINT9 \
SAM_PINMUX(b, 9, a, periph)
/* pb9b_adc0_ain3 */
#define PB9B_ADC0_AIN3 \
SAM_PINMUX(b, 9, b, periph)
/* pb9b_adc1_ain1 */
#define PB9B_ADC1_AIN1 \
SAM_PINMUX(b, 9, b, periph)
/* pb9b_ptc_xy2 */
#define PB9B_PTC_XY2 \
SAM_PINMUX(b, 9, b, periph)
/* pb9d_sercom4_pad1 */
#define PB9D_SERCOM4_PAD1 \
SAM_PINMUX(b, 9, d, periph)
/* pb9e_tc4_wo1 */
#define PB9E_TC4_WO1 \
SAM_PINMUX(b, 9, e, periph)
/* pb9n_ccl_out2 */
#define PB9N_CCL_OUT2 \
SAM_PINMUX(b, 9, n, periph)
/* pb10_gpio */
#define PB10_GPIO \
SAM_PINMUX(b, 10, gpio, gpio)
/* pb10a_eic_extint10 */
#define PB10A_EIC_EXTINT10 \
SAM_PINMUX(b, 10, a, periph)
/* pb10d_sercom4_pad2 */
#define PB10D_SERCOM4_PAD2 \
SAM_PINMUX(b, 10, d, periph)
/* pb10e_tc5_wo0 */
#define PB10E_TC5_WO0 \
SAM_PINMUX(b, 10, e, periph)
/* pb10f_tcc0_wo4 */
#define PB10F_TCC0_WO4 \
SAM_PINMUX(b, 10, f, periph)
/* pb10g_tcc1_wo0 */
#define PB10G_TCC1_WO0 \
SAM_PINMUX(b, 10, g, periph)
/* pb10h_qspi_sck */
#define PB10H_QSPI_SCK \
SAM_PINMUX(b, 10, h, periph)
/* pb10i_sdhc0_dat3 */
#define PB10I_SDHC0_DAT3 \
SAM_PINMUX(b, 10, i, periph)
/* pb10j_iis_sdi */
#define PB10J_IIS_SDI \
SAM_PINMUX(b, 10, j, periph)
/* pb10m_gclk_io4 */
#define PB10M_GCLK_IO4 \
SAM_PINMUX(b, 10, m, periph)
/* pb10n_ccl_in11 */
#define PB10N_CCL_IN11 \
SAM_PINMUX(b, 10, n, periph)
/* pb11_gpio */
#define PB11_GPIO \
SAM_PINMUX(b, 11, gpio, gpio)
/* pb11a_eic_extint11 */
#define PB11A_EIC_EXTINT11 \
SAM_PINMUX(b, 11, a, periph)
/* pb11d_sercom4_pad3 */
#define PB11D_SERCOM4_PAD3 \
SAM_PINMUX(b, 11, d, periph)
/* pb11e_tc5_wo1 */
#define PB11E_TC5_WO1 \
SAM_PINMUX(b, 11, e, periph)
/* pb11f_tcc0_wo5 */
#define PB11F_TCC0_WO5 \
SAM_PINMUX(b, 11, f, periph)
/* pb11g_tcc1_wo1 */
#define PB11G_TCC1_WO1 \
SAM_PINMUX(b, 11, g, periph)
/* pb11h_qspi_cs */
#define PB11H_QSPI_CS \
SAM_PINMUX(b, 11, h, periph)
/* pb11i_sdhc0_ck */
#define PB11I_SDHC0_CK \
SAM_PINMUX(b, 11, i, periph)
/* pb11j_iis_fs1 */
#define PB11J_IIS_FS1 \
SAM_PINMUX(b, 11, j, periph)
/* pb11m_gclk_io5 */
#define PB11M_GCLK_IO5 \
SAM_PINMUX(b, 11, m, periph)
/* pb11n_ccl_out1 */
#define PB11N_CCL_OUT1 \
SAM_PINMUX(b, 11, n, periph)
/* pb12_gpio */
#define PB12_GPIO \
SAM_PINMUX(b, 12, gpio, gpio)
/* pb12a_eic_extint12 */
#define PB12A_EIC_EXTINT12 \
SAM_PINMUX(b, 12, a, periph)
/* pb12b_ptc_xy26 */
#define PB12B_PTC_XY26 \
SAM_PINMUX(b, 12, b, periph)
/* pb12c_sercom4_pad0 */
#define PB12C_SERCOM4_PAD0 \
SAM_PINMUX(b, 12, c, periph)
/* pb12e_tc4_wo0 */
#define PB12E_TC4_WO0 \
SAM_PINMUX(b, 12, e, periph)
/* pb12f_tcc3_wo0 */
#define PB12F_TCC3_WO0 \
SAM_PINMUX(b, 12, f, periph)
/* pb12g_tcc0_wo0 */
#define PB12G_TCC0_WO0 \
SAM_PINMUX(b, 12, g, periph)
/* pb12h_can1_tx */
#define PB12H_CAN1_TX \
SAM_PINMUX(b, 12, h, periph)
/* pb12i_sdhc0_cd */
#define PB12I_SDHC0_CD \
SAM_PINMUX(b, 12, i, periph)
/* pb12j_iis_sck1 */
#define PB12J_IIS_SCK1 \
SAM_PINMUX(b, 12, j, periph)
/* pb12m_gclk_io6 */
#define PB12M_GCLK_IO6 \
SAM_PINMUX(b, 12, m, periph)
/* pb13_gpio */
#define PB13_GPIO \
SAM_PINMUX(b, 13, gpio, gpio)
/* pb13a_eic_extint13 */
#define PB13A_EIC_EXTINT13 \
SAM_PINMUX(b, 13, a, periph)
/* pb13b_ptc_xy27 */
#define PB13B_PTC_XY27 \
SAM_PINMUX(b, 13, b, periph)
/* pb13c_sercom4_pad1 */
#define PB13C_SERCOM4_PAD1 \
SAM_PINMUX(b, 13, c, periph)
/* pb13e_tc4_wo1 */
#define PB13E_TC4_WO1 \
SAM_PINMUX(b, 13, e, periph)
/* pb13f_tcc3_wo1 */
#define PB13F_TCC3_WO1 \
SAM_PINMUX(b, 13, f, periph)
/* pb13g_tcc0_wo1 */
#define PB13G_TCC0_WO1 \
SAM_PINMUX(b, 13, g, periph)
/* pb13h_can1_rx */
#define PB13H_CAN1_RX \
SAM_PINMUX(b, 13, h, periph)
/* pb13i_sdhc0_wp */
#define PB13I_SDHC0_WP \
SAM_PINMUX(b, 13, i, periph)
/* pb13j_iis_mck1 */
#define PB13J_IIS_MCK1 \
SAM_PINMUX(b, 13, j, periph)
/* pb13m_gclk_io7 */
#define PB13M_GCLK_IO7 \
SAM_PINMUX(b, 13, m, periph)
/* pb14_gpio */
#define PB14_GPIO \
SAM_PINMUX(b, 14, gpio, gpio)
/* pb14a_eic_extint14 */
#define PB14A_EIC_EXTINT14 \
SAM_PINMUX(b, 14, a, periph)
/* pb14b_ptc_xy28 */
#define PB14B_PTC_XY28 \
SAM_PINMUX(b, 14, b, periph)
/* pb14c_sercom4_pad2 */
#define PB14C_SERCOM4_PAD2 \
SAM_PINMUX(b, 14, c, periph)
/* pb14e_tc5_wo0 */
#define PB14E_TC5_WO0 \
SAM_PINMUX(b, 14, e, periph)
/* pb14f_tcc4_wo0 */
#define PB14F_TCC4_WO0 \
SAM_PINMUX(b, 14, f, periph)
/* pb14g_tcc0_wo2 */
#define PB14G_TCC0_WO2 \
SAM_PINMUX(b, 14, g, periph)
/* pb14h_can1_tx */
#define PB14H_CAN1_TX \
SAM_PINMUX(b, 14, h, periph)
/* pb14k_pcc_data8 */
#define PB14K_PCC_DATA8 \
SAM_PINMUX(b, 14, k, periph)
/* pb14l_gmac_gmdc */
#define PB14L_GMAC_GMDC \
SAM_PINMUX(b, 14, l, periph)
/* pb14m_gclk_io0 */
#define PB14M_GCLK_IO0 \
SAM_PINMUX(b, 14, m, periph)
/* pb14n_ccl_in9 */
#define PB14N_CCL_IN9 \
SAM_PINMUX(b, 14, n, periph)
/* pb15_gpio */
#define PB15_GPIO \
SAM_PINMUX(b, 15, gpio, gpio)
/* pb15a_eic_extint15 */
#define PB15A_EIC_EXTINT15 \
SAM_PINMUX(b, 15, a, periph)
/* pb15b_ptc_xy29 */
#define PB15B_PTC_XY29 \
SAM_PINMUX(b, 15, b, periph)
/* pb15c_sercom4_pad3 */
#define PB15C_SERCOM4_PAD3 \
SAM_PINMUX(b, 15, c, periph)
/* pb15e_tc5_wo1 */
#define PB15E_TC5_WO1 \
SAM_PINMUX(b, 15, e, periph)
/* pb15f_tcc4_wo1 */
#define PB15F_TCC4_WO1 \
SAM_PINMUX(b, 15, f, periph)
/* pb15g_tcc0_wo3 */
#define PB15G_TCC0_WO3 \
SAM_PINMUX(b, 15, g, periph)
/* pb15h_can1_rx */
#define PB15H_CAN1_RX \
SAM_PINMUX(b, 15, h, periph)
/* pb15k_pcc_data9 */
#define PB15K_PCC_DATA9 \
SAM_PINMUX(b, 15, k, periph)
/* pb15l_gmac_gmdio */
#define PB15L_GMAC_GMDIO \
SAM_PINMUX(b, 15, l, periph)
/* pb15m_gclk_io1 */
#define PB15M_GCLK_IO1 \
SAM_PINMUX(b, 15, m, periph)
/* pb15n_ccl_in10 */
#define PB15N_CCL_IN10 \
SAM_PINMUX(b, 15, n, periph)
/* pb16_gpio */
#define PB16_GPIO \
SAM_PINMUX(b, 16, gpio, gpio)
/* pb16a_eic_extint0 */
#define PB16A_EIC_EXTINT0 \
SAM_PINMUX(b, 16, a, periph)
/* pb16c_sercom5_pad0 */
#define PB16C_SERCOM5_PAD0 \
SAM_PINMUX(b, 16, c, periph)
/* pb16e_tc6_wo0 */
#define PB16E_TC6_WO0 \
SAM_PINMUX(b, 16, e, periph)
/* pb16f_tcc3_wo0 */
#define PB16F_TCC3_WO0 \
SAM_PINMUX(b, 16, f, periph)
/* pb16g_tcc0_wo4 */
#define PB16G_TCC0_WO4 \
SAM_PINMUX(b, 16, g, periph)
/* pb16i_sdhc1_cd */
#define PB16I_SDHC1_CD \
SAM_PINMUX(b, 16, i, periph)
/* pb16j_iis_sck0 */
#define PB16J_IIS_SCK0 \
SAM_PINMUX(b, 16, j, periph)
/* pb16m_gclk_io2 */
#define PB16M_GCLK_IO2 \
SAM_PINMUX(b, 16, m, periph)
/* pb16n_ccl_in11 */
#define PB16N_CCL_IN11 \
SAM_PINMUX(b, 16, n, periph)
/* pb17_gpio */
#define PB17_GPIO \
SAM_PINMUX(b, 17, gpio, gpio)
/* pb17a_eic_extint1 */
#define PB17A_EIC_EXTINT1 \
SAM_PINMUX(b, 17, a, periph)
/* pb17c_sercom5_pad1 */
#define PB17C_SERCOM5_PAD1 \
SAM_PINMUX(b, 17, c, periph)
/* pb17e_tc6_wo1 */
#define PB17E_TC6_WO1 \
SAM_PINMUX(b, 17, e, periph)
/* pb17f_tcc3_wo1 */
#define PB17F_TCC3_WO1 \
SAM_PINMUX(b, 17, f, periph)
/* pb17g_tcc0_wo5 */
#define PB17G_TCC0_WO5 \
SAM_PINMUX(b, 17, g, periph)
/* pb17i_sdhc1_wp */
#define PB17I_SDHC1_WP \
SAM_PINMUX(b, 17, i, periph)
/* pb17j_iis_mck0 */
#define PB17J_IIS_MCK0 \
SAM_PINMUX(b, 17, j, periph)
/* pb17m_gclk_io3 */
#define PB17M_GCLK_IO3 \
SAM_PINMUX(b, 17, m, periph)
/* pb17n_ccl_out3 */
#define PB17N_CCL_OUT3 \
SAM_PINMUX(b, 17, n, periph)
/* pb18_gpio */
#define PB18_GPIO \
SAM_PINMUX(b, 18, gpio, gpio)
/* pb18a_eic_extint2 */
#define PB18A_EIC_EXTINT2 \
SAM_PINMUX(b, 18, a, periph)
/* pb18c_sercom5_pad2 */
#define PB18C_SERCOM5_PAD2 \
SAM_PINMUX(b, 18, c, periph)
/* pb18d_sercom7_pad2 */
#define PB18D_SERCOM7_PAD2 \
SAM_PINMUX(b, 18, d, periph)
/* pb18f_tcc1_wo0 */
#define PB18F_TCC1_WO0 \
SAM_PINMUX(b, 18, f, periph)
/* pb18g_pdec_qdi0 */
#define PB18G_PDEC_QDI0 \
SAM_PINMUX(b, 18, g, periph)
/* pb18i_sdhc1_dat0 */
#define PB18I_SDHC1_DAT0 \
SAM_PINMUX(b, 18, i, periph)
/* pb18m_gclk_io4 */
#define PB18M_GCLK_IO4 \
SAM_PINMUX(b, 18, m, periph)
/* pb19_gpio */
#define PB19_GPIO \
SAM_PINMUX(b, 19, gpio, gpio)
/* pb19a_eic_extint3 */
#define PB19A_EIC_EXTINT3 \
SAM_PINMUX(b, 19, a, periph)
/* pb19c_sercom5_pad3 */
#define PB19C_SERCOM5_PAD3 \
SAM_PINMUX(b, 19, c, periph)
/* pb19d_sercom7_pad3 */
#define PB19D_SERCOM7_PAD3 \
SAM_PINMUX(b, 19, d, periph)
/* pb19f_tcc1_wo1 */
#define PB19F_TCC1_WO1 \
SAM_PINMUX(b, 19, f, periph)
/* pb19g_pdec_qdi1 */
#define PB19G_PDEC_QDI1 \
SAM_PINMUX(b, 19, g, periph)
/* pb19i_sdhc1_dat1 */
#define PB19I_SDHC1_DAT1 \
SAM_PINMUX(b, 19, i, periph)
/* pb19m_gclk_io5 */
#define PB19M_GCLK_IO5 \
SAM_PINMUX(b, 19, m, periph)
/* pb20_gpio */
#define PB20_GPIO \
SAM_PINMUX(b, 20, gpio, gpio)
/* pb20a_eic_extint4 */
#define PB20A_EIC_EXTINT4 \
SAM_PINMUX(b, 20, a, periph)
/* pb20c_sercom3_pad0 */
#define PB20C_SERCOM3_PAD0 \
SAM_PINMUX(b, 20, c, periph)
/* pb20d_sercom7_pad1 */
#define PB20D_SERCOM7_PAD1 \
SAM_PINMUX(b, 20, d, periph)
/* pb20f_tcc1_wo2 */
#define PB20F_TCC1_WO2 \
SAM_PINMUX(b, 20, f, periph)
/* pb20g_pdec_qdi2 */
#define PB20G_PDEC_QDI2 \
SAM_PINMUX(b, 20, g, periph)
/* pb20i_sdhc1_dat2 */
#define PB20I_SDHC1_DAT2 \
SAM_PINMUX(b, 20, i, periph)
/* pb20m_gclk_io6 */
#define PB20M_GCLK_IO6 \
SAM_PINMUX(b, 20, m, periph)
/* pb21_gpio */
#define PB21_GPIO \
SAM_PINMUX(b, 21, gpio, gpio)
/* pb21a_eic_extint5 */
#define PB21A_EIC_EXTINT5 \
SAM_PINMUX(b, 21, a, periph)
/* pb21c_sercom3_pad1 */
#define PB21C_SERCOM3_PAD1 \
SAM_PINMUX(b, 21, c, periph)
/* pb21d_sercom7_pad0 */
#define PB21D_SERCOM7_PAD0 \
SAM_PINMUX(b, 21, d, periph)
/* pb21f_tcc1_wo3 */
#define PB21F_TCC1_WO3 \
SAM_PINMUX(b, 21, f, periph)
/* pb21i_sdhc1_dat3 */
#define PB21I_SDHC1_DAT3 \
SAM_PINMUX(b, 21, i, periph)
/* pb21m_gclk_io7 */
#define PB21M_GCLK_IO7 \
SAM_PINMUX(b, 21, m, periph)
/* pb22_gpio */
#define PB22_GPIO \
SAM_PINMUX(b, 22, gpio, gpio)
/* pb22a_eic_extint6 */
#define PB22A_EIC_EXTINT6 \
SAM_PINMUX(b, 22, a, periph)
/* pb22c_sercom1_pad2 */
#define PB22C_SERCOM1_PAD2 \
SAM_PINMUX(b, 22, c, periph)
/* pb22d_sercom5_pad2 */
#define PB22D_SERCOM5_PAD2 \
SAM_PINMUX(b, 22, d, periph)
/* pb22e_tc7_wo0 */
#define PB22E_TC7_WO0 \
SAM_PINMUX(b, 22, e, periph)
/* pb22g_pdec_qdi2 */
#define PB22G_PDEC_QDI2 \
SAM_PINMUX(b, 22, g, periph)
/* pb22h_usb_sof */
#define PB22H_USB_SOF \
SAM_PINMUX(b, 22, h, periph)
/* pb22m_gclk_io0 */
#define PB22M_GCLK_IO0 \
SAM_PINMUX(b, 22, m, periph)
/* pb22n_ccl_in0 */
#define PB22N_CCL_IN0 \
SAM_PINMUX(b, 22, n, periph)
/* pb23_gpio */
#define PB23_GPIO \
SAM_PINMUX(b, 23, gpio, gpio)
/* pb23a_eic_extint7 */
#define PB23A_EIC_EXTINT7 \
SAM_PINMUX(b, 23, a, periph)
/* pb23c_sercom1_pad3 */
#define PB23C_SERCOM1_PAD3 \
SAM_PINMUX(b, 23, c, periph)
/* pb23d_sercom5_pad3 */
#define PB23D_SERCOM5_PAD3 \
SAM_PINMUX(b, 23, d, periph)
/* pb23e_tc7_wo1 */
#define PB23E_TC7_WO1 \
SAM_PINMUX(b, 23, e, periph)
/* pb23g_pdec_qdi0 */
#define PB23G_PDEC_QDI0 \
SAM_PINMUX(b, 23, g, periph)
/* pb23m_gclk_io1 */
#define PB23M_GCLK_IO1 \
SAM_PINMUX(b, 23, m, periph)
/* pb23n_ccl_out0 */
#define PB23N_CCL_OUT0 \
SAM_PINMUX(b, 23, n, periph)
/* pb24_gpio */
#define PB24_GPIO \
SAM_PINMUX(b, 24, gpio, gpio)
/* pb24a_eic_extint8 */
#define PB24A_EIC_EXTINT8 \
SAM_PINMUX(b, 24, a, periph)
/* pb24c_sercom0_pad0 */
#define PB24C_SERCOM0_PAD0 \
SAM_PINMUX(b, 24, c, periph)
/* pb24d_sercom2_pad1 */
#define PB24D_SERCOM2_PAD1 \
SAM_PINMUX(b, 24, d, periph)
/* pb24g_pdec_qdi1 */
#define PB24G_PDEC_QDI1 \
SAM_PINMUX(b, 24, g, periph)
/* pb24m_ac_cmp0 */
#define PB24M_AC_CMP0 \
SAM_PINMUX(b, 24, m, periph)
/* pb25_gpio */
#define PB25_GPIO \
SAM_PINMUX(b, 25, gpio, gpio)
/* pb25a_eic_extint9 */
#define PB25A_EIC_EXTINT9 \
SAM_PINMUX(b, 25, a, periph)
/* pb25c_sercom0_pad1 */
#define PB25C_SERCOM0_PAD1 \
SAM_PINMUX(b, 25, c, periph)
/* pb25d_sercom2_pad0 */
#define PB25D_SERCOM2_PAD0 \
SAM_PINMUX(b, 25, d, periph)
/* pb25g_pdec_qdi2 */
#define PB25G_PDEC_QDI2 \
SAM_PINMUX(b, 25, g, periph)
/* pb25m_ac_cmp1 */
#define PB25M_AC_CMP1 \
SAM_PINMUX(b, 25, m, periph)
/* pb26_gpio */
#define PB26_GPIO \
SAM_PINMUX(b, 26, gpio, gpio)
/* pb26a_eic_extint12 */
#define PB26A_EIC_EXTINT12 \
SAM_PINMUX(b, 26, a, periph)
/* pb26c_sercom2_pad0 */
#define PB26C_SERCOM2_PAD0 \
SAM_PINMUX(b, 26, c, periph)
/* pb26d_sercom4_pad1 */
#define PB26D_SERCOM4_PAD1 \
SAM_PINMUX(b, 26, d, periph)
/* pb26f_tcc1_wo2 */
#define PB26F_TCC1_WO2 \
SAM_PINMUX(b, 26, f, periph)
/* pb27_gpio */
#define PB27_GPIO \
SAM_PINMUX(b, 27, gpio, gpio)
/* pb27a_eic_extint13 */
#define PB27A_EIC_EXTINT13 \
SAM_PINMUX(b, 27, a, periph)
/* pb27c_sercom2_pad1 */
#define PB27C_SERCOM2_PAD1 \
SAM_PINMUX(b, 27, c, periph)
/* pb27d_sercom4_pad0 */
#define PB27D_SERCOM4_PAD0 \
SAM_PINMUX(b, 27, d, periph)
/* pb27f_tcc1_wo3 */
#define PB27F_TCC1_WO3 \
SAM_PINMUX(b, 27, f, periph)
/* pb28_gpio */
#define PB28_GPIO \
SAM_PINMUX(b, 28, gpio, gpio)
/* pb28a_eic_extint14 */
#define PB28A_EIC_EXTINT14 \
SAM_PINMUX(b, 28, a, periph)
/* pb28c_sercom2_pad2 */
#define PB28C_SERCOM2_PAD2 \
SAM_PINMUX(b, 28, c, periph)
/* pb28d_sercom4_pad2 */
#define PB28D_SERCOM4_PAD2 \
SAM_PINMUX(b, 28, d, periph)
/* pb28f_tcc1_wo4 */
#define PB28F_TCC1_WO4 \
SAM_PINMUX(b, 28, f, periph)
/* pb28j_iis_sck1 */
#define PB28J_IIS_SCK1 \
SAM_PINMUX(b, 28, j, periph)
/* pb29_gpio */
#define PB29_GPIO \
SAM_PINMUX(b, 29, gpio, gpio)
/* pb29a_eic_extint15 */
#define PB29A_EIC_EXTINT15 \
SAM_PINMUX(b, 29, a, periph)
/* pb29c_sercom2_pad3 */
#define PB29C_SERCOM2_PAD3 \
SAM_PINMUX(b, 29, c, periph)
/* pb29d_sercom4_pad3 */
#define PB29D_SERCOM4_PAD3 \
SAM_PINMUX(b, 29, d, periph)
/* pb29f_tcc1_wo5 */
#define PB29F_TCC1_WO5 \
SAM_PINMUX(b, 29, f, periph)
/* pb29j_iis_mck1 */
#define PB29J_IIS_MCK1 \
SAM_PINMUX(b, 29, j, periph)
/* pb30_gpio */
#define PB30_GPIO \
SAM_PINMUX(b, 30, gpio, gpio)
/* pb30a_eic_extint14 */
#define PB30A_EIC_EXTINT14 \
SAM_PINMUX(b, 30, a, periph)
/* pb30d_sercom5_pad1 */
#define PB30D_SERCOM5_PAD1 \
SAM_PINMUX(b, 30, d, periph)
/* pb30e_tc0_wo0 */
#define PB30E_TC0_WO0 \
SAM_PINMUX(b, 30, e, periph)
/* pb30f_tcc4_wo0 */
#define PB30F_TCC4_WO0 \
SAM_PINMUX(b, 30, f, periph)
/* pb30g_tcc0_wo6 */
#define PB30G_TCC0_WO6 \
SAM_PINMUX(b, 30, g, periph)
/* pb30h_swd_swo */
#define PB30H_SWD_SWO \
SAM_PINMUX(b, 30, h, periph)
/* pb31_gpio */
#define PB31_GPIO \
SAM_PINMUX(b, 31, gpio, gpio)
/* pb31a_eic_extint15 */
#define PB31A_EIC_EXTINT15 \
SAM_PINMUX(b, 31, a, periph)
/* pb31d_sercom5_pad0 */
#define PB31D_SERCOM5_PAD0 \
SAM_PINMUX(b, 31, d, periph)
/* pb31e_tc0_wo1 */
#define PB31E_TC0_WO1 \
SAM_PINMUX(b, 31, e, periph)
/* pb31f_tcc4_wo1 */
#define PB31F_TCC4_WO1 \
SAM_PINMUX(b, 31, f, periph)
/* pb31g_tcc0_wo7 */
#define PB31G_TCC0_WO7 \
SAM_PINMUX(b, 31, g, periph)
/* pc0_gpio */
#define PC0_GPIO \
SAM_PINMUX(c, 0, gpio, gpio)
/* pc0a_eic_extint0 */
#define PC0A_EIC_EXTINT0 \
SAM_PINMUX(c, 0, a, periph)
/* pc0b_adc1_ain10 */
#define PC0B_ADC1_AIN10 \
SAM_PINMUX(c, 0, b, periph)
/* pc1_gpio */
#define PC1_GPIO \
SAM_PINMUX(c, 1, gpio, gpio)
/* pc1a_eic_extint1 */
#define PC1A_EIC_EXTINT1 \
SAM_PINMUX(c, 1, a, periph)
/* pc1b_adc1_ain11 */
#define PC1B_ADC1_AIN11 \
SAM_PINMUX(c, 1, b, periph)
/* pc2_gpio */
#define PC2_GPIO \
SAM_PINMUX(c, 2, gpio, gpio)
/* pc2a_eic_extint2 */
#define PC2A_EIC_EXTINT2 \
SAM_PINMUX(c, 2, a, periph)
/* pc2b_adc1_ain4 */
#define PC2B_ADC1_AIN4 \
SAM_PINMUX(c, 2, b, periph)
/* pc3_gpio */
#define PC3_GPIO \
SAM_PINMUX(c, 3, gpio, gpio)
/* pc3a_eic_extint3 */
#define PC3A_EIC_EXTINT3 \
SAM_PINMUX(c, 3, a, periph)
/* pc3b_adc1_ain5 */
#define PC3B_ADC1_AIN5 \
SAM_PINMUX(c, 3, b, periph)
/* pc4_gpio */
#define PC4_GPIO \
SAM_PINMUX(c, 4, gpio, gpio)
/* pc4a_eic_extint4 */
#define PC4A_EIC_EXTINT4 \
SAM_PINMUX(c, 4, a, periph)
/* pc4c_sercom6_pad0 */
#define PC4C_SERCOM6_PAD0 \
SAM_PINMUX(c, 4, c, periph)
/* pc4f_tcc0_wo0 */
#define PC4F_TCC0_WO0 \
SAM_PINMUX(c, 4, f, periph)
/* pc5_gpio */
#define PC5_GPIO \
SAM_PINMUX(c, 5, gpio, gpio)
/* pc5a_eic_extint5 */
#define PC5A_EIC_EXTINT5 \
SAM_PINMUX(c, 5, a, periph)
/* pc5c_sercom6_pad1 */
#define PC5C_SERCOM6_PAD1 \
SAM_PINMUX(c, 5, c, periph)
/* pc6_gpio */
#define PC6_GPIO \
SAM_PINMUX(c, 6, gpio, gpio)
/* pc6a_eic_extint6 */
#define PC6A_EIC_EXTINT6 \
SAM_PINMUX(c, 6, a, periph)
/* pc6c_sercom6_pad2 */
#define PC6C_SERCOM6_PAD2 \
SAM_PINMUX(c, 6, c, periph)
/* pc6i_sdhc0_cd */
#define PC6I_SDHC0_CD \
SAM_PINMUX(c, 6, i, periph)
/* pc7_gpio */
#define PC7_GPIO \
SAM_PINMUX(c, 7, gpio, gpio)
/* pc7a_eic_extint7 */
#define PC7A_EIC_EXTINT7 \
SAM_PINMUX(c, 7, a, periph)
/* pc7c_sercom6_pad3 */
#define PC7C_SERCOM6_PAD3 \
SAM_PINMUX(c, 7, c, periph)
/* pc7i_sdhc0_wp */
#define PC7I_SDHC0_WP \
SAM_PINMUX(c, 7, i, periph)
/* pc10_gpio */
#define PC10_GPIO \
SAM_PINMUX(c, 10, gpio, gpio)
/* pc10a_eic_extint10 */
#define PC10A_EIC_EXTINT10 \
SAM_PINMUX(c, 10, a, periph)
/* pc10c_sercom6_pad2 */
#define PC10C_SERCOM6_PAD2 \
SAM_PINMUX(c, 10, c, periph)
/* pc10d_sercom7_pad2 */
#define PC10D_SERCOM7_PAD2 \
SAM_PINMUX(c, 10, d, periph)
/* pc10f_tcc0_wo0 */
#define PC10F_TCC0_WO0 \
SAM_PINMUX(c, 10, f, periph)
/* pc10g_tcc1_wo4 */
#define PC10G_TCC1_WO4 \
SAM_PINMUX(c, 10, g, periph)
/* pc11_gpio */
#define PC11_GPIO \
SAM_PINMUX(c, 11, gpio, gpio)
/* pc11a_eic_extint11 */
#define PC11A_EIC_EXTINT11 \
SAM_PINMUX(c, 11, a, periph)
/* pc11c_sercom6_pad3 */
#define PC11C_SERCOM6_PAD3 \
SAM_PINMUX(c, 11, c, periph)
/* pc11d_sercom7_pad3 */
#define PC11D_SERCOM7_PAD3 \
SAM_PINMUX(c, 11, d, periph)
/* pc11f_tcc0_wo1 */
#define PC11F_TCC0_WO1 \
SAM_PINMUX(c, 11, f, periph)
/* pc11g_tcc1_wo5 */
#define PC11G_TCC1_WO5 \
SAM_PINMUX(c, 11, g, periph)
/* pc11l_gmac_gmdc */
#define PC11L_GMAC_GMDC \
SAM_PINMUX(c, 11, l, periph)
/* pc12_gpio */
#define PC12_GPIO \
SAM_PINMUX(c, 12, gpio, gpio)
/* pc12a_eic_extint12 */
#define PC12A_EIC_EXTINT12 \
SAM_PINMUX(c, 12, a, periph)
/* pc12c_sercom7_pad0 */
#define PC12C_SERCOM7_PAD0 \
SAM_PINMUX(c, 12, c, periph)
/* pc12d_sercom6_pad1 */
#define PC12D_SERCOM6_PAD1 \
SAM_PINMUX(c, 12, d, periph)
/* pc12f_tcc0_wo2 */
#define PC12F_TCC0_WO2 \
SAM_PINMUX(c, 12, f, periph)
/* pc12g_tcc1_wo6 */
#define PC12G_TCC1_WO6 \
SAM_PINMUX(c, 12, g, periph)
/* pc12k_pcc_data10 */
#define PC12K_PCC_DATA10 \
SAM_PINMUX(c, 12, k, periph)
/* pc12l_gmac_gmdio */
#define PC12L_GMAC_GMDIO \
SAM_PINMUX(c, 12, l, periph)
/* pc13_gpio */
#define PC13_GPIO \
SAM_PINMUX(c, 13, gpio, gpio)
/* pc13a_eic_extint13 */
#define PC13A_EIC_EXTINT13 \
SAM_PINMUX(c, 13, a, periph)
/* pc13c_sercom7_pad1 */
#define PC13C_SERCOM7_PAD1 \
SAM_PINMUX(c, 13, c, periph)
/* pc13d_sercom6_pad0 */
#define PC13D_SERCOM6_PAD0 \
SAM_PINMUX(c, 13, d, periph)
/* pc13f_tcc0_wo3 */
#define PC13F_TCC0_WO3 \
SAM_PINMUX(c, 13, f, periph)
/* pc13g_tcc1_wo7 */
#define PC13G_TCC1_WO7 \
SAM_PINMUX(c, 13, g, periph)
/* pc13k_pcc_data11 */
#define PC13K_PCC_DATA11 \
SAM_PINMUX(c, 13, k, periph)
/* pc14_gpio */
#define PC14_GPIO \
SAM_PINMUX(c, 14, gpio, gpio)
/* pc14a_eic_extint14 */
#define PC14A_EIC_EXTINT14 \
SAM_PINMUX(c, 14, a, periph)
/* pc14c_sercom7_pad2 */
#define PC14C_SERCOM7_PAD2 \
SAM_PINMUX(c, 14, c, periph)
/* pc14d_sercom6_pad2 */
#define PC14D_SERCOM6_PAD2 \
SAM_PINMUX(c, 14, d, periph)
/* pc14f_tcc0_wo4 */
#define PC14F_TCC0_WO4 \
SAM_PINMUX(c, 14, f, periph)
/* pc14g_tcc1_wo0 */
#define PC14G_TCC1_WO0 \
SAM_PINMUX(c, 14, g, periph)
/* pc14k_pcc_data12 */
#define PC14K_PCC_DATA12 \
SAM_PINMUX(c, 14, k, periph)
/* pc14l_gmac_grx3 */
#define PC14L_GMAC_GRX3 \
SAM_PINMUX(c, 14, l, periph)
/* pc15_gpio */
#define PC15_GPIO \
SAM_PINMUX(c, 15, gpio, gpio)
/* pc15a_eic_extint15 */
#define PC15A_EIC_EXTINT15 \
SAM_PINMUX(c, 15, a, periph)
/* pc15c_sercom7_pad3 */
#define PC15C_SERCOM7_PAD3 \
SAM_PINMUX(c, 15, c, periph)
/* pc15d_sercom6_pad3 */
#define PC15D_SERCOM6_PAD3 \
SAM_PINMUX(c, 15, d, periph)
/* pc15f_tcc0_wo5 */
#define PC15F_TCC0_WO5 \
SAM_PINMUX(c, 15, f, periph)
/* pc15g_tcc1_wo1 */
#define PC15G_TCC1_WO1 \
SAM_PINMUX(c, 15, g, periph)
/* pc15k_pcc_data13 */
#define PC15K_PCC_DATA13 \
SAM_PINMUX(c, 15, k, periph)
/* pc15l_gmac_grx2 */
#define PC15L_GMAC_GRX2 \
SAM_PINMUX(c, 15, l, periph)
/* pc16_gpio */
#define PC16_GPIO \
SAM_PINMUX(c, 16, gpio, gpio)
/* pc16a_eic_extint0 */
#define PC16A_EIC_EXTINT0 \
SAM_PINMUX(c, 16, a, periph)
/* pc16c_sercom6_pad0 */
#define PC16C_SERCOM6_PAD0 \
SAM_PINMUX(c, 16, c, periph)
/* pc16d_sercom0_pad1 */
#define PC16D_SERCOM0_PAD1 \
SAM_PINMUX(c, 16, d, periph)
/* pc16f_tcc0_wo0 */
#define PC16F_TCC0_WO0 \
SAM_PINMUX(c, 16, f, periph)
/* pc16g_pdec_qdi0 */
#define PC16G_PDEC_QDI0 \
SAM_PINMUX(c, 16, g, periph)
/* pc16l_gmac_gtx2 */
#define PC16L_GMAC_GTX2 \
SAM_PINMUX(c, 16, l, periph)
/* pc17_gpio */
#define PC17_GPIO \
SAM_PINMUX(c, 17, gpio, gpio)
/* pc17a_eic_extint1 */
#define PC17A_EIC_EXTINT1 \
SAM_PINMUX(c, 17, a, periph)
/* pc17c_sercom6_pad1 */
#define PC17C_SERCOM6_PAD1 \
SAM_PINMUX(c, 17, c, periph)
/* pc17d_sercom0_pad0 */
#define PC17D_SERCOM0_PAD0 \
SAM_PINMUX(c, 17, d, periph)
/* pc17f_tcc0_wo1 */
#define PC17F_TCC0_WO1 \
SAM_PINMUX(c, 17, f, periph)
/* pc17g_pdec_qdi1 */
#define PC17G_PDEC_QDI1 \
SAM_PINMUX(c, 17, g, periph)
/* pc17l_gmac_gtx3 */
#define PC17L_GMAC_GTX3 \
SAM_PINMUX(c, 17, l, periph)
/* pc18_gpio */
#define PC18_GPIO \
SAM_PINMUX(c, 18, gpio, gpio)
/* pc18a_eic_extint2 */
#define PC18A_EIC_EXTINT2 \
SAM_PINMUX(c, 18, a, periph)
/* pc18c_sercom6_pad2 */
#define PC18C_SERCOM6_PAD2 \
SAM_PINMUX(c, 18, c, periph)
/* pc18d_sercom0_pad2 */
#define PC18D_SERCOM0_PAD2 \
SAM_PINMUX(c, 18, d, periph)
/* pc18f_tcc0_wo2 */
#define PC18F_TCC0_WO2 \
SAM_PINMUX(c, 18, f, periph)
/* pc18g_pdec_qdi2 */
#define PC18G_PDEC_QDI2 \
SAM_PINMUX(c, 18, g, periph)
/* pc18l_gmac_grxck */
#define PC18L_GMAC_GRXCK \
SAM_PINMUX(c, 18, l, periph)
/* pc19_gpio */
#define PC19_GPIO \
SAM_PINMUX(c, 19, gpio, gpio)
/* pc19a_eic_extint3 */
#define PC19A_EIC_EXTINT3 \
SAM_PINMUX(c, 19, a, periph)
/* pc19c_sercom6_pad3 */
#define PC19C_SERCOM6_PAD3 \
SAM_PINMUX(c, 19, c, periph)
/* pc19d_sercom0_pad3 */
#define PC19D_SERCOM0_PAD3 \
SAM_PINMUX(c, 19, d, periph)
/* pc19f_tcc0_wo3 */
#define PC19F_TCC0_WO3 \
SAM_PINMUX(c, 19, f, periph)
/* pc19l_gmac_gtxer */
#define PC19L_GMAC_GTXER \
SAM_PINMUX(c, 19, l, periph)
/* pc20_gpio */
#define PC20_GPIO \
SAM_PINMUX(c, 20, gpio, gpio)
/* pc20a_eic_extint4 */
#define PC20A_EIC_EXTINT4 \
SAM_PINMUX(c, 20, a, periph)
/* pc20f_tcc0_wo4 */
#define PC20F_TCC0_WO4 \
SAM_PINMUX(c, 20, f, periph)
/* pc20i_sdhc1_cd */
#define PC20I_SDHC1_CD \
SAM_PINMUX(c, 20, i, periph)
/* pc20l_gmac_grxdv */
#define PC20L_GMAC_GRXDV \
SAM_PINMUX(c, 20, l, periph)
/* pc20n_ccl_in9 */
#define PC20N_CCL_IN9 \
SAM_PINMUX(c, 20, n, periph)
/* pc21_gpio */
#define PC21_GPIO \
SAM_PINMUX(c, 21, gpio, gpio)
/* pc21a_eic_extint5 */
#define PC21A_EIC_EXTINT5 \
SAM_PINMUX(c, 21, a, periph)
/* pc21f_tcc0_wo5 */
#define PC21F_TCC0_WO5 \
SAM_PINMUX(c, 21, f, periph)
/* pc21i_sdhc1_wp */
#define PC21I_SDHC1_WP \
SAM_PINMUX(c, 21, i, periph)
/* pc21l_gmac_gcol */
#define PC21L_GMAC_GCOL \
SAM_PINMUX(c, 21, l, periph)
/* pc21n_ccl_in10 */
#define PC21N_CCL_IN10 \
SAM_PINMUX(c, 21, n, periph)
/* pc22_gpio */
#define PC22_GPIO \
SAM_PINMUX(c, 22, gpio, gpio)
/* pc22a_eic_extint6 */
#define PC22A_EIC_EXTINT6 \
SAM_PINMUX(c, 22, a, periph)
/* pc22c_sercom1_pad0 */
#define PC22C_SERCOM1_PAD0 \
SAM_PINMUX(c, 22, c, periph)
/* pc22d_sercom3_pad1 */
#define PC22D_SERCOM3_PAD1 \
SAM_PINMUX(c, 22, d, periph)
/* pc22f_tcc0_wo6 */
#define PC22F_TCC0_WO6 \
SAM_PINMUX(c, 22, f, periph)
/* pc22l_gmac_gmdc */
#define PC22L_GMAC_GMDC \
SAM_PINMUX(c, 22, l, periph)
/* pc23_gpio */
#define PC23_GPIO \
SAM_PINMUX(c, 23, gpio, gpio)
/* pc23a_eic_extint7 */
#define PC23A_EIC_EXTINT7 \
SAM_PINMUX(c, 23, a, periph)
/* pc23c_sercom1_pad1 */
#define PC23C_SERCOM1_PAD1 \
SAM_PINMUX(c, 23, c, periph)
/* pc23d_sercom3_pad0 */
#define PC23D_SERCOM3_PAD0 \
SAM_PINMUX(c, 23, d, periph)
/* pc23f_tcc0_wo7 */
#define PC23F_TCC0_WO7 \
SAM_PINMUX(c, 23, f, periph)
/* pc23l_gmac_gmdio */
#define PC23L_GMAC_GMDIO \
SAM_PINMUX(c, 23, l, periph)
/* pc24_gpio */
#define PC24_GPIO \
SAM_PINMUX(c, 24, gpio, gpio)
/* pc24a_eic_extint8 */
#define PC24A_EIC_EXTINT8 \
SAM_PINMUX(c, 24, a, periph)
/* pc24c_sercom0_pad2 */
#define PC24C_SERCOM0_PAD2 \
SAM_PINMUX(c, 24, c, periph)
/* pc24d_sercom2_pad2 */
#define PC24D_SERCOM2_PAD2 \
SAM_PINMUX(c, 24, d, periph)
/* pc24h_trace_data3 */
#define PC24H_TRACE_DATA3 \
SAM_PINMUX(c, 24, h, periph)
/* pc25_gpio */
#define PC25_GPIO \
SAM_PINMUX(c, 25, gpio, gpio)
/* pc25a_eic_extint9 */
#define PC25A_EIC_EXTINT9 \
SAM_PINMUX(c, 25, a, periph)
/* pc25c_sercom0_pad3 */
#define PC25C_SERCOM0_PAD3 \
SAM_PINMUX(c, 25, c, periph)
/* pc25d_sercom2_pad3 */
#define PC25D_SERCOM2_PAD3 \
SAM_PINMUX(c, 25, d, periph)
/* pc25h_trace_data2 */
#define PC25H_TRACE_DATA2 \
SAM_PINMUX(c, 25, h, periph)
/* pc26_gpio */
#define PC26_GPIO \
SAM_PINMUX(c, 26, gpio, gpio)
/* pc26a_eic_extint10 */
#define PC26A_EIC_EXTINT10 \
SAM_PINMUX(c, 26, a, periph)
/* pc26h_trace_data1 */
#define PC26H_TRACE_DATA1 \
SAM_PINMUX(c, 26, h, periph)
/* pc27_gpio */
#define PC27_GPIO \
SAM_PINMUX(c, 27, gpio, gpio)
/* pc27a_eic_extint11 */
#define PC27A_EIC_EXTINT11 \
SAM_PINMUX(c, 27, a, periph)
/* pc27c_sercom1_pad0 */
#define PC27C_SERCOM1_PAD0 \
SAM_PINMUX(c, 27, c, periph)
/* pc27h_trace_clk */
#define PC27H_TRACE_CLK \
SAM_PINMUX(c, 27, h, periph)
/* pc27m_swd_swo */
#define PC27M_SWD_SWO \
SAM_PINMUX(c, 27, m, periph)
/* pc27n_ccl_in4 */
#define PC27N_CCL_IN4 \
SAM_PINMUX(c, 27, n, periph)
/* pc28_gpio */
#define PC28_GPIO \
SAM_PINMUX(c, 28, gpio, gpio)
/* pc28a_eic_extint12 */
#define PC28A_EIC_EXTINT12 \
SAM_PINMUX(c, 28, a, periph)
/* pc28c_sercom1_pad1 */
#define PC28C_SERCOM1_PAD1 \
SAM_PINMUX(c, 28, c, periph)
/* pc28h_trace_data0 */
#define PC28H_TRACE_DATA0 \
SAM_PINMUX(c, 28, h, periph)
/* pc28n_ccl_in5 */
#define PC28N_CCL_IN5 \
SAM_PINMUX(c, 28, n, periph)
/* pc30_gpio */
#define PC30_GPIO \
SAM_PINMUX(c, 30, gpio, gpio)
/* pc30a_eic_extint14 */
#define PC30A_EIC_EXTINT14 \
SAM_PINMUX(c, 30, a, periph)
/* pc30b_adc1_ain12 */
#define PC30B_ADC1_AIN12 \
SAM_PINMUX(c, 30, b, periph)
/* pc31_gpio */
#define PC31_GPIO \
SAM_PINMUX(c, 31, gpio, gpio)
/* pc31a_eic_extint15 */
#define PC31A_EIC_EXTINT15 \
SAM_PINMUX(c, 31, a, periph)
/* pc31b_adc1_ain13 */
#define PC31B_ADC1_AIN13 \
SAM_PINMUX(c, 31, b, periph)
/* pd0_gpio */
#define PD0_GPIO \
SAM_PINMUX(d, 0, gpio, gpio)
/* pd0a_eic_extint0 */
#define PD0A_EIC_EXTINT0 \
SAM_PINMUX(d, 0, a, periph)
/* pd0b_adc1_ain14 */
#define PD0B_ADC1_AIN14 \
SAM_PINMUX(d, 0, b, periph)
/* pd1_gpio */
#define PD1_GPIO \
SAM_PINMUX(d, 1, gpio, gpio)
/* pd1a_eic_extint1 */
#define PD1A_EIC_EXTINT1 \
SAM_PINMUX(d, 1, a, periph)
/* pd1b_adc1_ain15 */
#define PD1B_ADC1_AIN15 \
SAM_PINMUX(d, 1, b, periph)
/* pd8_gpio */
#define PD8_GPIO \
SAM_PINMUX(d, 8, gpio, gpio)
/* pd8a_eic_extint3 */
#define PD8A_EIC_EXTINT3 \
SAM_PINMUX(d, 8, a, periph)
/* pd8c_sercom7_pad0 */
#define PD8C_SERCOM7_PAD0 \
SAM_PINMUX(d, 8, c, periph)
/* pd8d_sercom6_pad1 */
#define PD8D_SERCOM6_PAD1 \
SAM_PINMUX(d, 8, d, periph)
/* pd8f_tcc0_wo1 */
#define PD8F_TCC0_WO1 \
SAM_PINMUX(d, 8, f, periph)
/* pd9_gpio */
#define PD9_GPIO \
SAM_PINMUX(d, 9, gpio, gpio)
/* pd9a_eic_extint4 */
#define PD9A_EIC_EXTINT4 \
SAM_PINMUX(d, 9, a, periph)
/* pd9c_sercom7_pad1 */
#define PD9C_SERCOM7_PAD1 \
SAM_PINMUX(d, 9, c, periph)
/* pd9d_sercom6_pad0 */
#define PD9D_SERCOM6_PAD0 \
SAM_PINMUX(d, 9, d, periph)
/* pd9f_tcc0_wo2 */
#define PD9F_TCC0_WO2 \
SAM_PINMUX(d, 9, f, periph)
/* pd10_gpio */
#define PD10_GPIO \
SAM_PINMUX(d, 10, gpio, gpio)
/* pd10a_eic_extint5 */
#define PD10A_EIC_EXTINT5 \
SAM_PINMUX(d, 10, a, periph)
/* pd10c_sercom7_pad2 */
#define PD10C_SERCOM7_PAD2 \
SAM_PINMUX(d, 10, c, periph)
/* pd10d_sercom6_pad2 */
#define PD10D_SERCOM6_PAD2 \
SAM_PINMUX(d, 10, d, periph)
/* pd10f_tcc0_wo3 */
#define PD10F_TCC0_WO3 \
SAM_PINMUX(d, 10, f, periph)
/* pd11_gpio */
#define PD11_GPIO \
SAM_PINMUX(d, 11, gpio, gpio)
/* pd11a_eic_extint6 */
#define PD11A_EIC_EXTINT6 \
SAM_PINMUX(d, 11, a, periph)
/* pd11c_sercom7_pad3 */
#define PD11C_SERCOM7_PAD3 \
SAM_PINMUX(d, 11, c, periph)
/* pd11d_sercom6_pad3 */
#define PD11D_SERCOM6_PAD3 \
SAM_PINMUX(d, 11, d, periph)
/* pd11f_tcc0_wo4 */
#define PD11F_TCC0_WO4 \
SAM_PINMUX(d, 11, f, periph)
/* pd12_gpio */
#define PD12_GPIO \
SAM_PINMUX(d, 12, gpio, gpio)
/* pd12a_eic_extint7 */
#define PD12A_EIC_EXTINT7 \
SAM_PINMUX(d, 12, a, periph)
/* pd12f_tcc0_wo5 */
#define PD12F_TCC0_WO5 \
SAM_PINMUX(d, 12, f, periph)
/* pd20_gpio */
#define PD20_GPIO \
SAM_PINMUX(d, 20, gpio, gpio)
/* pd20a_eic_extint10 */
#define PD20A_EIC_EXTINT10 \
SAM_PINMUX(d, 20, a, periph)
/* pd20c_sercom1_pad2 */
#define PD20C_SERCOM1_PAD2 \
SAM_PINMUX(d, 20, c, periph)
/* pd20d_sercom3_pad2 */
#define PD20D_SERCOM3_PAD2 \
SAM_PINMUX(d, 20, d, periph)
/* pd20f_tcc1_wo0 */
#define PD20F_TCC1_WO0 \
SAM_PINMUX(d, 20, f, periph)
/* pd20i_sdhc1_cd */
#define PD20I_SDHC1_CD \
SAM_PINMUX(d, 20, i, periph)
/* pd21_gpio */
#define PD21_GPIO \
SAM_PINMUX(d, 21, gpio, gpio)
/* pd21a_eic_extint11 */
#define PD21A_EIC_EXTINT11 \
SAM_PINMUX(d, 21, a, periph)
/* pd21c_sercom1_pad3 */
#define PD21C_SERCOM1_PAD3 \
SAM_PINMUX(d, 21, c, periph)
/* pd21d_sercom3_pad3 */
#define PD21D_SERCOM3_PAD3 \
SAM_PINMUX(d, 21, d, periph)
/* pd21f_tcc1_wo1 */
#define PD21F_TCC1_WO1 \
SAM_PINMUX(d, 21, f, periph)
/* pd21i_sdhc1_wp */
#define PD21I_SDHC1_WP \
SAM_PINMUX(d, 21, i, periph)
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