diff --git a/include/dt-bindings/pinctrl/samc20e-pinctrl.h b/include/dt-bindings/pinctrl/samc20e-pinctrl.h
new file mode 100644
index 0000000..41fe3ff
--- /dev/null
+++ b/include/dt-bindings/pinctrl/samc20e-pinctrl.h
@@ -0,0 +1,715 @@
+/*
+ * Autogenerated file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/atmel_sam_pinctrl.h>
+
+/* pa0_gpio */
+#define PA0_GPIO \
+	SAM_PINMUX(a, 0, gpio, gpio)
+
+/* pa0a_eic_extint0 */
+#define PA0A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 0, a, periph)
+
+/* pa0d_sercom1_pad0 */
+#define PA0D_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 0, d, periph)
+
+/* pa0e_tc2_wo0 */
+#define PA0E_TC2_WO0 \
+	SAM_PINMUX(a, 0, e, periph)
+
+/* pa0h_ac_cmp2 */
+#define PA0H_AC_CMP2 \
+	SAM_PINMUX(a, 0, h, periph)
+
+/* pa1_gpio */
+#define PA1_GPIO \
+	SAM_PINMUX(a, 1, gpio, gpio)
+
+/* pa1a_eic_extint1 */
+#define PA1A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 1, a, periph)
+
+/* pa1d_sercom1_pad1 */
+#define PA1D_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 1, d, periph)
+
+/* pa1e_tc2_wo1 */
+#define PA1E_TC2_WO1 \
+	SAM_PINMUX(a, 1, e, periph)
+
+/* pa1h_ac_cmp3 */
+#define PA1H_AC_CMP3 \
+	SAM_PINMUX(a, 1, h, periph)
+
+/* pa2_gpio */
+#define PA2_GPIO \
+	SAM_PINMUX(a, 2, gpio, gpio)
+
+/* pa2a_eic_extint2 */
+#define PA2A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 2, a, periph)
+
+/* pa2b_adc0_ain0 */
+#define PA2B_ADC0_AIN0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ac_ain4 */
+#define PA2B_AC_AIN4 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ptc_y0 */
+#define PA2B_PTC_Y0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa3_gpio */
+#define PA3_GPIO \
+	SAM_PINMUX(a, 3, gpio, gpio)
+
+/* pa3a_eic_extint3 */
+#define PA3A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 3, a, periph)
+
+/* pa3b_anaref_vrefa */
+#define PA3B_ANAREF_VREFA \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_adc0_ain5 */
+#define PA3B_ADC0_AIN5 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ac_ain4 */
+#define PA3B_AC_AIN4 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ptc_y1 */
+#define PA3B_PTC_Y1 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa4_gpio */
+#define PA4_GPIO \
+	SAM_PINMUX(a, 4, gpio, gpio)
+
+/* pa4a_eic_extint4 */
+#define PA4A_EIC_EXTINT4 \
+	SAM_PINMUX(a, 4, a, periph)
+
+/* pa4b_anaref_vrefb */
+#define PA4B_ANAREF_VREFB \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_adc0_ain4 */
+#define PA4B_ADC0_AIN4 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ac_ain0 */
+#define PA4B_AC_AIN0 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ptc_y2 */
+#define PA4B_PTC_Y2 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4d_sercom0_pad0 */
+#define PA4D_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 4, d, periph)
+
+/* pa4e_tcc0_wo0 */
+#define PA4E_TCC0_WO0 \
+	SAM_PINMUX(a, 4, e, periph)
+
+/* pa5_gpio */
+#define PA5_GPIO \
+	SAM_PINMUX(a, 5, gpio, gpio)
+
+/* pa5a_eic_extint5 */
+#define PA5A_EIC_EXTINT5 \
+	SAM_PINMUX(a, 5, a, periph)
+
+/* pa5b_adc0_ain5 */
+#define PA5B_ADC0_AIN5 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ac_ain1 */
+#define PA5B_AC_AIN1 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ptc_y3 */
+#define PA5B_PTC_Y3 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5d_sercom0_pad1 */
+#define PA5D_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 5, d, periph)
+
+/* pa5e_tcc0_wo1 */
+#define PA5E_TCC0_WO1 \
+	SAM_PINMUX(a, 5, e, periph)
+
+/* pa6_gpio */
+#define PA6_GPIO \
+	SAM_PINMUX(a, 6, gpio, gpio)
+
+/* pa6a_eic_extint6 */
+#define PA6A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 6, a, periph)
+
+/* pa6b_adc0_ain6 */
+#define PA6B_ADC0_AIN6 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ac_ain2 */
+#define PA6B_AC_AIN2 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ptc_y4 */
+#define PA6B_PTC_Y4 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6d_sercom0_pad2 */
+#define PA6D_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 6, d, periph)
+
+/* pa6e_tcc1_wo0 */
+#define PA6E_TCC1_WO0 \
+	SAM_PINMUX(a, 6, e, periph)
+
+/* pa7_gpio */
+#define PA7_GPIO \
+	SAM_PINMUX(a, 7, gpio, gpio)
+
+/* pa7a_eic_extint7 */
+#define PA7A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 7, a, periph)
+
+/* pa7b_adc0_ain7 */
+#define PA7B_ADC0_AIN7 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ac_ain3 */
+#define PA7B_AC_AIN3 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ptc_y5 */
+#define PA7B_PTC_Y5 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7d_sercom0_pad3 */
+#define PA7D_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 7, d, periph)
+
+/* pa7e_tcc1_wo1 */
+#define PA7E_TCC1_WO1 \
+	SAM_PINMUX(a, 7, e, periph)
+
+/* pa8_gpio */
+#define PA8_GPIO \
+	SAM_PINMUX(a, 8, gpio, gpio)
+
+/* pa8a_eic_nmi */
+#define PA8A_EIC_NMI \
+	SAM_PINMUX(a, 8, a, periph)
+
+/* pa8b_adc0_ain8 */
+#define PA8B_ADC0_AIN8 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8b_ptc_xy16 */
+#define PA8B_PTC_XY16 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8c_sercom0_pad0 */
+#define PA8C_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 8, c, periph)
+
+/* pa8d_sercom2_pad0 */
+#define PA8D_SERCOM2_PAD0 \
+	SAM_PINMUX(a, 8, d, periph)
+
+/* pa8e_tcc0_wo0 */
+#define PA8E_TCC0_WO0 \
+	SAM_PINMUX(a, 8, e, periph)
+
+/* pa8f_tcc1_wo2 */
+#define PA8F_TCC1_WO2 \
+	SAM_PINMUX(a, 8, f, periph)
+
+/* pa9_gpio */
+#define PA9_GPIO \
+	SAM_PINMUX(a, 9, gpio, gpio)
+
+/* pa9a_eic_extint9 */
+#define PA9A_EIC_EXTINT9 \
+	SAM_PINMUX(a, 9, a, periph)
+
+/* pa9b_adc0_ain9 */
+#define PA9B_ADC0_AIN9 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9b_ptc_x1 */
+#define PA9B_PTC_X1 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9c_sercom0_pad1 */
+#define PA9C_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 9, c, periph)
+
+/* pa9d_sercom2_pad1 */
+#define PA9D_SERCOM2_PAD1 \
+	SAM_PINMUX(a, 9, d, periph)
+
+/* pa9e_tcc0_wo1 */
+#define PA9E_TCC0_WO1 \
+	SAM_PINMUX(a, 9, e, periph)
+
+/* pa9f_tcc1_wo3 */
+#define PA9F_TCC1_WO3 \
+	SAM_PINMUX(a, 9, f, periph)
+
+/* pa10_gpio */
+#define PA10_GPIO \
+	SAM_PINMUX(a, 10, gpio, gpio)
+
+/* pa10a_eic_extint10 */
+#define PA10A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 10, a, periph)
+
+/* pa10b_adc0_ain10 */
+#define PA10B_ADC0_AIN10 \
+	SAM_PINMUX(a, 10, b, periph)
+
+/* pa10b_ptc_x2 */
+#define PA10B_PTC_X2 \
+	SAM_PINMUX(a, 10, b, periph)
+
+/* pa10c_sercom0_pad2 */
+#define PA10C_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 10, c, periph)
+
+/* pa10d_sercom2_pad2 */
+#define PA10D_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 10, d, periph)
+
+/* pa10e_tcc1_wo0 */
+#define PA10E_TCC1_WO0 \
+	SAM_PINMUX(a, 10, e, periph)
+
+/* pa10f_tcc0_wo2 */
+#define PA10F_TCC0_WO2 \
+	SAM_PINMUX(a, 10, f, periph)
+
+/* pa10h_gclk_io4 */
+#define PA10H_GCLK_IO4 \
+	SAM_PINMUX(a, 10, h, periph)
+
+/* pa11_gpio */
+#define PA11_GPIO \
+	SAM_PINMUX(a, 11, gpio, gpio)
+
+/* pa11a_eic_extint11 */
+#define PA11A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 11, a, periph)
+
+/* pa11b_adc0_ain11 */
+#define PA11B_ADC0_AIN11 \
+	SAM_PINMUX(a, 11, b, periph)
+
+/* pa11b_ptc_x3 */
+#define PA11B_PTC_X3 \
+	SAM_PINMUX(a, 11, b, periph)
+
+/* pa11c_sercom0_pad3 */
+#define PA11C_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 11, c, periph)
+
+/* pa11d_sercom2_pad3 */
+#define PA11D_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 11, d, periph)
+
+/* pa11e_tcc1_wo1 */
+#define PA11E_TCC1_WO1 \
+	SAM_PINMUX(a, 11, e, periph)
+
+/* pa11f_tcc0_wo3 */
+#define PA11F_TCC0_WO3 \
+	SAM_PINMUX(a, 11, f, periph)
+
+/* pa11h_gclk_io5 */
+#define PA11H_GCLK_IO5 \
+	SAM_PINMUX(a, 11, h, periph)
+
+/* pa14_gpio */
+#define PA14_GPIO \
+	SAM_PINMUX(a, 14, gpio, gpio)
+
+/* pa14a_eic_extint14 */
+#define PA14A_EIC_EXTINT14 \
+	SAM_PINMUX(a, 14, a, periph)
+
+/* pa14c_sercom2_pad2 */
+#define PA14C_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 14, c, periph)
+
+/* pa14d_sercom4_pad2 */
+#define PA14D_SERCOM4_PAD2 \
+	SAM_PINMUX(a, 14, d, periph)
+
+/* pa14e_tc4_wo0 */
+#define PA14E_TC4_WO0 \
+	SAM_PINMUX(a, 14, e, periph)
+
+/* pa14f_tcc0_wo4 */
+#define PA14F_TCC0_WO4 \
+	SAM_PINMUX(a, 14, f, periph)
+
+/* pa14h_gclk_io0 */
+#define PA14H_GCLK_IO0 \
+	SAM_PINMUX(a, 14, h, periph)
+
+/* pa15_gpio */
+#define PA15_GPIO \
+	SAM_PINMUX(a, 15, gpio, gpio)
+
+/* pa15a_eic_extint15 */
+#define PA15A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 15, a, periph)
+
+/* pa15c_sercom2_pad3 */
+#define PA15C_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 15, c, periph)
+
+/* pa15d_sercom4_pad3 */
+#define PA15D_SERCOM4_PAD3 \
+	SAM_PINMUX(a, 15, d, periph)
+
+/* pa15e_tc4_wo1 */
+#define PA15E_TC4_WO1 \
+	SAM_PINMUX(a, 15, e, periph)
+
+/* pa15f_tcc0_wo5 */
+#define PA15F_TCC0_WO5 \
+	SAM_PINMUX(a, 15, f, periph)
+
+/* pa15h_gclk_io1 */
+#define PA15H_GCLK_IO1 \
+	SAM_PINMUX(a, 15, h, periph)
+
+/* pa16_gpio */
+#define PA16_GPIO \
+	SAM_PINMUX(a, 16, gpio, gpio)
+
+/* pa16a_eic_extint0 */
+#define PA16A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 16, a, periph)
+
+/* pa16b_ptc_x4 */
+#define PA16B_PTC_X4 \
+	SAM_PINMUX(a, 16, b, periph)
+
+/* pa16c_sercom1_pad0 */
+#define PA16C_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 16, c, periph)
+
+/* pa16d_sercom3_pad0 */
+#define PA16D_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 16, d, periph)
+
+/* pa16e_tcc2_wo0 */
+#define PA16E_TCC2_WO0 \
+	SAM_PINMUX(a, 16, e, periph)
+
+/* pa16f_tcc0_wo6 */
+#define PA16F_TCC0_WO6 \
+	SAM_PINMUX(a, 16, f, periph)
+
+/* pa16h_gclk_io2 */
+#define PA16H_GCLK_IO2 \
+	SAM_PINMUX(a, 16, h, periph)
+
+/* pa17_gpio */
+#define PA17_GPIO \
+	SAM_PINMUX(a, 17, gpio, gpio)
+
+/* pa17a_eic_extint1 */
+#define PA17A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 17, a, periph)
+
+/* pa17b_ptc_x5 */
+#define PA17B_PTC_X5 \
+	SAM_PINMUX(a, 17, b, periph)
+
+/* pa17c_sercom1_pad1 */
+#define PA17C_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 17, c, periph)
+
+/* pa17d_sercom3_pad1 */
+#define PA17D_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 17, d, periph)
+
+/* pa17e_tcc2_wo1 */
+#define PA17E_TCC2_WO1 \
+	SAM_PINMUX(a, 17, e, periph)
+
+/* pa17f_tcc0_wo7 */
+#define PA17F_TCC0_WO7 \
+	SAM_PINMUX(a, 17, f, periph)
+
+/* pa17h_gclk_io3 */
+#define PA17H_GCLK_IO3 \
+	SAM_PINMUX(a, 17, h, periph)
+
+/* pa18_gpio */
+#define PA18_GPIO \
+	SAM_PINMUX(a, 18, gpio, gpio)
+
+/* pa18a_eic_extint2 */
+#define PA18A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 18, a, periph)
+
+/* pa18b_ptc_x6 */
+#define PA18B_PTC_X6 \
+	SAM_PINMUX(a, 18, b, periph)
+
+/* pa18c_sercom1_pad2 */
+#define PA18C_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 18, c, periph)
+
+/* pa18d_sercom3_pad2 */
+#define PA18D_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 18, d, periph)
+
+/* pa18e_tc4_wo0 */
+#define PA18E_TC4_WO0 \
+	SAM_PINMUX(a, 18, e, periph)
+
+/* pa18f_tcc0_wo2 */
+#define PA18F_TCC0_WO2 \
+	SAM_PINMUX(a, 18, f, periph)
+
+/* pa18h_ac_cmp0 */
+#define PA18H_AC_CMP0 \
+	SAM_PINMUX(a, 18, h, periph)
+
+/* pa19_gpio */
+#define PA19_GPIO \
+	SAM_PINMUX(a, 19, gpio, gpio)
+
+/* pa19a_eic_extint3 */
+#define PA19A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 19, a, periph)
+
+/* pa19b_ptc_x7 */
+#define PA19B_PTC_X7 \
+	SAM_PINMUX(a, 19, b, periph)
+
+/* pa19c_sercom1_pad3 */
+#define PA19C_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 19, c, periph)
+
+/* pa19d_sercom3_pad3 */
+#define PA19D_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 19, d, periph)
+
+/* pa19e_tc4_wo1 */
+#define PA19E_TC4_WO1 \
+	SAM_PINMUX(a, 19, e, periph)
+
+/* pa19f_tcc0_wo3 */
+#define PA19F_TCC0_WO3 \
+	SAM_PINMUX(a, 19, f, periph)
+
+/* pa19h_ac_cmp1 */
+#define PA19H_AC_CMP1 \
+	SAM_PINMUX(a, 19, h, periph)
+
+/* pa22_gpio */
+#define PA22_GPIO \
+	SAM_PINMUX(a, 22, gpio, gpio)
+
+/* pa22a_eic_extint6 */
+#define PA22A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 22, a, periph)
+
+/* pa22b_ptc_x10 */
+#define PA22B_PTC_X10 \
+	SAM_PINMUX(a, 22, b, periph)
+
+/* pa22c_sercom3_pad0 */
+#define PA22C_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 22, c, periph)
+
+/* pa22d_sercom5_pad0 */
+#define PA22D_SERCOM5_PAD0 \
+	SAM_PINMUX(a, 22, d, periph)
+
+/* pa22e_tc0_wo0 */
+#define PA22E_TC0_WO0 \
+	SAM_PINMUX(a, 22, e, periph)
+
+/* pa22f_tcc0_wo4 */
+#define PA22F_TCC0_WO4 \
+	SAM_PINMUX(a, 22, f, periph)
+
+/* pa22h_gclk_io6 */
+#define PA22H_GCLK_IO6 \
+	SAM_PINMUX(a, 22, h, periph)
+
+/* pa23_gpio */
+#define PA23_GPIO \
+	SAM_PINMUX(a, 23, gpio, gpio)
+
+/* pa23a_eic_extint7 */
+#define PA23A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 23, a, periph)
+
+/* pa23b_ptc_x11 */
+#define PA23B_PTC_X11 \
+	SAM_PINMUX(a, 23, b, periph)
+
+/* pa23c_sercom3_pad1 */
+#define PA23C_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 23, c, periph)
+
+/* pa23d_sercom5_pad1 */
+#define PA23D_SERCOM5_PAD1 \
+	SAM_PINMUX(a, 23, d, periph)
+
+/* pa23e_tc0_wo1 */
+#define PA23E_TC0_WO1 \
+	SAM_PINMUX(a, 23, e, periph)
+
+/* pa23f_tcc0_wo5 */
+#define PA23F_TCC0_WO5 \
+	SAM_PINMUX(a, 23, f, periph)
+
+/* pa23h_gclk_io7 */
+#define PA23H_GCLK_IO7 \
+	SAM_PINMUX(a, 23, h, periph)
+
+/* pa24_gpio */
+#define PA24_GPIO \
+	SAM_PINMUX(a, 24, gpio, gpio)
+
+/* pa24a_eic_extint12 */
+#define PA24A_EIC_EXTINT12 \
+	SAM_PINMUX(a, 24, a, periph)
+
+/* pa24c_sercom3_pad2 */
+#define PA24C_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 24, c, periph)
+
+/* pa24d_sercom5_pad2 */
+#define PA24D_SERCOM5_PAD2 \
+	SAM_PINMUX(a, 24, d, periph)
+
+/* pa24e_tc1_wo0 */
+#define PA24E_TC1_WO0 \
+	SAM_PINMUX(a, 24, e, periph)
+
+/* pa24f_tcc1_wo2 */
+#define PA24F_TCC1_WO2 \
+	SAM_PINMUX(a, 24, f, periph)
+
+/* pa24h_ac_cmp2 */
+#define PA24H_AC_CMP2 \
+	SAM_PINMUX(a, 24, h, periph)
+
+/* pa25_gpio */
+#define PA25_GPIO \
+	SAM_PINMUX(a, 25, gpio, gpio)
+
+/* pa25a_eic_extint13 */
+#define PA25A_EIC_EXTINT13 \
+	SAM_PINMUX(a, 25, a, periph)
+
+/* pa25c_sercom3_pad3 */
+#define PA25C_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 25, c, periph)
+
+/* pa25d_sercom5_pad3 */
+#define PA25D_SERCOM5_PAD3 \
+	SAM_PINMUX(a, 25, d, periph)
+
+/* pa25e_tc1_wo1 */
+#define PA25E_TC1_WO1 \
+	SAM_PINMUX(a, 25, e, periph)
+
+/* pa25f_tcc1_wo3 */
+#define PA25F_TCC1_WO3 \
+	SAM_PINMUX(a, 25, f, periph)
+
+/* pa25h_ac_cmp3 */
+#define PA25H_AC_CMP3 \
+	SAM_PINMUX(a, 25, h, periph)
+
+/* pa27_gpio */
+#define PA27_GPIO \
+	SAM_PINMUX(a, 27, gpio, gpio)
+
+/* pa27a_eic_extint15 */
+#define PA27A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 27, a, periph)
+
+/* pa27h_gclk_io0 */
+#define PA27H_GCLK_IO0 \
+	SAM_PINMUX(a, 27, h, periph)
+
+/* pa28_gpio */
+#define PA28_GPIO \
+	SAM_PINMUX(a, 28, gpio, gpio)
+
+/* pa28a_eic_extint8 */
+#define PA28A_EIC_EXTINT8 \
+	SAM_PINMUX(a, 28, a, periph)
+
+/* pa28h_gclk_io0 */
+#define PA28H_GCLK_IO0 \
+	SAM_PINMUX(a, 28, h, periph)
+
+/* pa30_gpio */
+#define PA30_GPIO \
+	SAM_PINMUX(a, 30, gpio, gpio)
+
+/* pa30a_eic_extint10 */
+#define PA30A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 30, a, periph)
+
+/* pa30d_sercom1_pad2 */
+#define PA30D_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 30, d, periph)
+
+/* pa30e_tcc1_wo0 */
+#define PA30E_TCC1_WO0 \
+	SAM_PINMUX(a, 30, e, periph)
+
+/* pa30g_swd_clk */
+#define PA30G_SWD_CLK \
+	SAM_PINMUX(a, 30, g, periph)
+
+/* pa30h_gclk_io0 */
+#define PA30H_GCLK_IO0 \
+	SAM_PINMUX(a, 30, h, periph)
+
+/* pa31_gpio */
+#define PA31_GPIO \
+	SAM_PINMUX(a, 31, gpio, gpio)
+
+/* pa31a_eic_extint11 */
+#define PA31A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 31, a, periph)
+
+/* pa31d_sercom1_pad3 */
+#define PA31D_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 31, d, periph)
+
+/* pa31e_tcc1_wo1 */
+#define PA31E_TCC1_WO1 \
+	SAM_PINMUX(a, 31, e, periph)
+
+/* pa31g_swd_io */
+#define PA31G_SWD_IO \
+	SAM_PINMUX(a, 31, g, periph)
diff --git a/include/dt-bindings/pinctrl/samc20g-pinctrl.h b/include/dt-bindings/pinctrl/samc20g-pinctrl.h
new file mode 100644
index 0000000..ccdfc70
--- /dev/null
+++ b/include/dt-bindings/pinctrl/samc20g-pinctrl.h
@@ -0,0 +1,1011 @@
+/*
+ * Autogenerated file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/atmel_sam_pinctrl.h>
+
+/* pa0_gpio */
+#define PA0_GPIO \
+	SAM_PINMUX(a, 0, gpio, gpio)
+
+/* pa0a_eic_extint0 */
+#define PA0A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 0, a, periph)
+
+/* pa0d_sercom1_pad0 */
+#define PA0D_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 0, d, periph)
+
+/* pa0e_tc2_wo0 */
+#define PA0E_TC2_WO0 \
+	SAM_PINMUX(a, 0, e, periph)
+
+/* pa0h_ac_cmp2 */
+#define PA0H_AC_CMP2 \
+	SAM_PINMUX(a, 0, h, periph)
+
+/* pa1_gpio */
+#define PA1_GPIO \
+	SAM_PINMUX(a, 1, gpio, gpio)
+
+/* pa1a_eic_extint1 */
+#define PA1A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 1, a, periph)
+
+/* pa1d_sercom1_pad1 */
+#define PA1D_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 1, d, periph)
+
+/* pa1e_tc2_wo1 */
+#define PA1E_TC2_WO1 \
+	SAM_PINMUX(a, 1, e, periph)
+
+/* pa1h_ac_cmp3 */
+#define PA1H_AC_CMP3 \
+	SAM_PINMUX(a, 1, h, periph)
+
+/* pa2_gpio */
+#define PA2_GPIO \
+	SAM_PINMUX(a, 2, gpio, gpio)
+
+/* pa2a_eic_extint2 */
+#define PA2A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 2, a, periph)
+
+/* pa2b_adc0_ain0 */
+#define PA2B_ADC0_AIN0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ac_ain4 */
+#define PA2B_AC_AIN4 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ptc_y0 */
+#define PA2B_PTC_Y0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa3_gpio */
+#define PA3_GPIO \
+	SAM_PINMUX(a, 3, gpio, gpio)
+
+/* pa3a_eic_extint3 */
+#define PA3A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 3, a, periph)
+
+/* pa3b_anaref_vrefa */
+#define PA3B_ANAREF_VREFA \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_adc0_ain5 */
+#define PA3B_ADC0_AIN5 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ac_ain4 */
+#define PA3B_AC_AIN4 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ptc_y1 */
+#define PA3B_PTC_Y1 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa4_gpio */
+#define PA4_GPIO \
+	SAM_PINMUX(a, 4, gpio, gpio)
+
+/* pa4a_eic_extint4 */
+#define PA4A_EIC_EXTINT4 \
+	SAM_PINMUX(a, 4, a, periph)
+
+/* pa4b_anaref_vrefb */
+#define PA4B_ANAREF_VREFB \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_adc0_ain4 */
+#define PA4B_ADC0_AIN4 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ac_ain0 */
+#define PA4B_AC_AIN0 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ptc_y2 */
+#define PA4B_PTC_Y2 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4d_sercom0_pad0 */
+#define PA4D_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 4, d, periph)
+
+/* pa4e_tcc0_wo0 */
+#define PA4E_TCC0_WO0 \
+	SAM_PINMUX(a, 4, e, periph)
+
+/* pa5_gpio */
+#define PA5_GPIO \
+	SAM_PINMUX(a, 5, gpio, gpio)
+
+/* pa5a_eic_extint5 */
+#define PA5A_EIC_EXTINT5 \
+	SAM_PINMUX(a, 5, a, periph)
+
+/* pa5b_adc0_ain5 */
+#define PA5B_ADC0_AIN5 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ac_ain1 */
+#define PA5B_AC_AIN1 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ptc_y3 */
+#define PA5B_PTC_Y3 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5d_sercom0_pad1 */
+#define PA5D_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 5, d, periph)
+
+/* pa5e_tcc0_wo1 */
+#define PA5E_TCC0_WO1 \
+	SAM_PINMUX(a, 5, e, periph)
+
+/* pa6_gpio */
+#define PA6_GPIO \
+	SAM_PINMUX(a, 6, gpio, gpio)
+
+/* pa6a_eic_extint6 */
+#define PA6A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 6, a, periph)
+
+/* pa6b_adc0_ain6 */
+#define PA6B_ADC0_AIN6 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ac_ain2 */
+#define PA6B_AC_AIN2 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ptc_y4 */
+#define PA6B_PTC_Y4 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6d_sercom0_pad2 */
+#define PA6D_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 6, d, periph)
+
+/* pa6e_tcc1_wo0 */
+#define PA6E_TCC1_WO0 \
+	SAM_PINMUX(a, 6, e, periph)
+
+/* pa7_gpio */
+#define PA7_GPIO \
+	SAM_PINMUX(a, 7, gpio, gpio)
+
+/* pa7a_eic_extint7 */
+#define PA7A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 7, a, periph)
+
+/* pa7b_adc0_ain7 */
+#define PA7B_ADC0_AIN7 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ac_ain3 */
+#define PA7B_AC_AIN3 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ptc_y5 */
+#define PA7B_PTC_Y5 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7d_sercom0_pad3 */
+#define PA7D_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 7, d, periph)
+
+/* pa7e_tcc1_wo1 */
+#define PA7E_TCC1_WO1 \
+	SAM_PINMUX(a, 7, e, periph)
+
+/* pa8_gpio */
+#define PA8_GPIO \
+	SAM_PINMUX(a, 8, gpio, gpio)
+
+/* pa8a_eic_nmi */
+#define PA8A_EIC_NMI \
+	SAM_PINMUX(a, 8, a, periph)
+
+/* pa8b_adc0_ain8 */
+#define PA8B_ADC0_AIN8 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8b_ptc_xy16 */
+#define PA8B_PTC_XY16 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8c_sercom0_pad0 */
+#define PA8C_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 8, c, periph)
+
+/* pa8d_sercom2_pad0 */
+#define PA8D_SERCOM2_PAD0 \
+	SAM_PINMUX(a, 8, d, periph)
+
+/* pa8e_tcc0_wo0 */
+#define PA8E_TCC0_WO0 \
+	SAM_PINMUX(a, 8, e, periph)
+
+/* pa8f_tcc1_wo2 */
+#define PA8F_TCC1_WO2 \
+	SAM_PINMUX(a, 8, f, periph)
+
+/* pa9_gpio */
+#define PA9_GPIO \
+	SAM_PINMUX(a, 9, gpio, gpio)
+
+/* pa9a_eic_extint9 */
+#define PA9A_EIC_EXTINT9 \
+	SAM_PINMUX(a, 9, a, periph)
+
+/* pa9b_adc0_ain9 */
+#define PA9B_ADC0_AIN9 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9b_ptc_x1 */
+#define PA9B_PTC_X1 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9c_sercom0_pad1 */
+#define PA9C_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 9, c, periph)
+
+/* pa9d_sercom2_pad1 */
+#define PA9D_SERCOM2_PAD1 \
+	SAM_PINMUX(a, 9, d, periph)
+
+/* pa9e_tcc0_wo1 */
+#define PA9E_TCC0_WO1 \
+	SAM_PINMUX(a, 9, e, periph)
+
+/* pa9f_tcc1_wo3 */
+#define PA9F_TCC1_WO3 \
+	SAM_PINMUX(a, 9, f, periph)
+
+/* pa10_gpio */
+#define PA10_GPIO \
+	SAM_PINMUX(a, 10, gpio, gpio)
+
+/* pa10a_eic_extint10 */
+#define PA10A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 10, a, periph)
+
+/* pa10b_adc0_ain10 */
+#define PA10B_ADC0_AIN10 \
+	SAM_PINMUX(a, 10, b, periph)
+
+/* pa10b_ptc_x2 */
+#define PA10B_PTC_X2 \
+	SAM_PINMUX(a, 10, b, periph)
+
+/* pa10c_sercom0_pad2 */
+#define PA10C_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 10, c, periph)
+
+/* pa10d_sercom2_pad2 */
+#define PA10D_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 10, d, periph)
+
+/* pa10e_tcc1_wo0 */
+#define PA10E_TCC1_WO0 \
+	SAM_PINMUX(a, 10, e, periph)
+
+/* pa10f_tcc0_wo2 */
+#define PA10F_TCC0_WO2 \
+	SAM_PINMUX(a, 10, f, periph)
+
+/* pa10h_gclk_io4 */
+#define PA10H_GCLK_IO4 \
+	SAM_PINMUX(a, 10, h, periph)
+
+/* pa11_gpio */
+#define PA11_GPIO \
+	SAM_PINMUX(a, 11, gpio, gpio)
+
+/* pa11a_eic_extint11 */
+#define PA11A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 11, a, periph)
+
+/* pa11b_adc0_ain11 */
+#define PA11B_ADC0_AIN11 \
+	SAM_PINMUX(a, 11, b, periph)
+
+/* pa11b_ptc_x3 */
+#define PA11B_PTC_X3 \
+	SAM_PINMUX(a, 11, b, periph)
+
+/* pa11c_sercom0_pad3 */
+#define PA11C_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 11, c, periph)
+
+/* pa11d_sercom2_pad3 */
+#define PA11D_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 11, d, periph)
+
+/* pa11e_tcc1_wo1 */
+#define PA11E_TCC1_WO1 \
+	SAM_PINMUX(a, 11, e, periph)
+
+/* pa11f_tcc0_wo3 */
+#define PA11F_TCC0_WO3 \
+	SAM_PINMUX(a, 11, f, periph)
+
+/* pa11h_gclk_io5 */
+#define PA11H_GCLK_IO5 \
+	SAM_PINMUX(a, 11, h, periph)
+
+/* pa12_gpio */
+#define PA12_GPIO \
+	SAM_PINMUX(a, 12, gpio, gpio)
+
+/* pa12a_eic_extint12 */
+#define PA12A_EIC_EXTINT12 \
+	SAM_PINMUX(a, 12, a, periph)
+
+/* pa12c_sercom2_pad0 */
+#define PA12C_SERCOM2_PAD0 \
+	SAM_PINMUX(a, 12, c, periph)
+
+/* pa12d_sercom4_pad0 */
+#define PA12D_SERCOM4_PAD0 \
+	SAM_PINMUX(a, 12, d, periph)
+
+/* pa12e_tcc2_wo0 */
+#define PA12E_TCC2_WO0 \
+	SAM_PINMUX(a, 12, e, periph)
+
+/* pa12f_tcc0_wo6 */
+#define PA12F_TCC0_WO6 \
+	SAM_PINMUX(a, 12, f, periph)
+
+/* pa12h_ac_cmp0 */
+#define PA12H_AC_CMP0 \
+	SAM_PINMUX(a, 12, h, periph)
+
+/* pa13_gpio */
+#define PA13_GPIO \
+	SAM_PINMUX(a, 13, gpio, gpio)
+
+/* pa13a_eic_extint13 */
+#define PA13A_EIC_EXTINT13 \
+	SAM_PINMUX(a, 13, a, periph)
+
+/* pa13c_sercom2_pad1 */
+#define PA13C_SERCOM2_PAD1 \
+	SAM_PINMUX(a, 13, c, periph)
+
+/* pa13d_sercom4_pad1 */
+#define PA13D_SERCOM4_PAD1 \
+	SAM_PINMUX(a, 13, d, periph)
+
+/* pa13e_tcc2_wo1 */
+#define PA13E_TCC2_WO1 \
+	SAM_PINMUX(a, 13, e, periph)
+
+/* pa13f_tcc0_wo7 */
+#define PA13F_TCC0_WO7 \
+	SAM_PINMUX(a, 13, f, periph)
+
+/* pa13h_ac_cmp1 */
+#define PA13H_AC_CMP1 \
+	SAM_PINMUX(a, 13, h, periph)
+
+/* pa14_gpio */
+#define PA14_GPIO \
+	SAM_PINMUX(a, 14, gpio, gpio)
+
+/* pa14a_eic_extint14 */
+#define PA14A_EIC_EXTINT14 \
+	SAM_PINMUX(a, 14, a, periph)
+
+/* pa14c_sercom2_pad2 */
+#define PA14C_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 14, c, periph)
+
+/* pa14d_sercom4_pad2 */
+#define PA14D_SERCOM4_PAD2 \
+	SAM_PINMUX(a, 14, d, periph)
+
+/* pa14e_tc4_wo0 */
+#define PA14E_TC4_WO0 \
+	SAM_PINMUX(a, 14, e, periph)
+
+/* pa14f_tcc0_wo4 */
+#define PA14F_TCC0_WO4 \
+	SAM_PINMUX(a, 14, f, periph)
+
+/* pa14h_gclk_io0 */
+#define PA14H_GCLK_IO0 \
+	SAM_PINMUX(a, 14, h, periph)
+
+/* pa15_gpio */
+#define PA15_GPIO \
+	SAM_PINMUX(a, 15, gpio, gpio)
+
+/* pa15a_eic_extint15 */
+#define PA15A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 15, a, periph)
+
+/* pa15c_sercom2_pad3 */
+#define PA15C_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 15, c, periph)
+
+/* pa15d_sercom4_pad3 */
+#define PA15D_SERCOM4_PAD3 \
+	SAM_PINMUX(a, 15, d, periph)
+
+/* pa15e_tc4_wo1 */
+#define PA15E_TC4_WO1 \
+	SAM_PINMUX(a, 15, e, periph)
+
+/* pa15f_tcc0_wo5 */
+#define PA15F_TCC0_WO5 \
+	SAM_PINMUX(a, 15, f, periph)
+
+/* pa15h_gclk_io1 */
+#define PA15H_GCLK_IO1 \
+	SAM_PINMUX(a, 15, h, periph)
+
+/* pa16_gpio */
+#define PA16_GPIO \
+	SAM_PINMUX(a, 16, gpio, gpio)
+
+/* pa16a_eic_extint0 */
+#define PA16A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 16, a, periph)
+
+/* pa16b_ptc_x4 */
+#define PA16B_PTC_X4 \
+	SAM_PINMUX(a, 16, b, periph)
+
+/* pa16c_sercom1_pad0 */
+#define PA16C_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 16, c, periph)
+
+/* pa16d_sercom3_pad0 */
+#define PA16D_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 16, d, periph)
+
+/* pa16e_tcc2_wo0 */
+#define PA16E_TCC2_WO0 \
+	SAM_PINMUX(a, 16, e, periph)
+
+/* pa16f_tcc0_wo6 */
+#define PA16F_TCC0_WO6 \
+	SAM_PINMUX(a, 16, f, periph)
+
+/* pa16h_gclk_io2 */
+#define PA16H_GCLK_IO2 \
+	SAM_PINMUX(a, 16, h, periph)
+
+/* pa17_gpio */
+#define PA17_GPIO \
+	SAM_PINMUX(a, 17, gpio, gpio)
+
+/* pa17a_eic_extint1 */
+#define PA17A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 17, a, periph)
+
+/* pa17b_ptc_x5 */
+#define PA17B_PTC_X5 \
+	SAM_PINMUX(a, 17, b, periph)
+
+/* pa17c_sercom1_pad1 */
+#define PA17C_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 17, c, periph)
+
+/* pa17d_sercom3_pad1 */
+#define PA17D_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 17, d, periph)
+
+/* pa17e_tcc2_wo1 */
+#define PA17E_TCC2_WO1 \
+	SAM_PINMUX(a, 17, e, periph)
+
+/* pa17f_tcc0_wo7 */
+#define PA17F_TCC0_WO7 \
+	SAM_PINMUX(a, 17, f, periph)
+
+/* pa17h_gclk_io3 */
+#define PA17H_GCLK_IO3 \
+	SAM_PINMUX(a, 17, h, periph)
+
+/* pa18_gpio */
+#define PA18_GPIO \
+	SAM_PINMUX(a, 18, gpio, gpio)
+
+/* pa18a_eic_extint2 */
+#define PA18A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 18, a, periph)
+
+/* pa18b_ptc_x6 */
+#define PA18B_PTC_X6 \
+	SAM_PINMUX(a, 18, b, periph)
+
+/* pa18c_sercom1_pad2 */
+#define PA18C_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 18, c, periph)
+
+/* pa18d_sercom3_pad2 */
+#define PA18D_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 18, d, periph)
+
+/* pa18e_tc4_wo0 */
+#define PA18E_TC4_WO0 \
+	SAM_PINMUX(a, 18, e, periph)
+
+/* pa18f_tcc0_wo2 */
+#define PA18F_TCC0_WO2 \
+	SAM_PINMUX(a, 18, f, periph)
+
+/* pa18h_ac_cmp0 */
+#define PA18H_AC_CMP0 \
+	SAM_PINMUX(a, 18, h, periph)
+
+/* pa19_gpio */
+#define PA19_GPIO \
+	SAM_PINMUX(a, 19, gpio, gpio)
+
+/* pa19a_eic_extint3 */
+#define PA19A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 19, a, periph)
+
+/* pa19b_ptc_x7 */
+#define PA19B_PTC_X7 \
+	SAM_PINMUX(a, 19, b, periph)
+
+/* pa19c_sercom1_pad3 */
+#define PA19C_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 19, c, periph)
+
+/* pa19d_sercom3_pad3 */
+#define PA19D_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 19, d, periph)
+
+/* pa19e_tc4_wo1 */
+#define PA19E_TC4_WO1 \
+	SAM_PINMUX(a, 19, e, periph)
+
+/* pa19f_tcc0_wo3 */
+#define PA19F_TCC0_WO3 \
+	SAM_PINMUX(a, 19, f, periph)
+
+/* pa19h_ac_cmp1 */
+#define PA19H_AC_CMP1 \
+	SAM_PINMUX(a, 19, h, periph)
+
+/* pa20_gpio */
+#define PA20_GPIO \
+	SAM_PINMUX(a, 20, gpio, gpio)
+
+/* pa20a_eic_extint4 */
+#define PA20A_EIC_EXTINT4 \
+	SAM_PINMUX(a, 20, a, periph)
+
+/* pa20b_ptc_x8 */
+#define PA20B_PTC_X8 \
+	SAM_PINMUX(a, 20, b, periph)
+
+/* pa20c_sercom5_pad2 */
+#define PA20C_SERCOM5_PAD2 \
+	SAM_PINMUX(a, 20, c, periph)
+
+/* pa20d_sercom3_pad2 */
+#define PA20D_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 20, d, periph)
+
+/* pa20e_tc3_wo0 */
+#define PA20E_TC3_WO0 \
+	SAM_PINMUX(a, 20, e, periph)
+
+/* pa20f_tcc0_wo6 */
+#define PA20F_TCC0_WO6 \
+	SAM_PINMUX(a, 20, f, periph)
+
+/* pa20h_gclk_io4 */
+#define PA20H_GCLK_IO4 \
+	SAM_PINMUX(a, 20, h, periph)
+
+/* pa21_gpio */
+#define PA21_GPIO \
+	SAM_PINMUX(a, 21, gpio, gpio)
+
+/* pa21a_eic_extint5 */
+#define PA21A_EIC_EXTINT5 \
+	SAM_PINMUX(a, 21, a, periph)
+
+/* pa21b_ptc_x9 */
+#define PA21B_PTC_X9 \
+	SAM_PINMUX(a, 21, b, periph)
+
+/* pa21c_sercom5_pad3 */
+#define PA21C_SERCOM5_PAD3 \
+	SAM_PINMUX(a, 21, c, periph)
+
+/* pa21d_sercom3_pad3 */
+#define PA21D_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 21, d, periph)
+
+/* pa21e_tc3_wo1 */
+#define PA21E_TC3_WO1 \
+	SAM_PINMUX(a, 21, e, periph)
+
+/* pa21f_tcc0_wo7 */
+#define PA21F_TCC0_WO7 \
+	SAM_PINMUX(a, 21, f, periph)
+
+/* pa21h_gclk_io5 */
+#define PA21H_GCLK_IO5 \
+	SAM_PINMUX(a, 21, h, periph)
+
+/* pa22_gpio */
+#define PA22_GPIO \
+	SAM_PINMUX(a, 22, gpio, gpio)
+
+/* pa22a_eic_extint6 */
+#define PA22A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 22, a, periph)
+
+/* pa22b_ptc_x10 */
+#define PA22B_PTC_X10 \
+	SAM_PINMUX(a, 22, b, periph)
+
+/* pa22c_sercom3_pad0 */
+#define PA22C_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 22, c, periph)
+
+/* pa22d_sercom5_pad0 */
+#define PA22D_SERCOM5_PAD0 \
+	SAM_PINMUX(a, 22, d, periph)
+
+/* pa22e_tc0_wo0 */
+#define PA22E_TC0_WO0 \
+	SAM_PINMUX(a, 22, e, periph)
+
+/* pa22f_tcc0_wo4 */
+#define PA22F_TCC0_WO4 \
+	SAM_PINMUX(a, 22, f, periph)
+
+/* pa22h_gclk_io6 */
+#define PA22H_GCLK_IO6 \
+	SAM_PINMUX(a, 22, h, periph)
+
+/* pa23_gpio */
+#define PA23_GPIO \
+	SAM_PINMUX(a, 23, gpio, gpio)
+
+/* pa23a_eic_extint7 */
+#define PA23A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 23, a, periph)
+
+/* pa23b_ptc_x11 */
+#define PA23B_PTC_X11 \
+	SAM_PINMUX(a, 23, b, periph)
+
+/* pa23c_sercom3_pad1 */
+#define PA23C_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 23, c, periph)
+
+/* pa23d_sercom5_pad1 */
+#define PA23D_SERCOM5_PAD1 \
+	SAM_PINMUX(a, 23, d, periph)
+
+/* pa23e_tc0_wo1 */
+#define PA23E_TC0_WO1 \
+	SAM_PINMUX(a, 23, e, periph)
+
+/* pa23f_tcc0_wo5 */
+#define PA23F_TCC0_WO5 \
+	SAM_PINMUX(a, 23, f, periph)
+
+/* pa23h_gclk_io7 */
+#define PA23H_GCLK_IO7 \
+	SAM_PINMUX(a, 23, h, periph)
+
+/* pa24_gpio */
+#define PA24_GPIO \
+	SAM_PINMUX(a, 24, gpio, gpio)
+
+/* pa24a_eic_extint12 */
+#define PA24A_EIC_EXTINT12 \
+	SAM_PINMUX(a, 24, a, periph)
+
+/* pa24c_sercom3_pad2 */
+#define PA24C_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 24, c, periph)
+
+/* pa24d_sercom5_pad2 */
+#define PA24D_SERCOM5_PAD2 \
+	SAM_PINMUX(a, 24, d, periph)
+
+/* pa24e_tc1_wo0 */
+#define PA24E_TC1_WO0 \
+	SAM_PINMUX(a, 24, e, periph)
+
+/* pa24f_tcc1_wo2 */
+#define PA24F_TCC1_WO2 \
+	SAM_PINMUX(a, 24, f, periph)
+
+/* pa24h_ac_cmp2 */
+#define PA24H_AC_CMP2 \
+	SAM_PINMUX(a, 24, h, periph)
+
+/* pa25_gpio */
+#define PA25_GPIO \
+	SAM_PINMUX(a, 25, gpio, gpio)
+
+/* pa25a_eic_extint13 */
+#define PA25A_EIC_EXTINT13 \
+	SAM_PINMUX(a, 25, a, periph)
+
+/* pa25c_sercom3_pad3 */
+#define PA25C_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 25, c, periph)
+
+/* pa25d_sercom5_pad3 */
+#define PA25D_SERCOM5_PAD3 \
+	SAM_PINMUX(a, 25, d, periph)
+
+/* pa25e_tc1_wo1 */
+#define PA25E_TC1_WO1 \
+	SAM_PINMUX(a, 25, e, periph)
+
+/* pa25f_tcc1_wo3 */
+#define PA25F_TCC1_WO3 \
+	SAM_PINMUX(a, 25, f, periph)
+
+/* pa25h_ac_cmp3 */
+#define PA25H_AC_CMP3 \
+	SAM_PINMUX(a, 25, h, periph)
+
+/* pa27_gpio */
+#define PA27_GPIO \
+	SAM_PINMUX(a, 27, gpio, gpio)
+
+/* pa27a_eic_extint15 */
+#define PA27A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 27, a, periph)
+
+/* pa27h_gclk_io0 */
+#define PA27H_GCLK_IO0 \
+	SAM_PINMUX(a, 27, h, periph)
+
+/* pa28_gpio */
+#define PA28_GPIO \
+	SAM_PINMUX(a, 28, gpio, gpio)
+
+/* pa28a_eic_extint8 */
+#define PA28A_EIC_EXTINT8 \
+	SAM_PINMUX(a, 28, a, periph)
+
+/* pa28h_gclk_io0 */
+#define PA28H_GCLK_IO0 \
+	SAM_PINMUX(a, 28, h, periph)
+
+/* pa30_gpio */
+#define PA30_GPIO \
+	SAM_PINMUX(a, 30, gpio, gpio)
+
+/* pa30a_eic_extint10 */
+#define PA30A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 30, a, periph)
+
+/* pa30d_sercom1_pad2 */
+#define PA30D_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 30, d, periph)
+
+/* pa30e_tcc1_wo0 */
+#define PA30E_TCC1_WO0 \
+	SAM_PINMUX(a, 30, e, periph)
+
+/* pa30g_swd_clk */
+#define PA30G_SWD_CLK \
+	SAM_PINMUX(a, 30, g, periph)
+
+/* pa30h_gclk_io0 */
+#define PA30H_GCLK_IO0 \
+	SAM_PINMUX(a, 30, h, periph)
+
+/* pa31_gpio */
+#define PA31_GPIO \
+	SAM_PINMUX(a, 31, gpio, gpio)
+
+/* pa31a_eic_extint11 */
+#define PA31A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 31, a, periph)
+
+/* pa31d_sercom1_pad3 */
+#define PA31D_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 31, d, periph)
+
+/* pa31e_tcc1_wo1 */
+#define PA31E_TCC1_WO1 \
+	SAM_PINMUX(a, 31, e, periph)
+
+/* pa31g_swd_io */
+#define PA31G_SWD_IO \
+	SAM_PINMUX(a, 31, g, periph)
+
+/* pb2_gpio */
+#define PB2_GPIO \
+	SAM_PINMUX(b, 2, gpio, gpio)
+
+/* pb2a_eic_extint2 */
+#define PB2A_EIC_EXTINT2 \
+	SAM_PINMUX(b, 2, a, periph)
+
+/* pb2b_ptc_y8 */
+#define PB2B_PTC_Y8 \
+	SAM_PINMUX(b, 2, b, periph)
+
+/* pb2d_sercom5_pad0 */
+#define PB2D_SERCOM5_PAD0 \
+	SAM_PINMUX(b, 2, d, periph)
+
+/* pb2e_tc2_wo0 */
+#define PB2E_TC2_WO0 \
+	SAM_PINMUX(b, 2, e, periph)
+
+/* pb3_gpio */
+#define PB3_GPIO \
+	SAM_PINMUX(b, 3, gpio, gpio)
+
+/* pb3a_eic_extint3 */
+#define PB3A_EIC_EXTINT3 \
+	SAM_PINMUX(b, 3, a, periph)
+
+/* pb3b_ptc_y9 */
+#define PB3B_PTC_Y9 \
+	SAM_PINMUX(b, 3, b, periph)
+
+/* pb3d_sercom5_pad1 */
+#define PB3D_SERCOM5_PAD1 \
+	SAM_PINMUX(b, 3, d, periph)
+
+/* pb3e_tc2_wo1 */
+#define PB3E_TC2_WO1 \
+	SAM_PINMUX(b, 3, e, periph)
+
+/* pb8_gpio */
+#define PB8_GPIO \
+	SAM_PINMUX(b, 8, gpio, gpio)
+
+/* pb8a_eic_extint8 */
+#define PB8A_EIC_EXTINT8 \
+	SAM_PINMUX(b, 8, a, periph)
+
+/* pb8b_adc0_ain2 */
+#define PB8B_ADC0_AIN2 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8b_ptc_y14 */
+#define PB8B_PTC_Y14 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8d_sercom4_pad0 */
+#define PB8D_SERCOM4_PAD0 \
+	SAM_PINMUX(b, 8, d, periph)
+
+/* pb8e_tc0_wo0 */
+#define PB8E_TC0_WO0 \
+	SAM_PINMUX(b, 8, e, periph)
+
+/* pb9_gpio */
+#define PB9_GPIO \
+	SAM_PINMUX(b, 9, gpio, gpio)
+
+/* pb9a_eic_extint9 */
+#define PB9A_EIC_EXTINT9 \
+	SAM_PINMUX(b, 9, a, periph)
+
+/* pb9b_adc0_ain3 */
+#define PB9B_ADC0_AIN3 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9b_ptc_y15 */
+#define PB9B_PTC_Y15 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9d_sercom4_pad1 */
+#define PB9D_SERCOM4_PAD1 \
+	SAM_PINMUX(b, 9, d, periph)
+
+/* pb9e_tc0_wo1 */
+#define PB9E_TC0_WO1 \
+	SAM_PINMUX(b, 9, e, periph)
+
+/* pb10_gpio */
+#define PB10_GPIO \
+	SAM_PINMUX(b, 10, gpio, gpio)
+
+/* pb10a_eic_extint10 */
+#define PB10A_EIC_EXTINT10 \
+	SAM_PINMUX(b, 10, a, periph)
+
+/* pb10d_sercom4_pad2 */
+#define PB10D_SERCOM4_PAD2 \
+	SAM_PINMUX(b, 10, d, periph)
+
+/* pb10e_tc1_wo0 */
+#define PB10E_TC1_WO0 \
+	SAM_PINMUX(b, 10, e, periph)
+
+/* pb10f_tcc0_wo4 */
+#define PB10F_TCC0_WO4 \
+	SAM_PINMUX(b, 10, f, periph)
+
+/* pb10h_gclk_io4 */
+#define PB10H_GCLK_IO4 \
+	SAM_PINMUX(b, 10, h, periph)
+
+/* pb11_gpio */
+#define PB11_GPIO \
+	SAM_PINMUX(b, 11, gpio, gpio)
+
+/* pb11a_eic_extint11 */
+#define PB11A_EIC_EXTINT11 \
+	SAM_PINMUX(b, 11, a, periph)
+
+/* pb11d_sercom4_pad3 */
+#define PB11D_SERCOM4_PAD3 \
+	SAM_PINMUX(b, 11, d, periph)
+
+/* pb11e_tc1_wo1 */
+#define PB11E_TC1_WO1 \
+	SAM_PINMUX(b, 11, e, periph)
+
+/* pb11f_tcc0_wo5 */
+#define PB11F_TCC0_WO5 \
+	SAM_PINMUX(b, 11, f, periph)
+
+/* pb11h_gclk_io5 */
+#define PB11H_GCLK_IO5 \
+	SAM_PINMUX(b, 11, h, periph)
+
+/* pb22_gpio */
+#define PB22_GPIO \
+	SAM_PINMUX(b, 22, gpio, gpio)
+
+/* pb22a_eic_extint6 */
+#define PB22A_EIC_EXTINT6 \
+	SAM_PINMUX(b, 22, a, periph)
+
+/* pb22d_sercom5_pad2 */
+#define PB22D_SERCOM5_PAD2 \
+	SAM_PINMUX(b, 22, d, periph)
+
+/* pb22e_tc3_wo0 */
+#define PB22E_TC3_WO0 \
+	SAM_PINMUX(b, 22, e, periph)
+
+/* pb22h_gclk_io0 */
+#define PB22H_GCLK_IO0 \
+	SAM_PINMUX(b, 22, h, periph)
+
+/* pb23_gpio */
+#define PB23_GPIO \
+	SAM_PINMUX(b, 23, gpio, gpio)
+
+/* pb23a_eic_extint7 */
+#define PB23A_EIC_EXTINT7 \
+	SAM_PINMUX(b, 23, a, periph)
+
+/* pb23d_sercom5_pad3 */
+#define PB23D_SERCOM5_PAD3 \
+	SAM_PINMUX(b, 23, d, periph)
+
+/* pb23e_tc3_wo1 */
+#define PB23E_TC3_WO1 \
+	SAM_PINMUX(b, 23, e, periph)
+
+/* pb23h_gclk_io1 */
+#define PB23H_GCLK_IO1 \
+	SAM_PINMUX(b, 23, h, periph)
diff --git a/include/dt-bindings/pinctrl/samc20j-pinctrl.h b/include/dt-bindings/pinctrl/samc20j-pinctrl.h
new file mode 100644
index 0000000..b72defd
--- /dev/null
+++ b/include/dt-bindings/pinctrl/samc20j-pinctrl.h
@@ -0,0 +1,1323 @@
+/*
+ * Autogenerated file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/atmel_sam_pinctrl.h>
+
+/* pa0_gpio */
+#define PA0_GPIO \
+	SAM_PINMUX(a, 0, gpio, gpio)
+
+/* pa0a_eic_extint0 */
+#define PA0A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 0, a, periph)
+
+/* pa0d_sercom1_pad0 */
+#define PA0D_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 0, d, periph)
+
+/* pa0e_tc2_wo0 */
+#define PA0E_TC2_WO0 \
+	SAM_PINMUX(a, 0, e, periph)
+
+/* pa0h_ac_cmp2 */
+#define PA0H_AC_CMP2 \
+	SAM_PINMUX(a, 0, h, periph)
+
+/* pa1_gpio */
+#define PA1_GPIO \
+	SAM_PINMUX(a, 1, gpio, gpio)
+
+/* pa1a_eic_extint1 */
+#define PA1A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 1, a, periph)
+
+/* pa1d_sercom1_pad1 */
+#define PA1D_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 1, d, periph)
+
+/* pa1e_tc2_wo1 */
+#define PA1E_TC2_WO1 \
+	SAM_PINMUX(a, 1, e, periph)
+
+/* pa1h_ac_cmp3 */
+#define PA1H_AC_CMP3 \
+	SAM_PINMUX(a, 1, h, periph)
+
+/* pa2_gpio */
+#define PA2_GPIO \
+	SAM_PINMUX(a, 2, gpio, gpio)
+
+/* pa2a_eic_extint2 */
+#define PA2A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 2, a, periph)
+
+/* pa2b_adc0_ain0 */
+#define PA2B_ADC0_AIN0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ac_ain4 */
+#define PA2B_AC_AIN4 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ptc_y0 */
+#define PA2B_PTC_Y0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa3_gpio */
+#define PA3_GPIO \
+	SAM_PINMUX(a, 3, gpio, gpio)
+
+/* pa3a_eic_extint3 */
+#define PA3A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 3, a, periph)
+
+/* pa3b_anaref_vrefa */
+#define PA3B_ANAREF_VREFA \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_adc0_ain5 */
+#define PA3B_ADC0_AIN5 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ac_ain4 */
+#define PA3B_AC_AIN4 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ptc_y1 */
+#define PA3B_PTC_Y1 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa4_gpio */
+#define PA4_GPIO \
+	SAM_PINMUX(a, 4, gpio, gpio)
+
+/* pa4a_eic_extint4 */
+#define PA4A_EIC_EXTINT4 \
+	SAM_PINMUX(a, 4, a, periph)
+
+/* pa4b_anaref_vrefb */
+#define PA4B_ANAREF_VREFB \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_adc0_ain4 */
+#define PA4B_ADC0_AIN4 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ac_ain0 */
+#define PA4B_AC_AIN0 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ptc_y2 */
+#define PA4B_PTC_Y2 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4d_sercom0_pad0 */
+#define PA4D_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 4, d, periph)
+
+/* pa4e_tcc0_wo0 */
+#define PA4E_TCC0_WO0 \
+	SAM_PINMUX(a, 4, e, periph)
+
+/* pa5_gpio */
+#define PA5_GPIO \
+	SAM_PINMUX(a, 5, gpio, gpio)
+
+/* pa5a_eic_extint5 */
+#define PA5A_EIC_EXTINT5 \
+	SAM_PINMUX(a, 5, a, periph)
+
+/* pa5b_adc0_ain5 */
+#define PA5B_ADC0_AIN5 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ac_ain1 */
+#define PA5B_AC_AIN1 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ptc_y3 */
+#define PA5B_PTC_Y3 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5d_sercom0_pad1 */
+#define PA5D_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 5, d, periph)
+
+/* pa5e_tcc0_wo1 */
+#define PA5E_TCC0_WO1 \
+	SAM_PINMUX(a, 5, e, periph)
+
+/* pa6_gpio */
+#define PA6_GPIO \
+	SAM_PINMUX(a, 6, gpio, gpio)
+
+/* pa6a_eic_extint6 */
+#define PA6A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 6, a, periph)
+
+/* pa6b_adc0_ain6 */
+#define PA6B_ADC0_AIN6 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ac_ain2 */
+#define PA6B_AC_AIN2 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ptc_y4 */
+#define PA6B_PTC_Y4 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6d_sercom0_pad2 */
+#define PA6D_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 6, d, periph)
+
+/* pa6e_tcc1_wo0 */
+#define PA6E_TCC1_WO0 \
+	SAM_PINMUX(a, 6, e, periph)
+
+/* pa7_gpio */
+#define PA7_GPIO \
+	SAM_PINMUX(a, 7, gpio, gpio)
+
+/* pa7a_eic_extint7 */
+#define PA7A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 7, a, periph)
+
+/* pa7b_adc0_ain7 */
+#define PA7B_ADC0_AIN7 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ac_ain3 */
+#define PA7B_AC_AIN3 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ptc_y5 */
+#define PA7B_PTC_Y5 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7d_sercom0_pad3 */
+#define PA7D_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 7, d, periph)
+
+/* pa7e_tcc1_wo1 */
+#define PA7E_TCC1_WO1 \
+	SAM_PINMUX(a, 7, e, periph)
+
+/* pa8_gpio */
+#define PA8_GPIO \
+	SAM_PINMUX(a, 8, gpio, gpio)
+
+/* pa8a_eic_nmi */
+#define PA8A_EIC_NMI \
+	SAM_PINMUX(a, 8, a, periph)
+
+/* pa8b_adc0_ain8 */
+#define PA8B_ADC0_AIN8 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8b_ptc_xy16 */
+#define PA8B_PTC_XY16 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8c_sercom0_pad0 */
+#define PA8C_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 8, c, periph)
+
+/* pa8d_sercom2_pad0 */
+#define PA8D_SERCOM2_PAD0 \
+	SAM_PINMUX(a, 8, d, periph)
+
+/* pa8e_tcc0_wo0 */
+#define PA8E_TCC0_WO0 \
+	SAM_PINMUX(a, 8, e, periph)
+
+/* pa8f_tcc1_wo2 */
+#define PA8F_TCC1_WO2 \
+	SAM_PINMUX(a, 8, f, periph)
+
+/* pa9_gpio */
+#define PA9_GPIO \
+	SAM_PINMUX(a, 9, gpio, gpio)
+
+/* pa9a_eic_extint9 */
+#define PA9A_EIC_EXTINT9 \
+	SAM_PINMUX(a, 9, a, periph)
+
+/* pa9b_adc0_ain9 */
+#define PA9B_ADC0_AIN9 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9b_ptc_x1 */
+#define PA9B_PTC_X1 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9c_sercom0_pad1 */
+#define PA9C_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 9, c, periph)
+
+/* pa9d_sercom2_pad1 */
+#define PA9D_SERCOM2_PAD1 \
+	SAM_PINMUX(a, 9, d, periph)
+
+/* pa9e_tcc0_wo1 */
+#define PA9E_TCC0_WO1 \
+	SAM_PINMUX(a, 9, e, periph)
+
+/* pa9f_tcc1_wo3 */
+#define PA9F_TCC1_WO3 \
+	SAM_PINMUX(a, 9, f, periph)
+
+/* pa10_gpio */
+#define PA10_GPIO \
+	SAM_PINMUX(a, 10, gpio, gpio)
+
+/* pa10a_eic_extint10 */
+#define PA10A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 10, a, periph)
+
+/* pa10b_adc0_ain10 */
+#define PA10B_ADC0_AIN10 \
+	SAM_PINMUX(a, 10, b, periph)
+
+/* pa10b_ptc_x2 */
+#define PA10B_PTC_X2 \
+	SAM_PINMUX(a, 10, b, periph)
+
+/* pa10c_sercom0_pad2 */
+#define PA10C_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 10, c, periph)
+
+/* pa10d_sercom2_pad2 */
+#define PA10D_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 10, d, periph)
+
+/* pa10e_tcc1_wo0 */
+#define PA10E_TCC1_WO0 \
+	SAM_PINMUX(a, 10, e, periph)
+
+/* pa10f_tcc0_wo2 */
+#define PA10F_TCC0_WO2 \
+	SAM_PINMUX(a, 10, f, periph)
+
+/* pa10h_gclk_io4 */
+#define PA10H_GCLK_IO4 \
+	SAM_PINMUX(a, 10, h, periph)
+
+/* pa11_gpio */
+#define PA11_GPIO \
+	SAM_PINMUX(a, 11, gpio, gpio)
+
+/* pa11a_eic_extint11 */
+#define PA11A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 11, a, periph)
+
+/* pa11b_adc0_ain11 */
+#define PA11B_ADC0_AIN11 \
+	SAM_PINMUX(a, 11, b, periph)
+
+/* pa11b_ptc_x3 */
+#define PA11B_PTC_X3 \
+	SAM_PINMUX(a, 11, b, periph)
+
+/* pa11c_sercom0_pad3 */
+#define PA11C_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 11, c, periph)
+
+/* pa11d_sercom2_pad3 */
+#define PA11D_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 11, d, periph)
+
+/* pa11e_tcc1_wo1 */
+#define PA11E_TCC1_WO1 \
+	SAM_PINMUX(a, 11, e, periph)
+
+/* pa11f_tcc0_wo3 */
+#define PA11F_TCC0_WO3 \
+	SAM_PINMUX(a, 11, f, periph)
+
+/* pa11h_gclk_io5 */
+#define PA11H_GCLK_IO5 \
+	SAM_PINMUX(a, 11, h, periph)
+
+/* pa12_gpio */
+#define PA12_GPIO \
+	SAM_PINMUX(a, 12, gpio, gpio)
+
+/* pa12a_eic_extint12 */
+#define PA12A_EIC_EXTINT12 \
+	SAM_PINMUX(a, 12, a, periph)
+
+/* pa12c_sercom2_pad0 */
+#define PA12C_SERCOM2_PAD0 \
+	SAM_PINMUX(a, 12, c, periph)
+
+/* pa12d_sercom4_pad0 */
+#define PA12D_SERCOM4_PAD0 \
+	SAM_PINMUX(a, 12, d, periph)
+
+/* pa12e_tcc2_wo0 */
+#define PA12E_TCC2_WO0 \
+	SAM_PINMUX(a, 12, e, periph)
+
+/* pa12f_tcc0_wo6 */
+#define PA12F_TCC0_WO6 \
+	SAM_PINMUX(a, 12, f, periph)
+
+/* pa12h_ac_cmp0 */
+#define PA12H_AC_CMP0 \
+	SAM_PINMUX(a, 12, h, periph)
+
+/* pa13_gpio */
+#define PA13_GPIO \
+	SAM_PINMUX(a, 13, gpio, gpio)
+
+/* pa13a_eic_extint13 */
+#define PA13A_EIC_EXTINT13 \
+	SAM_PINMUX(a, 13, a, periph)
+
+/* pa13c_sercom2_pad1 */
+#define PA13C_SERCOM2_PAD1 \
+	SAM_PINMUX(a, 13, c, periph)
+
+/* pa13d_sercom4_pad1 */
+#define PA13D_SERCOM4_PAD1 \
+	SAM_PINMUX(a, 13, d, periph)
+
+/* pa13e_tcc2_wo1 */
+#define PA13E_TCC2_WO1 \
+	SAM_PINMUX(a, 13, e, periph)
+
+/* pa13f_tcc0_wo7 */
+#define PA13F_TCC0_WO7 \
+	SAM_PINMUX(a, 13, f, periph)
+
+/* pa13h_ac_cmp1 */
+#define PA13H_AC_CMP1 \
+	SAM_PINMUX(a, 13, h, periph)
+
+/* pa14_gpio */
+#define PA14_GPIO \
+	SAM_PINMUX(a, 14, gpio, gpio)
+
+/* pa14a_eic_extint14 */
+#define PA14A_EIC_EXTINT14 \
+	SAM_PINMUX(a, 14, a, periph)
+
+/* pa14c_sercom2_pad2 */
+#define PA14C_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 14, c, periph)
+
+/* pa14d_sercom4_pad2 */
+#define PA14D_SERCOM4_PAD2 \
+	SAM_PINMUX(a, 14, d, periph)
+
+/* pa14e_tc4_wo0 */
+#define PA14E_TC4_WO0 \
+	SAM_PINMUX(a, 14, e, periph)
+
+/* pa14f_tcc0_wo4 */
+#define PA14F_TCC0_WO4 \
+	SAM_PINMUX(a, 14, f, periph)
+
+/* pa14h_gclk_io0 */
+#define PA14H_GCLK_IO0 \
+	SAM_PINMUX(a, 14, h, periph)
+
+/* pa15_gpio */
+#define PA15_GPIO \
+	SAM_PINMUX(a, 15, gpio, gpio)
+
+/* pa15a_eic_extint15 */
+#define PA15A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 15, a, periph)
+
+/* pa15c_sercom2_pad3 */
+#define PA15C_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 15, c, periph)
+
+/* pa15d_sercom4_pad3 */
+#define PA15D_SERCOM4_PAD3 \
+	SAM_PINMUX(a, 15, d, periph)
+
+/* pa15e_tc4_wo1 */
+#define PA15E_TC4_WO1 \
+	SAM_PINMUX(a, 15, e, periph)
+
+/* pa15f_tcc0_wo5 */
+#define PA15F_TCC0_WO5 \
+	SAM_PINMUX(a, 15, f, periph)
+
+/* pa15h_gclk_io1 */
+#define PA15H_GCLK_IO1 \
+	SAM_PINMUX(a, 15, h, periph)
+
+/* pa16_gpio */
+#define PA16_GPIO \
+	SAM_PINMUX(a, 16, gpio, gpio)
+
+/* pa16a_eic_extint0 */
+#define PA16A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 16, a, periph)
+
+/* pa16b_ptc_x4 */
+#define PA16B_PTC_X4 \
+	SAM_PINMUX(a, 16, b, periph)
+
+/* pa16c_sercom1_pad0 */
+#define PA16C_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 16, c, periph)
+
+/* pa16d_sercom3_pad0 */
+#define PA16D_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 16, d, periph)
+
+/* pa16e_tcc2_wo0 */
+#define PA16E_TCC2_WO0 \
+	SAM_PINMUX(a, 16, e, periph)
+
+/* pa16f_tcc0_wo6 */
+#define PA16F_TCC0_WO6 \
+	SAM_PINMUX(a, 16, f, periph)
+
+/* pa16h_gclk_io2 */
+#define PA16H_GCLK_IO2 \
+	SAM_PINMUX(a, 16, h, periph)
+
+/* pa17_gpio */
+#define PA17_GPIO \
+	SAM_PINMUX(a, 17, gpio, gpio)
+
+/* pa17a_eic_extint1 */
+#define PA17A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 17, a, periph)
+
+/* pa17b_ptc_x5 */
+#define PA17B_PTC_X5 \
+	SAM_PINMUX(a, 17, b, periph)
+
+/* pa17c_sercom1_pad1 */
+#define PA17C_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 17, c, periph)
+
+/* pa17d_sercom3_pad1 */
+#define PA17D_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 17, d, periph)
+
+/* pa17e_tcc2_wo1 */
+#define PA17E_TCC2_WO1 \
+	SAM_PINMUX(a, 17, e, periph)
+
+/* pa17f_tcc0_wo7 */
+#define PA17F_TCC0_WO7 \
+	SAM_PINMUX(a, 17, f, periph)
+
+/* pa17h_gclk_io3 */
+#define PA17H_GCLK_IO3 \
+	SAM_PINMUX(a, 17, h, periph)
+
+/* pa18_gpio */
+#define PA18_GPIO \
+	SAM_PINMUX(a, 18, gpio, gpio)
+
+/* pa18a_eic_extint2 */
+#define PA18A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 18, a, periph)
+
+/* pa18b_ptc_x6 */
+#define PA18B_PTC_X6 \
+	SAM_PINMUX(a, 18, b, periph)
+
+/* pa18c_sercom1_pad2 */
+#define PA18C_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 18, c, periph)
+
+/* pa18d_sercom3_pad2 */
+#define PA18D_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 18, d, periph)
+
+/* pa18e_tc4_wo0 */
+#define PA18E_TC4_WO0 \
+	SAM_PINMUX(a, 18, e, periph)
+
+/* pa18f_tcc0_wo2 */
+#define PA18F_TCC0_WO2 \
+	SAM_PINMUX(a, 18, f, periph)
+
+/* pa18h_ac_cmp0 */
+#define PA18H_AC_CMP0 \
+	SAM_PINMUX(a, 18, h, periph)
+
+/* pa19_gpio */
+#define PA19_GPIO \
+	SAM_PINMUX(a, 19, gpio, gpio)
+
+/* pa19a_eic_extint3 */
+#define PA19A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 19, a, periph)
+
+/* pa19b_ptc_x7 */
+#define PA19B_PTC_X7 \
+	SAM_PINMUX(a, 19, b, periph)
+
+/* pa19c_sercom1_pad3 */
+#define PA19C_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 19, c, periph)
+
+/* pa19d_sercom3_pad3 */
+#define PA19D_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 19, d, periph)
+
+/* pa19e_tc4_wo1 */
+#define PA19E_TC4_WO1 \
+	SAM_PINMUX(a, 19, e, periph)
+
+/* pa19f_tcc0_wo3 */
+#define PA19F_TCC0_WO3 \
+	SAM_PINMUX(a, 19, f, periph)
+
+/* pa19h_ac_cmp1 */
+#define PA19H_AC_CMP1 \
+	SAM_PINMUX(a, 19, h, periph)
+
+/* pa20_gpio */
+#define PA20_GPIO \
+	SAM_PINMUX(a, 20, gpio, gpio)
+
+/* pa20a_eic_extint4 */
+#define PA20A_EIC_EXTINT4 \
+	SAM_PINMUX(a, 20, a, periph)
+
+/* pa20b_ptc_x8 */
+#define PA20B_PTC_X8 \
+	SAM_PINMUX(a, 20, b, periph)
+
+/* pa20c_sercom5_pad2 */
+#define PA20C_SERCOM5_PAD2 \
+	SAM_PINMUX(a, 20, c, periph)
+
+/* pa20d_sercom3_pad2 */
+#define PA20D_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 20, d, periph)
+
+/* pa20e_tc3_wo0 */
+#define PA20E_TC3_WO0 \
+	SAM_PINMUX(a, 20, e, periph)
+
+/* pa20f_tcc0_wo6 */
+#define PA20F_TCC0_WO6 \
+	SAM_PINMUX(a, 20, f, periph)
+
+/* pa20h_gclk_io4 */
+#define PA20H_GCLK_IO4 \
+	SAM_PINMUX(a, 20, h, periph)
+
+/* pa21_gpio */
+#define PA21_GPIO \
+	SAM_PINMUX(a, 21, gpio, gpio)
+
+/* pa21a_eic_extint5 */
+#define PA21A_EIC_EXTINT5 \
+	SAM_PINMUX(a, 21, a, periph)
+
+/* pa21b_ptc_x9 */
+#define PA21B_PTC_X9 \
+	SAM_PINMUX(a, 21, b, periph)
+
+/* pa21c_sercom5_pad3 */
+#define PA21C_SERCOM5_PAD3 \
+	SAM_PINMUX(a, 21, c, periph)
+
+/* pa21d_sercom3_pad3 */
+#define PA21D_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 21, d, periph)
+
+/* pa21e_tc3_wo1 */
+#define PA21E_TC3_WO1 \
+	SAM_PINMUX(a, 21, e, periph)
+
+/* pa21f_tcc0_wo7 */
+#define PA21F_TCC0_WO7 \
+	SAM_PINMUX(a, 21, f, periph)
+
+/* pa21h_gclk_io5 */
+#define PA21H_GCLK_IO5 \
+	SAM_PINMUX(a, 21, h, periph)
+
+/* pa22_gpio */
+#define PA22_GPIO \
+	SAM_PINMUX(a, 22, gpio, gpio)
+
+/* pa22a_eic_extint6 */
+#define PA22A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 22, a, periph)
+
+/* pa22b_ptc_x10 */
+#define PA22B_PTC_X10 \
+	SAM_PINMUX(a, 22, b, periph)
+
+/* pa22c_sercom3_pad0 */
+#define PA22C_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 22, c, periph)
+
+/* pa22d_sercom5_pad0 */
+#define PA22D_SERCOM5_PAD0 \
+	SAM_PINMUX(a, 22, d, periph)
+
+/* pa22e_tc0_wo0 */
+#define PA22E_TC0_WO0 \
+	SAM_PINMUX(a, 22, e, periph)
+
+/* pa22f_tcc0_wo4 */
+#define PA22F_TCC0_WO4 \
+	SAM_PINMUX(a, 22, f, periph)
+
+/* pa22h_gclk_io6 */
+#define PA22H_GCLK_IO6 \
+	SAM_PINMUX(a, 22, h, periph)
+
+/* pa23_gpio */
+#define PA23_GPIO \
+	SAM_PINMUX(a, 23, gpio, gpio)
+
+/* pa23a_eic_extint7 */
+#define PA23A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 23, a, periph)
+
+/* pa23b_ptc_x11 */
+#define PA23B_PTC_X11 \
+	SAM_PINMUX(a, 23, b, periph)
+
+/* pa23c_sercom3_pad1 */
+#define PA23C_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 23, c, periph)
+
+/* pa23d_sercom5_pad1 */
+#define PA23D_SERCOM5_PAD1 \
+	SAM_PINMUX(a, 23, d, periph)
+
+/* pa23e_tc0_wo1 */
+#define PA23E_TC0_WO1 \
+	SAM_PINMUX(a, 23, e, periph)
+
+/* pa23f_tcc0_wo5 */
+#define PA23F_TCC0_WO5 \
+	SAM_PINMUX(a, 23, f, periph)
+
+/* pa23h_gclk_io7 */
+#define PA23H_GCLK_IO7 \
+	SAM_PINMUX(a, 23, h, periph)
+
+/* pa24_gpio */
+#define PA24_GPIO \
+	SAM_PINMUX(a, 24, gpio, gpio)
+
+/* pa24a_eic_extint12 */
+#define PA24A_EIC_EXTINT12 \
+	SAM_PINMUX(a, 24, a, periph)
+
+/* pa24c_sercom3_pad2 */
+#define PA24C_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 24, c, periph)
+
+/* pa24d_sercom5_pad2 */
+#define PA24D_SERCOM5_PAD2 \
+	SAM_PINMUX(a, 24, d, periph)
+
+/* pa24e_tc1_wo0 */
+#define PA24E_TC1_WO0 \
+	SAM_PINMUX(a, 24, e, periph)
+
+/* pa24f_tcc1_wo2 */
+#define PA24F_TCC1_WO2 \
+	SAM_PINMUX(a, 24, f, periph)
+
+/* pa24h_ac_cmp2 */
+#define PA24H_AC_CMP2 \
+	SAM_PINMUX(a, 24, h, periph)
+
+/* pa25_gpio */
+#define PA25_GPIO \
+	SAM_PINMUX(a, 25, gpio, gpio)
+
+/* pa25a_eic_extint13 */
+#define PA25A_EIC_EXTINT13 \
+	SAM_PINMUX(a, 25, a, periph)
+
+/* pa25c_sercom3_pad3 */
+#define PA25C_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 25, c, periph)
+
+/* pa25d_sercom5_pad3 */
+#define PA25D_SERCOM5_PAD3 \
+	SAM_PINMUX(a, 25, d, periph)
+
+/* pa25e_tc1_wo1 */
+#define PA25E_TC1_WO1 \
+	SAM_PINMUX(a, 25, e, periph)
+
+/* pa25f_tcc1_wo3 */
+#define PA25F_TCC1_WO3 \
+	SAM_PINMUX(a, 25, f, periph)
+
+/* pa25h_ac_cmp3 */
+#define PA25H_AC_CMP3 \
+	SAM_PINMUX(a, 25, h, periph)
+
+/* pa27_gpio */
+#define PA27_GPIO \
+	SAM_PINMUX(a, 27, gpio, gpio)
+
+/* pa27a_eic_extint15 */
+#define PA27A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 27, a, periph)
+
+/* pa27h_gclk_io0 */
+#define PA27H_GCLK_IO0 \
+	SAM_PINMUX(a, 27, h, periph)
+
+/* pa28_gpio */
+#define PA28_GPIO \
+	SAM_PINMUX(a, 28, gpio, gpio)
+
+/* pa28a_eic_extint8 */
+#define PA28A_EIC_EXTINT8 \
+	SAM_PINMUX(a, 28, a, periph)
+
+/* pa28h_gclk_io0 */
+#define PA28H_GCLK_IO0 \
+	SAM_PINMUX(a, 28, h, periph)
+
+/* pa30_gpio */
+#define PA30_GPIO \
+	SAM_PINMUX(a, 30, gpio, gpio)
+
+/* pa30a_eic_extint10 */
+#define PA30A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 30, a, periph)
+
+/* pa30d_sercom1_pad2 */
+#define PA30D_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 30, d, periph)
+
+/* pa30e_tcc1_wo0 */
+#define PA30E_TCC1_WO0 \
+	SAM_PINMUX(a, 30, e, periph)
+
+/* pa30g_swd_clk */
+#define PA30G_SWD_CLK \
+	SAM_PINMUX(a, 30, g, periph)
+
+/* pa30h_gclk_io0 */
+#define PA30H_GCLK_IO0 \
+	SAM_PINMUX(a, 30, h, periph)
+
+/* pa31_gpio */
+#define PA31_GPIO \
+	SAM_PINMUX(a, 31, gpio, gpio)
+
+/* pa31a_eic_extint11 */
+#define PA31A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 31, a, periph)
+
+/* pa31d_sercom1_pad3 */
+#define PA31D_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 31, d, periph)
+
+/* pa31e_tcc1_wo1 */
+#define PA31E_TCC1_WO1 \
+	SAM_PINMUX(a, 31, e, periph)
+
+/* pa31g_swd_io */
+#define PA31G_SWD_IO \
+	SAM_PINMUX(a, 31, g, periph)
+
+/* pb0_gpio */
+#define PB0_GPIO \
+	SAM_PINMUX(b, 0, gpio, gpio)
+
+/* pb0a_eic_extint0 */
+#define PB0A_EIC_EXTINT0 \
+	SAM_PINMUX(b, 0, a, periph)
+
+/* pb0b_ptc_y6 */
+#define PB0B_PTC_Y6 \
+	SAM_PINMUX(b, 0, b, periph)
+
+/* pb0d_sercom5_pad2 */
+#define PB0D_SERCOM5_PAD2 \
+	SAM_PINMUX(b, 0, d, periph)
+
+/* pb0e_tc3_wo0 */
+#define PB0E_TC3_WO0 \
+	SAM_PINMUX(b, 0, e, periph)
+
+/* pb1_gpio */
+#define PB1_GPIO \
+	SAM_PINMUX(b, 1, gpio, gpio)
+
+/* pb1a_eic_extint1 */
+#define PB1A_EIC_EXTINT1 \
+	SAM_PINMUX(b, 1, a, periph)
+
+/* pb1b_ptc_y7 */
+#define PB1B_PTC_Y7 \
+	SAM_PINMUX(b, 1, b, periph)
+
+/* pb1d_sercom5_pad3 */
+#define PB1D_SERCOM5_PAD3 \
+	SAM_PINMUX(b, 1, d, periph)
+
+/* pb1e_tc3_wo1 */
+#define PB1E_TC3_WO1 \
+	SAM_PINMUX(b, 1, e, periph)
+
+/* pb2_gpio */
+#define PB2_GPIO \
+	SAM_PINMUX(b, 2, gpio, gpio)
+
+/* pb2a_eic_extint2 */
+#define PB2A_EIC_EXTINT2 \
+	SAM_PINMUX(b, 2, a, periph)
+
+/* pb2b_ptc_y8 */
+#define PB2B_PTC_Y8 \
+	SAM_PINMUX(b, 2, b, periph)
+
+/* pb2d_sercom5_pad0 */
+#define PB2D_SERCOM5_PAD0 \
+	SAM_PINMUX(b, 2, d, periph)
+
+/* pb2e_tc2_wo0 */
+#define PB2E_TC2_WO0 \
+	SAM_PINMUX(b, 2, e, periph)
+
+/* pb3_gpio */
+#define PB3_GPIO \
+	SAM_PINMUX(b, 3, gpio, gpio)
+
+/* pb3a_eic_extint3 */
+#define PB3A_EIC_EXTINT3 \
+	SAM_PINMUX(b, 3, a, periph)
+
+/* pb3b_ptc_y9 */
+#define PB3B_PTC_Y9 \
+	SAM_PINMUX(b, 3, b, periph)
+
+/* pb3d_sercom5_pad1 */
+#define PB3D_SERCOM5_PAD1 \
+	SAM_PINMUX(b, 3, d, periph)
+
+/* pb3e_tc2_wo1 */
+#define PB3E_TC2_WO1 \
+	SAM_PINMUX(b, 3, e, periph)
+
+/* pb4_gpio */
+#define PB4_GPIO \
+	SAM_PINMUX(b, 4, gpio, gpio)
+
+/* pb4a_eic_extint4 */
+#define PB4A_EIC_EXTINT4 \
+	SAM_PINMUX(b, 4, a, periph)
+
+/* pb4b_adc0_ain6 */
+#define PB4B_ADC0_AIN6 \
+	SAM_PINMUX(b, 4, b, periph)
+
+/* pb4b_ptc_y10 */
+#define PB4B_PTC_Y10 \
+	SAM_PINMUX(b, 4, b, periph)
+
+/* pb5_gpio */
+#define PB5_GPIO \
+	SAM_PINMUX(b, 5, gpio, gpio)
+
+/* pb5a_eic_extint5 */
+#define PB5A_EIC_EXTINT5 \
+	SAM_PINMUX(b, 5, a, periph)
+
+/* pb5b_adc0_ain7 */
+#define PB5B_ADC0_AIN7 \
+	SAM_PINMUX(b, 5, b, periph)
+
+/* pb5b_ac_ain6 */
+#define PB5B_AC_AIN6 \
+	SAM_PINMUX(b, 5, b, periph)
+
+/* pb5b_ptc_y11 */
+#define PB5B_PTC_Y11 \
+	SAM_PINMUX(b, 5, b, periph)
+
+/* pb6_gpio */
+#define PB6_GPIO \
+	SAM_PINMUX(b, 6, gpio, gpio)
+
+/* pb6a_eic_extint6 */
+#define PB6A_EIC_EXTINT6 \
+	SAM_PINMUX(b, 6, a, periph)
+
+/* pb6b_adc0_ain8 */
+#define PB6B_ADC0_AIN8 \
+	SAM_PINMUX(b, 6, b, periph)
+
+/* pb6b_ac_ain7 */
+#define PB6B_AC_AIN7 \
+	SAM_PINMUX(b, 6, b, periph)
+
+/* pb6b_ptc_y12 */
+#define PB6B_PTC_Y12 \
+	SAM_PINMUX(b, 6, b, periph)
+
+/* pb7_gpio */
+#define PB7_GPIO \
+	SAM_PINMUX(b, 7, gpio, gpio)
+
+/* pb7a_eic_extint7 */
+#define PB7A_EIC_EXTINT7 \
+	SAM_PINMUX(b, 7, a, periph)
+
+/* pb7b_adc0_ain9 */
+#define PB7B_ADC0_AIN9 \
+	SAM_PINMUX(b, 7, b, periph)
+
+/* pb7b_ptc_y13 */
+#define PB7B_PTC_Y13 \
+	SAM_PINMUX(b, 7, b, periph)
+
+/* pb8_gpio */
+#define PB8_GPIO \
+	SAM_PINMUX(b, 8, gpio, gpio)
+
+/* pb8a_eic_extint8 */
+#define PB8A_EIC_EXTINT8 \
+	SAM_PINMUX(b, 8, a, periph)
+
+/* pb8b_adc0_ain2 */
+#define PB8B_ADC0_AIN2 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8b_ptc_y14 */
+#define PB8B_PTC_Y14 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8d_sercom4_pad0 */
+#define PB8D_SERCOM4_PAD0 \
+	SAM_PINMUX(b, 8, d, periph)
+
+/* pb8e_tc0_wo0 */
+#define PB8E_TC0_WO0 \
+	SAM_PINMUX(b, 8, e, periph)
+
+/* pb9_gpio */
+#define PB9_GPIO \
+	SAM_PINMUX(b, 9, gpio, gpio)
+
+/* pb9a_eic_extint9 */
+#define PB9A_EIC_EXTINT9 \
+	SAM_PINMUX(b, 9, a, periph)
+
+/* pb9b_adc0_ain3 */
+#define PB9B_ADC0_AIN3 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9b_ptc_y15 */
+#define PB9B_PTC_Y15 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9d_sercom4_pad1 */
+#define PB9D_SERCOM4_PAD1 \
+	SAM_PINMUX(b, 9, d, periph)
+
+/* pb9e_tc0_wo1 */
+#define PB9E_TC0_WO1 \
+	SAM_PINMUX(b, 9, e, periph)
+
+/* pb10_gpio */
+#define PB10_GPIO \
+	SAM_PINMUX(b, 10, gpio, gpio)
+
+/* pb10a_eic_extint10 */
+#define PB10A_EIC_EXTINT10 \
+	SAM_PINMUX(b, 10, a, periph)
+
+/* pb10d_sercom4_pad2 */
+#define PB10D_SERCOM4_PAD2 \
+	SAM_PINMUX(b, 10, d, periph)
+
+/* pb10e_tc1_wo0 */
+#define PB10E_TC1_WO0 \
+	SAM_PINMUX(b, 10, e, periph)
+
+/* pb10f_tcc0_wo4 */
+#define PB10F_TCC0_WO4 \
+	SAM_PINMUX(b, 10, f, periph)
+
+/* pb10h_gclk_io4 */
+#define PB10H_GCLK_IO4 \
+	SAM_PINMUX(b, 10, h, periph)
+
+/* pb11_gpio */
+#define PB11_GPIO \
+	SAM_PINMUX(b, 11, gpio, gpio)
+
+/* pb11a_eic_extint11 */
+#define PB11A_EIC_EXTINT11 \
+	SAM_PINMUX(b, 11, a, periph)
+
+/* pb11d_sercom4_pad3 */
+#define PB11D_SERCOM4_PAD3 \
+	SAM_PINMUX(b, 11, d, periph)
+
+/* pb11e_tc1_wo1 */
+#define PB11E_TC1_WO1 \
+	SAM_PINMUX(b, 11, e, periph)
+
+/* pb11f_tcc0_wo5 */
+#define PB11F_TCC0_WO5 \
+	SAM_PINMUX(b, 11, f, periph)
+
+/* pb11h_gclk_io5 */
+#define PB11H_GCLK_IO5 \
+	SAM_PINMUX(b, 11, h, periph)
+
+/* pb12_gpio */
+#define PB12_GPIO \
+	SAM_PINMUX(b, 12, gpio, gpio)
+
+/* pb12a_eic_extint12 */
+#define PB12A_EIC_EXTINT12 \
+	SAM_PINMUX(b, 12, a, periph)
+
+/* pb12b_ptc_x12 */
+#define PB12B_PTC_X12 \
+	SAM_PINMUX(b, 12, b, periph)
+
+/* pb12c_sercom4_pad0 */
+#define PB12C_SERCOM4_PAD0 \
+	SAM_PINMUX(b, 12, c, periph)
+
+/* pb12e_tc0_wo0 */
+#define PB12E_TC0_WO0 \
+	SAM_PINMUX(b, 12, e, periph)
+
+/* pb12f_tcc0_wo6 */
+#define PB12F_TCC0_WO6 \
+	SAM_PINMUX(b, 12, f, periph)
+
+/* pb12h_gclk_io6 */
+#define PB12H_GCLK_IO6 \
+	SAM_PINMUX(b, 12, h, periph)
+
+/* pb13_gpio */
+#define PB13_GPIO \
+	SAM_PINMUX(b, 13, gpio, gpio)
+
+/* pb13a_eic_extint13 */
+#define PB13A_EIC_EXTINT13 \
+	SAM_PINMUX(b, 13, a, periph)
+
+/* pb13b_ptc_x13 */
+#define PB13B_PTC_X13 \
+	SAM_PINMUX(b, 13, b, periph)
+
+/* pb13c_sercom4_pad1 */
+#define PB13C_SERCOM4_PAD1 \
+	SAM_PINMUX(b, 13, c, periph)
+
+/* pb13e_tc0_wo1 */
+#define PB13E_TC0_WO1 \
+	SAM_PINMUX(b, 13, e, periph)
+
+/* pb13f_tcc0_wo7 */
+#define PB13F_TCC0_WO7 \
+	SAM_PINMUX(b, 13, f, periph)
+
+/* pb13h_gclk_io7 */
+#define PB13H_GCLK_IO7 \
+	SAM_PINMUX(b, 13, h, periph)
+
+/* pb14_gpio */
+#define PB14_GPIO \
+	SAM_PINMUX(b, 14, gpio, gpio)
+
+/* pb14a_eic_extint14 */
+#define PB14A_EIC_EXTINT14 \
+	SAM_PINMUX(b, 14, a, periph)
+
+/* pb14b_ptc_x14 */
+#define PB14B_PTC_X14 \
+	SAM_PINMUX(b, 14, b, periph)
+
+/* pb14c_sercom4_pad2 */
+#define PB14C_SERCOM4_PAD2 \
+	SAM_PINMUX(b, 14, c, periph)
+
+/* pb14e_tc1_wo0 */
+#define PB14E_TC1_WO0 \
+	SAM_PINMUX(b, 14, e, periph)
+
+/* pb14h_gclk_io0 */
+#define PB14H_GCLK_IO0 \
+	SAM_PINMUX(b, 14, h, periph)
+
+/* pb15_gpio */
+#define PB15_GPIO \
+	SAM_PINMUX(b, 15, gpio, gpio)
+
+/* pb15a_eic_extint15 */
+#define PB15A_EIC_EXTINT15 \
+	SAM_PINMUX(b, 15, a, periph)
+
+/* pb15b_ptc_x15 */
+#define PB15B_PTC_X15 \
+	SAM_PINMUX(b, 15, b, periph)
+
+/* pb15c_sercom4_pad3 */
+#define PB15C_SERCOM4_PAD3 \
+	SAM_PINMUX(b, 15, c, periph)
+
+/* pb15e_tc1_wo1 */
+#define PB15E_TC1_WO1 \
+	SAM_PINMUX(b, 15, e, periph)
+
+/* pb15h_gclk_io1 */
+#define PB15H_GCLK_IO1 \
+	SAM_PINMUX(b, 15, h, periph)
+
+/* pb16_gpio */
+#define PB16_GPIO \
+	SAM_PINMUX(b, 16, gpio, gpio)
+
+/* pb16a_eic_extint0 */
+#define PB16A_EIC_EXTINT0 \
+	SAM_PINMUX(b, 16, a, periph)
+
+/* pb16c_sercom5_pad0 */
+#define PB16C_SERCOM5_PAD0 \
+	SAM_PINMUX(b, 16, c, periph)
+
+/* pb16e_tc2_wo0 */
+#define PB16E_TC2_WO0 \
+	SAM_PINMUX(b, 16, e, periph)
+
+/* pb16f_tcc0_wo4 */
+#define PB16F_TCC0_WO4 \
+	SAM_PINMUX(b, 16, f, periph)
+
+/* pb16h_gclk_io2 */
+#define PB16H_GCLK_IO2 \
+	SAM_PINMUX(b, 16, h, periph)
+
+/* pb17_gpio */
+#define PB17_GPIO \
+	SAM_PINMUX(b, 17, gpio, gpio)
+
+/* pb17a_eic_extint1 */
+#define PB17A_EIC_EXTINT1 \
+	SAM_PINMUX(b, 17, a, periph)
+
+/* pb17c_sercom5_pad1 */
+#define PB17C_SERCOM5_PAD1 \
+	SAM_PINMUX(b, 17, c, periph)
+
+/* pb17e_tc2_wo1 */
+#define PB17E_TC2_WO1 \
+	SAM_PINMUX(b, 17, e, periph)
+
+/* pb17f_tcc0_wo5 */
+#define PB17F_TCC0_WO5 \
+	SAM_PINMUX(b, 17, f, periph)
+
+/* pb17h_gclk_io3 */
+#define PB17H_GCLK_IO3 \
+	SAM_PINMUX(b, 17, h, periph)
+
+/* pb22_gpio */
+#define PB22_GPIO \
+	SAM_PINMUX(b, 22, gpio, gpio)
+
+/* pb22a_eic_extint6 */
+#define PB22A_EIC_EXTINT6 \
+	SAM_PINMUX(b, 22, a, periph)
+
+/* pb22d_sercom5_pad2 */
+#define PB22D_SERCOM5_PAD2 \
+	SAM_PINMUX(b, 22, d, periph)
+
+/* pb22e_tc3_wo0 */
+#define PB22E_TC3_WO0 \
+	SAM_PINMUX(b, 22, e, periph)
+
+/* pb22h_gclk_io0 */
+#define PB22H_GCLK_IO0 \
+	SAM_PINMUX(b, 22, h, periph)
+
+/* pb23_gpio */
+#define PB23_GPIO \
+	SAM_PINMUX(b, 23, gpio, gpio)
+
+/* pb23a_eic_extint7 */
+#define PB23A_EIC_EXTINT7 \
+	SAM_PINMUX(b, 23, a, periph)
+
+/* pb23d_sercom5_pad3 */
+#define PB23D_SERCOM5_PAD3 \
+	SAM_PINMUX(b, 23, d, periph)
+
+/* pb23e_tc3_wo1 */
+#define PB23E_TC3_WO1 \
+	SAM_PINMUX(b, 23, e, periph)
+
+/* pb23h_gclk_io1 */
+#define PB23H_GCLK_IO1 \
+	SAM_PINMUX(b, 23, h, periph)
+
+/* pb30_gpio */
+#define PB30_GPIO \
+	SAM_PINMUX(b, 30, gpio, gpio)
+
+/* pb30a_eic_extint14 */
+#define PB30A_EIC_EXTINT14 \
+	SAM_PINMUX(b, 30, a, periph)
+
+/* pb30d_sercom5_pad0 */
+#define PB30D_SERCOM5_PAD0 \
+	SAM_PINMUX(b, 30, d, periph)
+
+/* pb30e_tcc0_wo0 */
+#define PB30E_TCC0_WO0 \
+	SAM_PINMUX(b, 30, e, periph)
+
+/* pb30f_tcc1_wo2 */
+#define PB30F_TCC1_WO2 \
+	SAM_PINMUX(b, 30, f, periph)
+
+/* pb30h_ac_cmp2 */
+#define PB30H_AC_CMP2 \
+	SAM_PINMUX(b, 30, h, periph)
+
+/* pb31_gpio */
+#define PB31_GPIO \
+	SAM_PINMUX(b, 31, gpio, gpio)
+
+/* pb31a_eic_extint15 */
+#define PB31A_EIC_EXTINT15 \
+	SAM_PINMUX(b, 31, a, periph)
+
+/* pb31d_sercom5_pad1 */
+#define PB31D_SERCOM5_PAD1 \
+	SAM_PINMUX(b, 31, d, periph)
+
+/* pb31e_tcc0_wo1 */
+#define PB31E_TCC0_WO1 \
+	SAM_PINMUX(b, 31, e, periph)
+
+/* pb31f_tcc1_wo3 */
+#define PB31F_TCC1_WO3 \
+	SAM_PINMUX(b, 31, f, periph)
+
+/* pb31h_ac_cmp3 */
+#define PB31H_AC_CMP3 \
+	SAM_PINMUX(b, 31, h, periph)
diff --git a/include/dt-bindings/pinctrl/samc20n-pinctrl.h b/include/dt-bindings/pinctrl/samc20n-pinctrl.h
new file mode 100644
index 0000000..377c097
--- /dev/null
+++ b/include/dt-bindings/pinctrl/samc20n-pinctrl.h
@@ -0,0 +1,1771 @@
+/*
+ * Autogenerated file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/atmel_sam_pinctrl.h>
+
+/* pa0_gpio */
+#define PA0_GPIO \
+	SAM_PINMUX(a, 0, gpio, gpio)
+
+/* pa0a_eic_extint0 */
+#define PA0A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 0, a, periph)
+
+/* pa0d_sercom1_pad0 */
+#define PA0D_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 0, d, periph)
+
+/* pa0e_tc2_wo0 */
+#define PA0E_TC2_WO0 \
+	SAM_PINMUX(a, 0, e, periph)
+
+/* pa0h_ac_cmp2 */
+#define PA0H_AC_CMP2 \
+	SAM_PINMUX(a, 0, h, periph)
+
+/* pa1_gpio */
+#define PA1_GPIO \
+	SAM_PINMUX(a, 1, gpio, gpio)
+
+/* pa1a_eic_extint1 */
+#define PA1A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 1, a, periph)
+
+/* pa1d_sercom1_pad1 */
+#define PA1D_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 1, d, periph)
+
+/* pa1e_tc2_wo1 */
+#define PA1E_TC2_WO1 \
+	SAM_PINMUX(a, 1, e, periph)
+
+/* pa1h_ac_cmp3 */
+#define PA1H_AC_CMP3 \
+	SAM_PINMUX(a, 1, h, periph)
+
+/* pa2_gpio */
+#define PA2_GPIO \
+	SAM_PINMUX(a, 2, gpio, gpio)
+
+/* pa2a_eic_extint2 */
+#define PA2A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 2, a, periph)
+
+/* pa2b_adc0_ain0 */
+#define PA2B_ADC0_AIN0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ac_ain4 */
+#define PA2B_AC_AIN4 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ptc_y0 */
+#define PA2B_PTC_Y0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa3_gpio */
+#define PA3_GPIO \
+	SAM_PINMUX(a, 3, gpio, gpio)
+
+/* pa3a_eic_extint3 */
+#define PA3A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 3, a, periph)
+
+/* pa3b_anaref_vrefa */
+#define PA3B_ANAREF_VREFA \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_adc0_ain5 */
+#define PA3B_ADC0_AIN5 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ac_ain4 */
+#define PA3B_AC_AIN4 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ptc_y1 */
+#define PA3B_PTC_Y1 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa4_gpio */
+#define PA4_GPIO \
+	SAM_PINMUX(a, 4, gpio, gpio)
+
+/* pa4a_eic_extint4 */
+#define PA4A_EIC_EXTINT4 \
+	SAM_PINMUX(a, 4, a, periph)
+
+/* pa4b_anaref_vrefb */
+#define PA4B_ANAREF_VREFB \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_adc0_ain4 */
+#define PA4B_ADC0_AIN4 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ac_ain0 */
+#define PA4B_AC_AIN0 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ptc_y2 */
+#define PA4B_PTC_Y2 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4d_sercom0_pad0 */
+#define PA4D_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 4, d, periph)
+
+/* pa4e_tc0_wo0 */
+#define PA4E_TC0_WO0 \
+	SAM_PINMUX(a, 4, e, periph)
+
+/* pa5_gpio */
+#define PA5_GPIO \
+	SAM_PINMUX(a, 5, gpio, gpio)
+
+/* pa5a_eic_extint5 */
+#define PA5A_EIC_EXTINT5 \
+	SAM_PINMUX(a, 5, a, periph)
+
+/* pa5b_adc0_ain5 */
+#define PA5B_ADC0_AIN5 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ac_ain1 */
+#define PA5B_AC_AIN1 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ptc_y3 */
+#define PA5B_PTC_Y3 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5d_sercom0_pad1 */
+#define PA5D_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 5, d, periph)
+
+/* pa5e_tc0_wo1 */
+#define PA5E_TC0_WO1 \
+	SAM_PINMUX(a, 5, e, periph)
+
+/* pa6_gpio */
+#define PA6_GPIO \
+	SAM_PINMUX(a, 6, gpio, gpio)
+
+/* pa6a_eic_extint6 */
+#define PA6A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 6, a, periph)
+
+/* pa6b_adc0_ain6 */
+#define PA6B_ADC0_AIN6 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ac_ain2 */
+#define PA6B_AC_AIN2 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ptc_y4 */
+#define PA6B_PTC_Y4 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6d_sercom0_pad2 */
+#define PA6D_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 6, d, periph)
+
+/* pa6e_tcc1_wo0 */
+#define PA6E_TCC1_WO0 \
+	SAM_PINMUX(a, 6, e, periph)
+
+/* pa7_gpio */
+#define PA7_GPIO \
+	SAM_PINMUX(a, 7, gpio, gpio)
+
+/* pa7a_eic_extint7 */
+#define PA7A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 7, a, periph)
+
+/* pa7b_adc0_ain7 */
+#define PA7B_ADC0_AIN7 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ac_ain3 */
+#define PA7B_AC_AIN3 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ptc_y5 */
+#define PA7B_PTC_Y5 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7d_sercom0_pad3 */
+#define PA7D_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 7, d, periph)
+
+/* pa7e_tcc1_wo1 */
+#define PA7E_TCC1_WO1 \
+	SAM_PINMUX(a, 7, e, periph)
+
+/* pa8_gpio */
+#define PA8_GPIO \
+	SAM_PINMUX(a, 8, gpio, gpio)
+
+/* pa8a_eic_nmi */
+#define PA8A_EIC_NMI \
+	SAM_PINMUX(a, 8, a, periph)
+
+/* pa8b_ptc_xy16 */
+#define PA8B_PTC_XY16 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8c_sercom0_pad0 */
+#define PA8C_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 8, c, periph)
+
+/* pa8d_sercom2_pad0 */
+#define PA8D_SERCOM2_PAD0 \
+	SAM_PINMUX(a, 8, d, periph)
+
+/* pa8e_tc0_wo0 */
+#define PA8E_TC0_WO0 \
+	SAM_PINMUX(a, 8, e, periph)
+
+/* pa8f_tcc0_wo0 */
+#define PA8F_TCC0_WO0 \
+	SAM_PINMUX(a, 8, f, periph)
+
+/* pa9_gpio */
+#define PA9_GPIO \
+	SAM_PINMUX(a, 9, gpio, gpio)
+
+/* pa9a_eic_extint9 */
+#define PA9A_EIC_EXTINT9 \
+	SAM_PINMUX(a, 9, a, periph)
+
+/* pa9b_ptc_x1 */
+#define PA9B_PTC_X1 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9c_sercom0_pad1 */
+#define PA9C_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 9, c, periph)
+
+/* pa9d_sercom2_pad1 */
+#define PA9D_SERCOM2_PAD1 \
+	SAM_PINMUX(a, 9, d, periph)
+
+/* pa9e_tc0_wo1 */
+#define PA9E_TC0_WO1 \
+	SAM_PINMUX(a, 9, e, periph)
+
+/* pa9f_tcc0_wo1 */
+#define PA9F_TCC0_WO1 \
+	SAM_PINMUX(a, 9, f, periph)
+
+/* pa10_gpio */
+#define PA10_GPIO \
+	SAM_PINMUX(a, 10, gpio, gpio)
+
+/* pa10a_eic_extint10 */
+#define PA10A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 10, a, periph)
+
+/* pa10b_ptc_x2 */
+#define PA10B_PTC_X2 \
+	SAM_PINMUX(a, 10, b, periph)
+
+/* pa10c_sercom0_pad2 */
+#define PA10C_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 10, c, periph)
+
+/* pa10d_sercom2_pad2 */
+#define PA10D_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 10, d, periph)
+
+/* pa10e_tc1_wo0 */
+#define PA10E_TC1_WO0 \
+	SAM_PINMUX(a, 10, e, periph)
+
+/* pa10f_tcc0_wo2 */
+#define PA10F_TCC0_WO2 \
+	SAM_PINMUX(a, 10, f, periph)
+
+/* pa10h_gclk_io4 */
+#define PA10H_GCLK_IO4 \
+	SAM_PINMUX(a, 10, h, periph)
+
+/* pa11_gpio */
+#define PA11_GPIO \
+	SAM_PINMUX(a, 11, gpio, gpio)
+
+/* pa11a_eic_extint11 */
+#define PA11A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 11, a, periph)
+
+/* pa11b_ptc_x3 */
+#define PA11B_PTC_X3 \
+	SAM_PINMUX(a, 11, b, periph)
+
+/* pa11c_sercom0_pad3 */
+#define PA11C_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 11, c, periph)
+
+/* pa11d_sercom2_pad3 */
+#define PA11D_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 11, d, periph)
+
+/* pa11e_tc1_wo1 */
+#define PA11E_TC1_WO1 \
+	SAM_PINMUX(a, 11, e, periph)
+
+/* pa11f_tcc0_wo3 */
+#define PA11F_TCC0_WO3 \
+	SAM_PINMUX(a, 11, f, periph)
+
+/* pa11h_gclk_io5 */
+#define PA11H_GCLK_IO5 \
+	SAM_PINMUX(a, 11, h, periph)
+
+/* pa12_gpio */
+#define PA12_GPIO \
+	SAM_PINMUX(a, 12, gpio, gpio)
+
+/* pa12a_eic_extint12 */
+#define PA12A_EIC_EXTINT12 \
+	SAM_PINMUX(a, 12, a, periph)
+
+/* pa12c_sercom2_pad0 */
+#define PA12C_SERCOM2_PAD0 \
+	SAM_PINMUX(a, 12, c, periph)
+
+/* pa12d_sercom4_pad0 */
+#define PA12D_SERCOM4_PAD0 \
+	SAM_PINMUX(a, 12, d, periph)
+
+/* pa12e_tcc2_wo0 */
+#define PA12E_TCC2_WO0 \
+	SAM_PINMUX(a, 12, e, periph)
+
+/* pa12f_tcc0_wo6 */
+#define PA12F_TCC0_WO6 \
+	SAM_PINMUX(a, 12, f, periph)
+
+/* pa12h_ac_cmp0 */
+#define PA12H_AC_CMP0 \
+	SAM_PINMUX(a, 12, h, periph)
+
+/* pa13_gpio */
+#define PA13_GPIO \
+	SAM_PINMUX(a, 13, gpio, gpio)
+
+/* pa13a_eic_extint13 */
+#define PA13A_EIC_EXTINT13 \
+	SAM_PINMUX(a, 13, a, periph)
+
+/* pa13c_sercom2_pad1 */
+#define PA13C_SERCOM2_PAD1 \
+	SAM_PINMUX(a, 13, c, periph)
+
+/* pa13d_sercom4_pad1 */
+#define PA13D_SERCOM4_PAD1 \
+	SAM_PINMUX(a, 13, d, periph)
+
+/* pa13e_tcc2_wo1 */
+#define PA13E_TCC2_WO1 \
+	SAM_PINMUX(a, 13, e, periph)
+
+/* pa13f_tcc0_wo7 */
+#define PA13F_TCC0_WO7 \
+	SAM_PINMUX(a, 13, f, periph)
+
+/* pa13h_ac_cmp1 */
+#define PA13H_AC_CMP1 \
+	SAM_PINMUX(a, 13, h, periph)
+
+/* pa14_gpio */
+#define PA14_GPIO \
+	SAM_PINMUX(a, 14, gpio, gpio)
+
+/* pa14a_eic_extint14 */
+#define PA14A_EIC_EXTINT14 \
+	SAM_PINMUX(a, 14, a, periph)
+
+/* pa14c_sercom2_pad2 */
+#define PA14C_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 14, c, periph)
+
+/* pa14d_sercom4_pad2 */
+#define PA14D_SERCOM4_PAD2 \
+	SAM_PINMUX(a, 14, d, periph)
+
+/* pa14e_tc3_wo0 */
+#define PA14E_TC3_WO0 \
+	SAM_PINMUX(a, 14, e, periph)
+
+/* pa14h_gclk_io0 */
+#define PA14H_GCLK_IO0 \
+	SAM_PINMUX(a, 14, h, periph)
+
+/* pa15_gpio */
+#define PA15_GPIO \
+	SAM_PINMUX(a, 15, gpio, gpio)
+
+/* pa15a_eic_extint15 */
+#define PA15A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 15, a, periph)
+
+/* pa15c_sercom2_pad3 */
+#define PA15C_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 15, c, periph)
+
+/* pa15d_sercom4_pad3 */
+#define PA15D_SERCOM4_PAD3 \
+	SAM_PINMUX(a, 15, d, periph)
+
+/* pa15e_tc3_wo1 */
+#define PA15E_TC3_WO1 \
+	SAM_PINMUX(a, 15, e, periph)
+
+/* pa15h_gclk_io1 */
+#define PA15H_GCLK_IO1 \
+	SAM_PINMUX(a, 15, h, periph)
+
+/* pa16_gpio */
+#define PA16_GPIO \
+	SAM_PINMUX(a, 16, gpio, gpio)
+
+/* pa16a_eic_extint0 */
+#define PA16A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 16, a, periph)
+
+/* pa16b_ptc_x4 */
+#define PA16B_PTC_X4 \
+	SAM_PINMUX(a, 16, b, periph)
+
+/* pa16c_sercom1_pad0 */
+#define PA16C_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 16, c, periph)
+
+/* pa16d_sercom3_pad0 */
+#define PA16D_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 16, d, periph)
+
+/* pa16e_tcc2_wo0 */
+#define PA16E_TCC2_WO0 \
+	SAM_PINMUX(a, 16, e, periph)
+
+/* pa16f_tcc1_wo6 */
+#define PA16F_TCC1_WO6 \
+	SAM_PINMUX(a, 16, f, periph)
+
+/* pa16h_gclk_io2 */
+#define PA16H_GCLK_IO2 \
+	SAM_PINMUX(a, 16, h, periph)
+
+/* pa17_gpio */
+#define PA17_GPIO \
+	SAM_PINMUX(a, 17, gpio, gpio)
+
+/* pa17a_eic_extint1 */
+#define PA17A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 17, a, periph)
+
+/* pa17b_ptc_x5 */
+#define PA17B_PTC_X5 \
+	SAM_PINMUX(a, 17, b, periph)
+
+/* pa17c_sercom1_pad1 */
+#define PA17C_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 17, c, periph)
+
+/* pa17d_sercom3_pad1 */
+#define PA17D_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 17, d, periph)
+
+/* pa17e_tcc2_wo1 */
+#define PA17E_TCC2_WO1 \
+	SAM_PINMUX(a, 17, e, periph)
+
+/* pa17f_tcc1_wo7 */
+#define PA17F_TCC1_WO7 \
+	SAM_PINMUX(a, 17, f, periph)
+
+/* pa17h_gclk_io3 */
+#define PA17H_GCLK_IO3 \
+	SAM_PINMUX(a, 17, h, periph)
+
+/* pa18_gpio */
+#define PA18_GPIO \
+	SAM_PINMUX(a, 18, gpio, gpio)
+
+/* pa18a_eic_extint2 */
+#define PA18A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 18, a, periph)
+
+/* pa18b_ptc_x6 */
+#define PA18B_PTC_X6 \
+	SAM_PINMUX(a, 18, b, periph)
+
+/* pa18c_sercom1_pad2 */
+#define PA18C_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 18, c, periph)
+
+/* pa18d_sercom3_pad2 */
+#define PA18D_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 18, d, periph)
+
+/* pa18e_tc3_wo0 */
+#define PA18E_TC3_WO0 \
+	SAM_PINMUX(a, 18, e, periph)
+
+/* pa18f_tcc1_wo2 */
+#define PA18F_TCC1_WO2 \
+	SAM_PINMUX(a, 18, f, periph)
+
+/* pa18h_ac_cmp0 */
+#define PA18H_AC_CMP0 \
+	SAM_PINMUX(a, 18, h, periph)
+
+/* pa19_gpio */
+#define PA19_GPIO \
+	SAM_PINMUX(a, 19, gpio, gpio)
+
+/* pa19a_eic_extint3 */
+#define PA19A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 19, a, periph)
+
+/* pa19b_ptc_x7 */
+#define PA19B_PTC_X7 \
+	SAM_PINMUX(a, 19, b, periph)
+
+/* pa19c_sercom1_pad3 */
+#define PA19C_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 19, c, periph)
+
+/* pa19d_sercom3_pad3 */
+#define PA19D_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 19, d, periph)
+
+/* pa19e_tc3_wo1 */
+#define PA19E_TC3_WO1 \
+	SAM_PINMUX(a, 19, e, periph)
+
+/* pa19f_tcc1_wo3 */
+#define PA19F_TCC1_WO3 \
+	SAM_PINMUX(a, 19, f, periph)
+
+/* pa19h_ac_cmp1 */
+#define PA19H_AC_CMP1 \
+	SAM_PINMUX(a, 19, h, periph)
+
+/* pa20_gpio */
+#define PA20_GPIO \
+	SAM_PINMUX(a, 20, gpio, gpio)
+
+/* pa20a_eic_extint4 */
+#define PA20A_EIC_EXTINT4 \
+	SAM_PINMUX(a, 20, a, periph)
+
+/* pa20b_ptc_x8 */
+#define PA20B_PTC_X8 \
+	SAM_PINMUX(a, 20, b, periph)
+
+/* pa20c_sercom5_pad2 */
+#define PA20C_SERCOM5_PAD2 \
+	SAM_PINMUX(a, 20, c, periph)
+
+/* pa20d_sercom3_pad2 */
+#define PA20D_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 20, d, periph)
+
+/* pa20e_tc7_wo0 */
+#define PA20E_TC7_WO0 \
+	SAM_PINMUX(a, 20, e, periph)
+
+/* pa20f_tcc2_wo0 */
+#define PA20F_TCC2_WO0 \
+	SAM_PINMUX(a, 20, f, periph)
+
+/* pa20h_gclk_io4 */
+#define PA20H_GCLK_IO4 \
+	SAM_PINMUX(a, 20, h, periph)
+
+/* pa21_gpio */
+#define PA21_GPIO \
+	SAM_PINMUX(a, 21, gpio, gpio)
+
+/* pa21a_eic_extint5 */
+#define PA21A_EIC_EXTINT5 \
+	SAM_PINMUX(a, 21, a, periph)
+
+/* pa21b_ptc_x9 */
+#define PA21B_PTC_X9 \
+	SAM_PINMUX(a, 21, b, periph)
+
+/* pa21c_sercom5_pad3 */
+#define PA21C_SERCOM5_PAD3 \
+	SAM_PINMUX(a, 21, c, periph)
+
+/* pa21d_sercom3_pad3 */
+#define PA21D_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 21, d, periph)
+
+/* pa21e_tc7_wo1 */
+#define PA21E_TC7_WO1 \
+	SAM_PINMUX(a, 21, e, periph)
+
+/* pa21f_tcc2_wo1 */
+#define PA21F_TCC2_WO1 \
+	SAM_PINMUX(a, 21, f, periph)
+
+/* pa21h_gclk_io5 */
+#define PA21H_GCLK_IO5 \
+	SAM_PINMUX(a, 21, h, periph)
+
+/* pa22_gpio */
+#define PA22_GPIO \
+	SAM_PINMUX(a, 22, gpio, gpio)
+
+/* pa22a_eic_extint6 */
+#define PA22A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 22, a, periph)
+
+/* pa22b_ptc_x10 */
+#define PA22B_PTC_X10 \
+	SAM_PINMUX(a, 22, b, periph)
+
+/* pa22c_sercom3_pad0 */
+#define PA22C_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 22, c, periph)
+
+/* pa22d_sercom5_pad0 */
+#define PA22D_SERCOM5_PAD0 \
+	SAM_PINMUX(a, 22, d, periph)
+
+/* pa22e_tc4_wo0 */
+#define PA22E_TC4_WO0 \
+	SAM_PINMUX(a, 22, e, periph)
+
+/* pa22f_tcc1_wo0 */
+#define PA22F_TCC1_WO0 \
+	SAM_PINMUX(a, 22, f, periph)
+
+/* pa22h_gclk_io6 */
+#define PA22H_GCLK_IO6 \
+	SAM_PINMUX(a, 22, h, periph)
+
+/* pa23_gpio */
+#define PA23_GPIO \
+	SAM_PINMUX(a, 23, gpio, gpio)
+
+/* pa23a_eic_extint7 */
+#define PA23A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 23, a, periph)
+
+/* pa23b_ptc_x11 */
+#define PA23B_PTC_X11 \
+	SAM_PINMUX(a, 23, b, periph)
+
+/* pa23c_sercom3_pad1 */
+#define PA23C_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 23, c, periph)
+
+/* pa23d_sercom5_pad1 */
+#define PA23D_SERCOM5_PAD1 \
+	SAM_PINMUX(a, 23, d, periph)
+
+/* pa23e_tc4_wo1 */
+#define PA23E_TC4_WO1 \
+	SAM_PINMUX(a, 23, e, periph)
+
+/* pa23f_tcc1_wo1 */
+#define PA23F_TCC1_WO1 \
+	SAM_PINMUX(a, 23, f, periph)
+
+/* pa23h_gclk_io7 */
+#define PA23H_GCLK_IO7 \
+	SAM_PINMUX(a, 23, h, periph)
+
+/* pa24_gpio */
+#define PA24_GPIO \
+	SAM_PINMUX(a, 24, gpio, gpio)
+
+/* pa24a_eic_extint12 */
+#define PA24A_EIC_EXTINT12 \
+	SAM_PINMUX(a, 24, a, periph)
+
+/* pa24c_sercom3_pad2 */
+#define PA24C_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 24, c, periph)
+
+/* pa24d_sercom5_pad2 */
+#define PA24D_SERCOM5_PAD2 \
+	SAM_PINMUX(a, 24, d, periph)
+
+/* pa24e_tc5_wo0 */
+#define PA24E_TC5_WO0 \
+	SAM_PINMUX(a, 24, e, periph)
+
+/* pa24f_tcc2_wo0 */
+#define PA24F_TCC2_WO0 \
+	SAM_PINMUX(a, 24, f, periph)
+
+/* pa24h_ac_cmp2 */
+#define PA24H_AC_CMP2 \
+	SAM_PINMUX(a, 24, h, periph)
+
+/* pa25_gpio */
+#define PA25_GPIO \
+	SAM_PINMUX(a, 25, gpio, gpio)
+
+/* pa25a_eic_extint13 */
+#define PA25A_EIC_EXTINT13 \
+	SAM_PINMUX(a, 25, a, periph)
+
+/* pa25c_sercom3_pad3 */
+#define PA25C_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 25, c, periph)
+
+/* pa25d_sercom5_pad3 */
+#define PA25D_SERCOM5_PAD3 \
+	SAM_PINMUX(a, 25, d, periph)
+
+/* pa25e_tc5_wo1 */
+#define PA25E_TC5_WO1 \
+	SAM_PINMUX(a, 25, e, periph)
+
+/* pa25f_tcc2_wo1 */
+#define PA25F_TCC2_WO1 \
+	SAM_PINMUX(a, 25, f, periph)
+
+/* pa25h_ac_cmp3 */
+#define PA25H_AC_CMP3 \
+	SAM_PINMUX(a, 25, h, periph)
+
+/* pa27_gpio */
+#define PA27_GPIO \
+	SAM_PINMUX(a, 27, gpio, gpio)
+
+/* pa27a_eic_extint15 */
+#define PA27A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 27, a, periph)
+
+/* pa27h_gclk_io0 */
+#define PA27H_GCLK_IO0 \
+	SAM_PINMUX(a, 27, h, periph)
+
+/* pa28_gpio */
+#define PA28_GPIO \
+	SAM_PINMUX(a, 28, gpio, gpio)
+
+/* pa28a_eic_extint8 */
+#define PA28A_EIC_EXTINT8 \
+	SAM_PINMUX(a, 28, a, periph)
+
+/* pa28h_gclk_io0 */
+#define PA28H_GCLK_IO0 \
+	SAM_PINMUX(a, 28, h, periph)
+
+/* pa30_gpio */
+#define PA30_GPIO \
+	SAM_PINMUX(a, 30, gpio, gpio)
+
+/* pa30a_eic_extint10 */
+#define PA30A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 30, a, periph)
+
+/* pa30d_sercom1_pad2 */
+#define PA30D_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 30, d, periph)
+
+/* pa30e_tc1_wo0 */
+#define PA30E_TC1_WO0 \
+	SAM_PINMUX(a, 30, e, periph)
+
+/* pa30g_swd_clk */
+#define PA30G_SWD_CLK \
+	SAM_PINMUX(a, 30, g, periph)
+
+/* pa30h_gclk_io0 */
+#define PA30H_GCLK_IO0 \
+	SAM_PINMUX(a, 30, h, periph)
+
+/* pa31_gpio */
+#define PA31_GPIO \
+	SAM_PINMUX(a, 31, gpio, gpio)
+
+/* pa31a_eic_extint11 */
+#define PA31A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 31, a, periph)
+
+/* pa31d_sercom1_pad3 */
+#define PA31D_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 31, d, periph)
+
+/* pa31e_tc1_wo1 */
+#define PA31E_TC1_WO1 \
+	SAM_PINMUX(a, 31, e, periph)
+
+/* pa31g_swd_io */
+#define PA31G_SWD_IO \
+	SAM_PINMUX(a, 31, g, periph)
+
+/* pb0_gpio */
+#define PB0_GPIO \
+	SAM_PINMUX(b, 0, gpio, gpio)
+
+/* pb0a_eic_extint0 */
+#define PB0A_EIC_EXTINT0 \
+	SAM_PINMUX(b, 0, a, periph)
+
+/* pb0b_ptc_y6 */
+#define PB0B_PTC_Y6 \
+	SAM_PINMUX(b, 0, b, periph)
+
+/* pb0d_sercom5_pad2 */
+#define PB0D_SERCOM5_PAD2 \
+	SAM_PINMUX(b, 0, d, periph)
+
+/* pb0e_tc7_wo0 */
+#define PB0E_TC7_WO0 \
+	SAM_PINMUX(b, 0, e, periph)
+
+/* pb1_gpio */
+#define PB1_GPIO \
+	SAM_PINMUX(b, 1, gpio, gpio)
+
+/* pb1a_eic_extint1 */
+#define PB1A_EIC_EXTINT1 \
+	SAM_PINMUX(b, 1, a, periph)
+
+/* pb1b_ptc_y7 */
+#define PB1B_PTC_Y7 \
+	SAM_PINMUX(b, 1, b, periph)
+
+/* pb1d_sercom5_pad3 */
+#define PB1D_SERCOM5_PAD3 \
+	SAM_PINMUX(b, 1, d, periph)
+
+/* pb1e_tc7_wo1 */
+#define PB1E_TC7_WO1 \
+	SAM_PINMUX(b, 1, e, periph)
+
+/* pb2_gpio */
+#define PB2_GPIO \
+	SAM_PINMUX(b, 2, gpio, gpio)
+
+/* pb2a_eic_extint2 */
+#define PB2A_EIC_EXTINT2 \
+	SAM_PINMUX(b, 2, a, periph)
+
+/* pb2b_ptc_y8 */
+#define PB2B_PTC_Y8 \
+	SAM_PINMUX(b, 2, b, periph)
+
+/* pb2d_sercom5_pad0 */
+#define PB2D_SERCOM5_PAD0 \
+	SAM_PINMUX(b, 2, d, periph)
+
+/* pb2e_tc6_wo0 */
+#define PB2E_TC6_WO0 \
+	SAM_PINMUX(b, 2, e, periph)
+
+/* pb3_gpio */
+#define PB3_GPIO \
+	SAM_PINMUX(b, 3, gpio, gpio)
+
+/* pb3a_eic_extint3 */
+#define PB3A_EIC_EXTINT3 \
+	SAM_PINMUX(b, 3, a, periph)
+
+/* pb3b_ptc_y9 */
+#define PB3B_PTC_Y9 \
+	SAM_PINMUX(b, 3, b, periph)
+
+/* pb3d_sercom5_pad1 */
+#define PB3D_SERCOM5_PAD1 \
+	SAM_PINMUX(b, 3, d, periph)
+
+/* pb3e_tc6_wo1 */
+#define PB3E_TC6_WO1 \
+	SAM_PINMUX(b, 3, e, periph)
+
+/* pb4_gpio */
+#define PB4_GPIO \
+	SAM_PINMUX(b, 4, gpio, gpio)
+
+/* pb4a_eic_extint4 */
+#define PB4A_EIC_EXTINT4 \
+	SAM_PINMUX(b, 4, a, periph)
+
+/* pb4b_adc0_ain6 */
+#define PB4B_ADC0_AIN6 \
+	SAM_PINMUX(b, 4, b, periph)
+
+/* pb4b_ptc_y10 */
+#define PB4B_PTC_Y10 \
+	SAM_PINMUX(b, 4, b, periph)
+
+/* pb5_gpio */
+#define PB5_GPIO \
+	SAM_PINMUX(b, 5, gpio, gpio)
+
+/* pb5a_eic_extint5 */
+#define PB5A_EIC_EXTINT5 \
+	SAM_PINMUX(b, 5, a, periph)
+
+/* pb5b_adc0_ain7 */
+#define PB5B_ADC0_AIN7 \
+	SAM_PINMUX(b, 5, b, periph)
+
+/* pb5b_ac_ain6 */
+#define PB5B_AC_AIN6 \
+	SAM_PINMUX(b, 5, b, periph)
+
+/* pb5b_ptc_y11 */
+#define PB5B_PTC_Y11 \
+	SAM_PINMUX(b, 5, b, periph)
+
+/* pb6_gpio */
+#define PB6_GPIO \
+	SAM_PINMUX(b, 6, gpio, gpio)
+
+/* pb6a_eic_extint6 */
+#define PB6A_EIC_EXTINT6 \
+	SAM_PINMUX(b, 6, a, periph)
+
+/* pb6b_adc0_ain8 */
+#define PB6B_ADC0_AIN8 \
+	SAM_PINMUX(b, 6, b, periph)
+
+/* pb6b_ac_ain7 */
+#define PB6B_AC_AIN7 \
+	SAM_PINMUX(b, 6, b, periph)
+
+/* pb6b_ptc_y12 */
+#define PB6B_PTC_Y12 \
+	SAM_PINMUX(b, 6, b, periph)
+
+/* pb6c_sercom7_pad1 */
+#define PB6C_SERCOM7_PAD1 \
+	SAM_PINMUX(b, 6, c, periph)
+
+/* pb7_gpio */
+#define PB7_GPIO \
+	SAM_PINMUX(b, 7, gpio, gpio)
+
+/* pb7a_eic_extint7 */
+#define PB7A_EIC_EXTINT7 \
+	SAM_PINMUX(b, 7, a, periph)
+
+/* pb7b_adc0_ain9 */
+#define PB7B_ADC0_AIN9 \
+	SAM_PINMUX(b, 7, b, periph)
+
+/* pb7b_ptc_y13 */
+#define PB7B_PTC_Y13 \
+	SAM_PINMUX(b, 7, b, periph)
+
+/* pb7c_sercom7_pad3 */
+#define PB7C_SERCOM7_PAD3 \
+	SAM_PINMUX(b, 7, c, periph)
+
+/* pb7d_sercom7_pad2 */
+#define PB7D_SERCOM7_PAD2 \
+	SAM_PINMUX(b, 7, d, periph)
+
+/* pb8_gpio */
+#define PB8_GPIO \
+	SAM_PINMUX(b, 8, gpio, gpio)
+
+/* pb8a_eic_extint8 */
+#define PB8A_EIC_EXTINT8 \
+	SAM_PINMUX(b, 8, a, periph)
+
+/* pb8b_adc0_ain2 */
+#define PB8B_ADC0_AIN2 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8b_ptc_y14 */
+#define PB8B_PTC_Y14 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8c_sercom7_pad2 */
+#define PB8C_SERCOM7_PAD2 \
+	SAM_PINMUX(b, 8, c, periph)
+
+/* pb8d_sercom7_pad3 */
+#define PB8D_SERCOM7_PAD3 \
+	SAM_PINMUX(b, 8, d, periph)
+
+/* pb8e_tc4_wo0 */
+#define PB8E_TC4_WO0 \
+	SAM_PINMUX(b, 8, e, periph)
+
+/* pb9_gpio */
+#define PB9_GPIO \
+	SAM_PINMUX(b, 9, gpio, gpio)
+
+/* pb9a_eic_extint9 */
+#define PB9A_EIC_EXTINT9 \
+	SAM_PINMUX(b, 9, a, periph)
+
+/* pb9b_adc0_ain3 */
+#define PB9B_ADC0_AIN3 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9b_ptc_y15 */
+#define PB9B_PTC_Y15 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9d_sercom4_pad1 */
+#define PB9D_SERCOM4_PAD1 \
+	SAM_PINMUX(b, 9, d, periph)
+
+/* pb9e_tc4_wo1 */
+#define PB9E_TC4_WO1 \
+	SAM_PINMUX(b, 9, e, periph)
+
+/* pb10_gpio */
+#define PB10_GPIO \
+	SAM_PINMUX(b, 10, gpio, gpio)
+
+/* pb10a_eic_extint10 */
+#define PB10A_EIC_EXTINT10 \
+	SAM_PINMUX(b, 10, a, periph)
+
+/* pb10d_sercom4_pad2 */
+#define PB10D_SERCOM4_PAD2 \
+	SAM_PINMUX(b, 10, d, periph)
+
+/* pb10e_tc5_wo0 */
+#define PB10E_TC5_WO0 \
+	SAM_PINMUX(b, 10, e, periph)
+
+/* pb10f_tcc0_wo4 */
+#define PB10F_TCC0_WO4 \
+	SAM_PINMUX(b, 10, f, periph)
+
+/* pb10h_gclk_io4 */
+#define PB10H_GCLK_IO4 \
+	SAM_PINMUX(b, 10, h, periph)
+
+/* pb11_gpio */
+#define PB11_GPIO \
+	SAM_PINMUX(b, 11, gpio, gpio)
+
+/* pb11a_eic_extint11 */
+#define PB11A_EIC_EXTINT11 \
+	SAM_PINMUX(b, 11, a, periph)
+
+/* pb11d_sercom4_pad3 */
+#define PB11D_SERCOM4_PAD3 \
+	SAM_PINMUX(b, 11, d, periph)
+
+/* pb11e_tc5_wo1 */
+#define PB11E_TC5_WO1 \
+	SAM_PINMUX(b, 11, e, periph)
+
+/* pb11f_tcc0_wo5 */
+#define PB11F_TCC0_WO5 \
+	SAM_PINMUX(b, 11, f, periph)
+
+/* pb11h_gclk_io5 */
+#define PB11H_GCLK_IO5 \
+	SAM_PINMUX(b, 11, h, periph)
+
+/* pb12_gpio */
+#define PB12_GPIO \
+	SAM_PINMUX(b, 12, gpio, gpio)
+
+/* pb12a_eic_extint12 */
+#define PB12A_EIC_EXTINT12 \
+	SAM_PINMUX(b, 12, a, periph)
+
+/* pb12b_ptc_x12 */
+#define PB12B_PTC_X12 \
+	SAM_PINMUX(b, 12, b, periph)
+
+/* pb12c_sercom4_pad0 */
+#define PB12C_SERCOM4_PAD0 \
+	SAM_PINMUX(b, 12, c, periph)
+
+/* pb12e_tc4_wo0 */
+#define PB12E_TC4_WO0 \
+	SAM_PINMUX(b, 12, e, periph)
+
+/* pb12f_tcc0_wo6 */
+#define PB12F_TCC0_WO6 \
+	SAM_PINMUX(b, 12, f, periph)
+
+/* pb12h_gclk_io6 */
+#define PB12H_GCLK_IO6 \
+	SAM_PINMUX(b, 12, h, periph)
+
+/* pb13_gpio */
+#define PB13_GPIO \
+	SAM_PINMUX(b, 13, gpio, gpio)
+
+/* pb13a_eic_extint13 */
+#define PB13A_EIC_EXTINT13 \
+	SAM_PINMUX(b, 13, a, periph)
+
+/* pb13b_ptc_x13 */
+#define PB13B_PTC_X13 \
+	SAM_PINMUX(b, 13, b, periph)
+
+/* pb13c_sercom4_pad1 */
+#define PB13C_SERCOM4_PAD1 \
+	SAM_PINMUX(b, 13, c, periph)
+
+/* pb13e_tc4_wo1 */
+#define PB13E_TC4_WO1 \
+	SAM_PINMUX(b, 13, e, periph)
+
+/* pb13f_tcc0_wo7 */
+#define PB13F_TCC0_WO7 \
+	SAM_PINMUX(b, 13, f, periph)
+
+/* pb13h_gclk_io7 */
+#define PB13H_GCLK_IO7 \
+	SAM_PINMUX(b, 13, h, periph)
+
+/* pb14_gpio */
+#define PB14_GPIO \
+	SAM_PINMUX(b, 14, gpio, gpio)
+
+/* pb14a_eic_extint14 */
+#define PB14A_EIC_EXTINT14 \
+	SAM_PINMUX(b, 14, a, periph)
+
+/* pb14b_ptc_x14 */
+#define PB14B_PTC_X14 \
+	SAM_PINMUX(b, 14, b, periph)
+
+/* pb14c_sercom4_pad2 */
+#define PB14C_SERCOM4_PAD2 \
+	SAM_PINMUX(b, 14, c, periph)
+
+/* pb14e_tc5_wo0 */
+#define PB14E_TC5_WO0 \
+	SAM_PINMUX(b, 14, e, periph)
+
+/* pb14h_gclk_io0 */
+#define PB14H_GCLK_IO0 \
+	SAM_PINMUX(b, 14, h, periph)
+
+/* pb15_gpio */
+#define PB15_GPIO \
+	SAM_PINMUX(b, 15, gpio, gpio)
+
+/* pb15a_eic_extint15 */
+#define PB15A_EIC_EXTINT15 \
+	SAM_PINMUX(b, 15, a, periph)
+
+/* pb15b_ptc_x15 */
+#define PB15B_PTC_X15 \
+	SAM_PINMUX(b, 15, b, periph)
+
+/* pb15c_sercom4_pad3 */
+#define PB15C_SERCOM4_PAD3 \
+	SAM_PINMUX(b, 15, c, periph)
+
+/* pb15e_tc5_wo1 */
+#define PB15E_TC5_WO1 \
+	SAM_PINMUX(b, 15, e, periph)
+
+/* pb15h_gclk_io1 */
+#define PB15H_GCLK_IO1 \
+	SAM_PINMUX(b, 15, h, periph)
+
+/* pb16_gpio */
+#define PB16_GPIO \
+	SAM_PINMUX(b, 16, gpio, gpio)
+
+/* pb16a_eic_extint0 */
+#define PB16A_EIC_EXTINT0 \
+	SAM_PINMUX(b, 16, a, periph)
+
+/* pb16c_sercom5_pad0 */
+#define PB16C_SERCOM5_PAD0 \
+	SAM_PINMUX(b, 16, c, periph)
+
+/* pb16e_tc6_wo0 */
+#define PB16E_TC6_WO0 \
+	SAM_PINMUX(b, 16, e, periph)
+
+/* pb16h_gclk_io2 */
+#define PB16H_GCLK_IO2 \
+	SAM_PINMUX(b, 16, h, periph)
+
+/* pb17_gpio */
+#define PB17_GPIO \
+	SAM_PINMUX(b, 17, gpio, gpio)
+
+/* pb17a_eic_extint1 */
+#define PB17A_EIC_EXTINT1 \
+	SAM_PINMUX(b, 17, a, periph)
+
+/* pb17c_sercom5_pad1 */
+#define PB17C_SERCOM5_PAD1 \
+	SAM_PINMUX(b, 17, c, periph)
+
+/* pb17e_tc6_wo1 */
+#define PB17E_TC6_WO1 \
+	SAM_PINMUX(b, 17, e, periph)
+
+/* pb17h_gclk_io3 */
+#define PB17H_GCLK_IO3 \
+	SAM_PINMUX(b, 17, h, periph)
+
+/* pb18_gpio */
+#define PB18_GPIO \
+	SAM_PINMUX(b, 18, gpio, gpio)
+
+/* pb18a_eic_extint2 */
+#define PB18A_EIC_EXTINT2 \
+	SAM_PINMUX(b, 18, a, periph)
+
+/* pb18c_sercom5_pad2 */
+#define PB18C_SERCOM5_PAD2 \
+	SAM_PINMUX(b, 18, c, periph)
+
+/* pb18d_sercom3_pad2 */
+#define PB18D_SERCOM3_PAD2 \
+	SAM_PINMUX(b, 18, d, periph)
+
+/* pb18h_gclk_io4 */
+#define PB18H_GCLK_IO4 \
+	SAM_PINMUX(b, 18, h, periph)
+
+/* pb19_gpio */
+#define PB19_GPIO \
+	SAM_PINMUX(b, 19, gpio, gpio)
+
+/* pb19a_eic_extint3 */
+#define PB19A_EIC_EXTINT3 \
+	SAM_PINMUX(b, 19, a, periph)
+
+/* pb19c_sercom5_pad3 */
+#define PB19C_SERCOM5_PAD3 \
+	SAM_PINMUX(b, 19, c, periph)
+
+/* pb19d_sercom3_pad3 */
+#define PB19D_SERCOM3_PAD3 \
+	SAM_PINMUX(b, 19, d, periph)
+
+/* pb19h_gclk_io5 */
+#define PB19H_GCLK_IO5 \
+	SAM_PINMUX(b, 19, h, periph)
+
+/* pb20_gpio */
+#define PB20_GPIO \
+	SAM_PINMUX(b, 20, gpio, gpio)
+
+/* pb20a_eic_extint4 */
+#define PB20A_EIC_EXTINT4 \
+	SAM_PINMUX(b, 20, a, periph)
+
+/* pb20c_sercom3_pad0 */
+#define PB20C_SERCOM3_PAD0 \
+	SAM_PINMUX(b, 20, c, periph)
+
+/* pb20d_sercom2_pad0 */
+#define PB20D_SERCOM2_PAD0 \
+	SAM_PINMUX(b, 20, d, periph)
+
+/* pb20h_gclk_io6 */
+#define PB20H_GCLK_IO6 \
+	SAM_PINMUX(b, 20, h, periph)
+
+/* pb21_gpio */
+#define PB21_GPIO \
+	SAM_PINMUX(b, 21, gpio, gpio)
+
+/* pb21a_eic_extint5 */
+#define PB21A_EIC_EXTINT5 \
+	SAM_PINMUX(b, 21, a, periph)
+
+/* pb21c_sercom3_pad1 */
+#define PB21C_SERCOM3_PAD1 \
+	SAM_PINMUX(b, 21, c, periph)
+
+/* pb21d_sercom2_pad2 */
+#define PB21D_SERCOM2_PAD2 \
+	SAM_PINMUX(b, 21, d, periph)
+
+/* pb21h_gclk_io7 */
+#define PB21H_GCLK_IO7 \
+	SAM_PINMUX(b, 21, h, periph)
+
+/* pb22_gpio */
+#define PB22_GPIO \
+	SAM_PINMUX(b, 22, gpio, gpio)
+
+/* pb22a_eic_extint6 */
+#define PB22A_EIC_EXTINT6 \
+	SAM_PINMUX(b, 22, a, periph)
+
+/* pb22c_sercom0_pad2 */
+#define PB22C_SERCOM0_PAD2 \
+	SAM_PINMUX(b, 22, c, periph)
+
+/* pb22d_sercom5_pad2 */
+#define PB22D_SERCOM5_PAD2 \
+	SAM_PINMUX(b, 22, d, periph)
+
+/* pb22e_tc7_wo0 */
+#define PB22E_TC7_WO0 \
+	SAM_PINMUX(b, 22, e, periph)
+
+/* pb22f_tcc1_wo2 */
+#define PB22F_TCC1_WO2 \
+	SAM_PINMUX(b, 22, f, periph)
+
+/* pb22h_gclk_io0 */
+#define PB22H_GCLK_IO0 \
+	SAM_PINMUX(b, 22, h, periph)
+
+/* pb23_gpio */
+#define PB23_GPIO \
+	SAM_PINMUX(b, 23, gpio, gpio)
+
+/* pb23a_eic_extint7 */
+#define PB23A_EIC_EXTINT7 \
+	SAM_PINMUX(b, 23, a, periph)
+
+/* pb23c_sercom0_pad3 */
+#define PB23C_SERCOM0_PAD3 \
+	SAM_PINMUX(b, 23, c, periph)
+
+/* pb23d_sercom5_pad3 */
+#define PB23D_SERCOM5_PAD3 \
+	SAM_PINMUX(b, 23, d, periph)
+
+/* pb23e_tc7_wo1 */
+#define PB23E_TC7_WO1 \
+	SAM_PINMUX(b, 23, e, periph)
+
+/* pb23f_tcc1_wo3 */
+#define PB23F_TCC1_WO3 \
+	SAM_PINMUX(b, 23, f, periph)
+
+/* pb23h_gclk_io1 */
+#define PB23H_GCLK_IO1 \
+	SAM_PINMUX(b, 23, h, periph)
+
+/* pb24_gpio */
+#define PB24_GPIO \
+	SAM_PINMUX(b, 24, gpio, gpio)
+
+/* pb24a_eic_extint7 */
+#define PB24A_EIC_EXTINT7 \
+	SAM_PINMUX(b, 24, a, periph)
+
+/* pb24c_sercom0_pad0 */
+#define PB24C_SERCOM0_PAD0 \
+	SAM_PINMUX(b, 24, c, periph)
+
+/* pb24d_sercom4_pad0 */
+#define PB24D_SERCOM4_PAD0 \
+	SAM_PINMUX(b, 24, d, periph)
+
+/* pb24h_ac_cmp0 */
+#define PB24H_AC_CMP0 \
+	SAM_PINMUX(b, 24, h, periph)
+
+/* pb25_gpio */
+#define PB25_GPIO \
+	SAM_PINMUX(b, 25, gpio, gpio)
+
+/* pb25a_eic_extint8 */
+#define PB25A_EIC_EXTINT8 \
+	SAM_PINMUX(b, 25, a, periph)
+
+/* pb25c_sercom0_pad1 */
+#define PB25C_SERCOM0_PAD1 \
+	SAM_PINMUX(b, 25, c, periph)
+
+/* pb25d_sercom4_pad1 */
+#define PB25D_SERCOM4_PAD1 \
+	SAM_PINMUX(b, 25, d, periph)
+
+/* pb25h_ac_cmp1 */
+#define PB25H_AC_CMP1 \
+	SAM_PINMUX(b, 25, h, periph)
+
+/* pb30_gpio */
+#define PB30_GPIO \
+	SAM_PINMUX(b, 30, gpio, gpio)
+
+/* pb30a_eic_extint14 */
+#define PB30A_EIC_EXTINT14 \
+	SAM_PINMUX(b, 30, a, periph)
+
+/* pb30d_sercom5_pad0 */
+#define PB30D_SERCOM5_PAD0 \
+	SAM_PINMUX(b, 30, d, periph)
+
+/* pb30e_tc0_wo0 */
+#define PB30E_TC0_WO0 \
+	SAM_PINMUX(b, 30, e, periph)
+
+/* pb30h_ac_cmp2 */
+#define PB30H_AC_CMP2 \
+	SAM_PINMUX(b, 30, h, periph)
+
+/* pb31_gpio */
+#define PB31_GPIO \
+	SAM_PINMUX(b, 31, gpio, gpio)
+
+/* pb31a_eic_extint15 */
+#define PB31A_EIC_EXTINT15 \
+	SAM_PINMUX(b, 31, a, periph)
+
+/* pb31d_sercom5_pad1 */
+#define PB31D_SERCOM5_PAD1 \
+	SAM_PINMUX(b, 31, d, periph)
+
+/* pb31e_tc0_wo1 */
+#define PB31E_TC0_WO1 \
+	SAM_PINMUX(b, 31, e, periph)
+
+/* pb31h_ac_cmp3 */
+#define PB31H_AC_CMP3 \
+	SAM_PINMUX(b, 31, h, periph)
+
+/* pc0_gpio */
+#define PC0_GPIO \
+	SAM_PINMUX(c, 0, gpio, gpio)
+
+/* pc0a_eic_extint8 */
+#define PC0A_EIC_EXTINT8 \
+	SAM_PINMUX(c, 0, a, periph)
+
+/* pc0b_adc0_ain8 */
+#define PC0B_ADC0_AIN8 \
+	SAM_PINMUX(c, 0, b, periph)
+
+/* pc1_gpio */
+#define PC1_GPIO \
+	SAM_PINMUX(c, 1, gpio, gpio)
+
+/* pc1a_eic_extint9 */
+#define PC1A_EIC_EXTINT9 \
+	SAM_PINMUX(c, 1, a, periph)
+
+/* pc1b_adc0_ain9 */
+#define PC1B_ADC0_AIN9 \
+	SAM_PINMUX(c, 1, b, periph)
+
+/* pc2_gpio */
+#define PC2_GPIO \
+	SAM_PINMUX(c, 2, gpio, gpio)
+
+/* pc2a_eic_extint10 */
+#define PC2A_EIC_EXTINT10 \
+	SAM_PINMUX(c, 2, a, periph)
+
+/* pc2b_adc0_ain10 */
+#define PC2B_ADC0_AIN10 \
+	SAM_PINMUX(c, 2, b, periph)
+
+/* pc3_gpio */
+#define PC3_GPIO \
+	SAM_PINMUX(c, 3, gpio, gpio)
+
+/* pc3a_eic_extint11 */
+#define PC3A_EIC_EXTINT11 \
+	SAM_PINMUX(c, 3, a, periph)
+
+/* pc3b_adc0_ain11 */
+#define PC3B_ADC0_AIN11 \
+	SAM_PINMUX(c, 3, b, periph)
+
+/* pc3c_sercom7_pad0 */
+#define PC3C_SERCOM7_PAD0 \
+	SAM_PINMUX(c, 3, c, periph)
+
+/* pc3f_tcc2_wo0 */
+#define PC3F_TCC2_WO0 \
+	SAM_PINMUX(c, 3, f, periph)
+
+/* pc5_gpio */
+#define PC5_GPIO \
+	SAM_PINMUX(c, 5, gpio, gpio)
+
+/* pc5a_eic_extint13 */
+#define PC5A_EIC_EXTINT13 \
+	SAM_PINMUX(c, 5, a, periph)
+
+/* pc5c_sercom6_pad3 */
+#define PC5C_SERCOM6_PAD3 \
+	SAM_PINMUX(c, 5, c, periph)
+
+/* pc5f_tcc2_wo1 */
+#define PC5F_TCC2_WO1 \
+	SAM_PINMUX(c, 5, f, periph)
+
+/* pc6_gpio */
+#define PC6_GPIO \
+	SAM_PINMUX(c, 6, gpio, gpio)
+
+/* pc6a_eic_extint14 */
+#define PC6A_EIC_EXTINT14 \
+	SAM_PINMUX(c, 6, a, periph)
+
+/* pc6c_sercom6_pad0 */
+#define PC6C_SERCOM6_PAD0 \
+	SAM_PINMUX(c, 6, c, periph)
+
+/* pc7_gpio */
+#define PC7_GPIO \
+	SAM_PINMUX(c, 7, gpio, gpio)
+
+/* pc7a_eic_extint15 */
+#define PC7A_EIC_EXTINT15 \
+	SAM_PINMUX(c, 7, a, periph)
+
+/* pc7c_sercom6_pad1 */
+#define PC7C_SERCOM6_PAD1 \
+	SAM_PINMUX(c, 7, c, periph)
+
+/* pc8_gpio */
+#define PC8_GPIO \
+	SAM_PINMUX(c, 8, gpio, gpio)
+
+/* pc8a_eic_extint0 */
+#define PC8A_EIC_EXTINT0 \
+	SAM_PINMUX(c, 8, a, periph)
+
+/* pc8c_sercom6_pad0 */
+#define PC8C_SERCOM6_PAD0 \
+	SAM_PINMUX(c, 8, c, periph)
+
+/* pc8d_sercom7_pad0 */
+#define PC8D_SERCOM7_PAD0 \
+	SAM_PINMUX(c, 8, d, periph)
+
+/* pc9_gpio */
+#define PC9_GPIO \
+	SAM_PINMUX(c, 9, gpio, gpio)
+
+/* pc9a_eic_extint1 */
+#define PC9A_EIC_EXTINT1 \
+	SAM_PINMUX(c, 9, a, periph)
+
+/* pc9c_sercom6_pad1 */
+#define PC9C_SERCOM6_PAD1 \
+	SAM_PINMUX(c, 9, c, periph)
+
+/* pc9d_sercom7_pad1 */
+#define PC9D_SERCOM7_PAD1 \
+	SAM_PINMUX(c, 9, d, periph)
+
+/* pc10_gpio */
+#define PC10_GPIO \
+	SAM_PINMUX(c, 10, gpio, gpio)
+
+/* pc10a_eic_extint2 */
+#define PC10A_EIC_EXTINT2 \
+	SAM_PINMUX(c, 10, a, periph)
+
+/* pc10c_sercom6_pad2 */
+#define PC10C_SERCOM6_PAD2 \
+	SAM_PINMUX(c, 10, c, periph)
+
+/* pc10d_sercom7_pad2 */
+#define PC10D_SERCOM7_PAD2 \
+	SAM_PINMUX(c, 10, d, periph)
+
+/* pc11_gpio */
+#define PC11_GPIO \
+	SAM_PINMUX(c, 11, gpio, gpio)
+
+/* pc11a_eic_extint3 */
+#define PC11A_EIC_EXTINT3 \
+	SAM_PINMUX(c, 11, a, periph)
+
+/* pc11c_sercom6_pad3 */
+#define PC11C_SERCOM6_PAD3 \
+	SAM_PINMUX(c, 11, c, periph)
+
+/* pc11d_sercom7_pad3 */
+#define PC11D_SERCOM7_PAD3 \
+	SAM_PINMUX(c, 11, d, periph)
+
+/* pc12_gpio */
+#define PC12_GPIO \
+	SAM_PINMUX(c, 12, gpio, gpio)
+
+/* pc12a_eic_extint4 */
+#define PC12A_EIC_EXTINT4 \
+	SAM_PINMUX(c, 12, a, periph)
+
+/* pc12c_sercom7_pad0 */
+#define PC12C_SERCOM7_PAD0 \
+	SAM_PINMUX(c, 12, c, periph)
+
+/* pc13_gpio */
+#define PC13_GPIO \
+	SAM_PINMUX(c, 13, gpio, gpio)
+
+/* pc13a_eic_extint5 */
+#define PC13A_EIC_EXTINT5 \
+	SAM_PINMUX(c, 13, a, periph)
+
+/* pc13c_sercom7_pad1 */
+#define PC13C_SERCOM7_PAD1 \
+	SAM_PINMUX(c, 13, c, periph)
+
+/* pc14_gpio */
+#define PC14_GPIO \
+	SAM_PINMUX(c, 14, gpio, gpio)
+
+/* pc14a_eic_extint6 */
+#define PC14A_EIC_EXTINT6 \
+	SAM_PINMUX(c, 14, a, periph)
+
+/* pc14c_sercom7_pad2 */
+#define PC14C_SERCOM7_PAD2 \
+	SAM_PINMUX(c, 14, c, periph)
+
+/* pc15_gpio */
+#define PC15_GPIO \
+	SAM_PINMUX(c, 15, gpio, gpio)
+
+/* pc15a_eic_extint7 */
+#define PC15A_EIC_EXTINT7 \
+	SAM_PINMUX(c, 15, a, periph)
+
+/* pc15c_sercom7_pad3 */
+#define PC15C_SERCOM7_PAD3 \
+	SAM_PINMUX(c, 15, c, periph)
+
+/* pc16_gpio */
+#define PC16_GPIO \
+	SAM_PINMUX(c, 16, gpio, gpio)
+
+/* pc16a_eic_extint8 */
+#define PC16A_EIC_EXTINT8 \
+	SAM_PINMUX(c, 16, a, periph)
+
+/* pc16c_sercom6_pad0 */
+#define PC16C_SERCOM6_PAD0 \
+	SAM_PINMUX(c, 16, c, periph)
+
+/* pc17_gpio */
+#define PC17_GPIO \
+	SAM_PINMUX(c, 17, gpio, gpio)
+
+/* pc17a_eic_extint9 */
+#define PC17A_EIC_EXTINT9 \
+	SAM_PINMUX(c, 17, a, periph)
+
+/* pc17c_sercom6_pad1 */
+#define PC17C_SERCOM6_PAD1 \
+	SAM_PINMUX(c, 17, c, periph)
+
+/* pc18_gpio */
+#define PC18_GPIO \
+	SAM_PINMUX(c, 18, gpio, gpio)
+
+/* pc18a_eic_extint10 */
+#define PC18A_EIC_EXTINT10 \
+	SAM_PINMUX(c, 18, a, periph)
+
+/* pc18c_sercom6_pad2 */
+#define PC18C_SERCOM6_PAD2 \
+	SAM_PINMUX(c, 18, c, periph)
+
+/* pc19_gpio */
+#define PC19_GPIO \
+	SAM_PINMUX(c, 19, gpio, gpio)
+
+/* pc19a_eic_extint11 */
+#define PC19A_EIC_EXTINT11 \
+	SAM_PINMUX(c, 19, a, periph)
+
+/* pc19c_sercom6_pad3 */
+#define PC19C_SERCOM6_PAD3 \
+	SAM_PINMUX(c, 19, c, periph)
+
+/* pc20_gpio */
+#define PC20_GPIO \
+	SAM_PINMUX(c, 20, gpio, gpio)
+
+/* pc20a_eic_extint12 */
+#define PC20A_EIC_EXTINT12 \
+	SAM_PINMUX(c, 20, a, periph)
+
+/* pc21_gpio */
+#define PC21_GPIO \
+	SAM_PINMUX(c, 21, gpio, gpio)
+
+/* pc21a_eic_extint13 */
+#define PC21A_EIC_EXTINT13 \
+	SAM_PINMUX(c, 21, a, periph)
+
+/* pc24_gpio */
+#define PC24_GPIO \
+	SAM_PINMUX(c, 24, gpio, gpio)
+
+/* pc24a_eic_extint0 */
+#define PC24A_EIC_EXTINT0 \
+	SAM_PINMUX(c, 24, a, periph)
+
+/* pc24c_sercom0_pad2 */
+#define PC24C_SERCOM0_PAD2 \
+	SAM_PINMUX(c, 24, c, periph)
+
+/* pc24d_sercom4_pad2 */
+#define PC24D_SERCOM4_PAD2 \
+	SAM_PINMUX(c, 24, d, periph)
+
+/* pc25_gpio */
+#define PC25_GPIO \
+	SAM_PINMUX(c, 25, gpio, gpio)
+
+/* pc25a_eic_extint1 */
+#define PC25A_EIC_EXTINT1 \
+	SAM_PINMUX(c, 25, a, periph)
+
+/* pc25c_sercom0_pad3 */
+#define PC25C_SERCOM0_PAD3 \
+	SAM_PINMUX(c, 25, c, periph)
+
+/* pc25d_sercom4_pad3 */
+#define PC25D_SERCOM4_PAD3 \
+	SAM_PINMUX(c, 25, d, periph)
+
+/* pc26_gpio */
+#define PC26_GPIO \
+	SAM_PINMUX(c, 26, gpio, gpio)
+
+/* pc26a_eic_extint2 */
+#define PC26A_EIC_EXTINT2 \
+	SAM_PINMUX(c, 26, a, periph)
+
+/* pc27_gpio */
+#define PC27_GPIO \
+	SAM_PINMUX(c, 27, gpio, gpio)
+
+/* pc27a_eic_extint3 */
+#define PC27A_EIC_EXTINT3 \
+	SAM_PINMUX(c, 27, a, periph)
+
+/* pc27d_sercom1_pad0 */
+#define PC27D_SERCOM1_PAD0 \
+	SAM_PINMUX(c, 27, d, periph)
+
+/* pc28_gpio */
+#define PC28_GPIO \
+	SAM_PINMUX(c, 28, gpio, gpio)
+
+/* pc28a_eic_extint4 */
+#define PC28A_EIC_EXTINT4 \
+	SAM_PINMUX(c, 28, a, periph)
+
+/* pc28d_sercom1_pad1 */
+#define PC28D_SERCOM1_PAD1 \
+	SAM_PINMUX(c, 28, d, periph)
diff --git a/include/dt-bindings/pinctrl/samc21e-pinctrl.h b/include/dt-bindings/pinctrl/samc21e-pinctrl.h
new file mode 100644
index 0000000..aba58af
--- /dev/null
+++ b/include/dt-bindings/pinctrl/samc21e-pinctrl.h
@@ -0,0 +1,743 @@
+/*
+ * Autogenerated file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/atmel_sam_pinctrl.h>
+
+/* pa0_gpio */
+#define PA0_GPIO \
+	SAM_PINMUX(a, 0, gpio, gpio)
+
+/* pa0a_eic_extint0 */
+#define PA0A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 0, a, periph)
+
+/* pa0d_sercom1_pad0 */
+#define PA0D_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 0, d, periph)
+
+/* pa0e_tc2_wo0 */
+#define PA0E_TC2_WO0 \
+	SAM_PINMUX(a, 0, e, periph)
+
+/* pa0h_ac_cmp2 */
+#define PA0H_AC_CMP2 \
+	SAM_PINMUX(a, 0, h, periph)
+
+/* pa1_gpio */
+#define PA1_GPIO \
+	SAM_PINMUX(a, 1, gpio, gpio)
+
+/* pa1a_eic_extint1 */
+#define PA1A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 1, a, periph)
+
+/* pa1d_sercom1_pad1 */
+#define PA1D_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 1, d, periph)
+
+/* pa1e_tc2_wo1 */
+#define PA1E_TC2_WO1 \
+	SAM_PINMUX(a, 1, e, periph)
+
+/* pa1h_ac_cmp3 */
+#define PA1H_AC_CMP3 \
+	SAM_PINMUX(a, 1, h, periph)
+
+/* pa2_gpio */
+#define PA2_GPIO \
+	SAM_PINMUX(a, 2, gpio, gpio)
+
+/* pa2a_eic_extint2 */
+#define PA2A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 2, a, periph)
+
+/* pa2b_adc0_ain0 */
+#define PA2B_ADC0_AIN0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ac_ain4 */
+#define PA2B_AC_AIN4 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ptc_y0 */
+#define PA2B_PTC_Y0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_dac_vout */
+#define PA2B_DAC_VOUT \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa3_gpio */
+#define PA3_GPIO \
+	SAM_PINMUX(a, 3, gpio, gpio)
+
+/* pa3a_eic_extint3 */
+#define PA3A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 3, a, periph)
+
+/* pa3b_anaref_vrefa */
+#define PA3B_ANAREF_VREFA \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_adc0_ain5 */
+#define PA3B_ADC0_AIN5 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ac_ain4 */
+#define PA3B_AC_AIN4 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ptc_y1 */
+#define PA3B_PTC_Y1 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa4_gpio */
+#define PA4_GPIO \
+	SAM_PINMUX(a, 4, gpio, gpio)
+
+/* pa4a_eic_extint4 */
+#define PA4A_EIC_EXTINT4 \
+	SAM_PINMUX(a, 4, a, periph)
+
+/* pa4b_anaref_vrefb */
+#define PA4B_ANAREF_VREFB \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_adc0_ain4 */
+#define PA4B_ADC0_AIN4 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ac_ain0 */
+#define PA4B_AC_AIN0 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ptc_y2 */
+#define PA4B_PTC_Y2 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4d_sercom0_pad0 */
+#define PA4D_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 4, d, periph)
+
+/* pa4e_tcc0_wo0 */
+#define PA4E_TCC0_WO0 \
+	SAM_PINMUX(a, 4, e, periph)
+
+/* pa5_gpio */
+#define PA5_GPIO \
+	SAM_PINMUX(a, 5, gpio, gpio)
+
+/* pa5a_eic_extint5 */
+#define PA5A_EIC_EXTINT5 \
+	SAM_PINMUX(a, 5, a, periph)
+
+/* pa5b_adc0_ain5 */
+#define PA5B_ADC0_AIN5 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ac_ain1 */
+#define PA5B_AC_AIN1 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ptc_y3 */
+#define PA5B_PTC_Y3 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5d_sercom0_pad1 */
+#define PA5D_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 5, d, periph)
+
+/* pa5e_tcc0_wo1 */
+#define PA5E_TCC0_WO1 \
+	SAM_PINMUX(a, 5, e, periph)
+
+/* pa6_gpio */
+#define PA6_GPIO \
+	SAM_PINMUX(a, 6, gpio, gpio)
+
+/* pa6a_eic_extint6 */
+#define PA6A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 6, a, periph)
+
+/* pa6b_adc0_ain6 */
+#define PA6B_ADC0_AIN6 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ac_ain2 */
+#define PA6B_AC_AIN2 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ptc_y4 */
+#define PA6B_PTC_Y4 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_sdadc0_ainn0 */
+#define PA6B_SDADC0_AINN0 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6d_sercom0_pad2 */
+#define PA6D_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 6, d, periph)
+
+/* pa6e_tcc1_wo0 */
+#define PA6E_TCC1_WO0 \
+	SAM_PINMUX(a, 6, e, periph)
+
+/* pa7_gpio */
+#define PA7_GPIO \
+	SAM_PINMUX(a, 7, gpio, gpio)
+
+/* pa7a_eic_extint7 */
+#define PA7A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 7, a, periph)
+
+/* pa7b_adc0_ain7 */
+#define PA7B_ADC0_AIN7 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ac_ain3 */
+#define PA7B_AC_AIN3 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ptc_y5 */
+#define PA7B_PTC_Y5 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_sdadc0_ainp0 */
+#define PA7B_SDADC0_AINP0 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7d_sercom0_pad3 */
+#define PA7D_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 7, d, periph)
+
+/* pa7e_tcc1_wo1 */
+#define PA7E_TCC1_WO1 \
+	SAM_PINMUX(a, 7, e, periph)
+
+/* pa8_gpio */
+#define PA8_GPIO \
+	SAM_PINMUX(a, 8, gpio, gpio)
+
+/* pa8a_eic_nmi */
+#define PA8A_EIC_NMI \
+	SAM_PINMUX(a, 8, a, periph)
+
+/* pa8b_adc0_ain8 */
+#define PA8B_ADC0_AIN8 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8b_adc1_ain10 */
+#define PA8B_ADC1_AIN10 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8b_ptc_xy16 */
+#define PA8B_PTC_XY16 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8c_sercom0_pad0 */
+#define PA8C_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 8, c, periph)
+
+/* pa8d_sercom2_pad0 */
+#define PA8D_SERCOM2_PAD0 \
+	SAM_PINMUX(a, 8, d, periph)
+
+/* pa8e_tcc0_wo0 */
+#define PA8E_TCC0_WO0 \
+	SAM_PINMUX(a, 8, e, periph)
+
+/* pa8f_tcc1_wo2 */
+#define PA8F_TCC1_WO2 \
+	SAM_PINMUX(a, 8, f, periph)
+
+/* pa9_gpio */
+#define PA9_GPIO \
+	SAM_PINMUX(a, 9, gpio, gpio)
+
+/* pa9a_eic_extint9 */
+#define PA9A_EIC_EXTINT9 \
+	SAM_PINMUX(a, 9, a, periph)
+
+/* pa9b_adc0_ain9 */
+#define PA9B_ADC0_AIN9 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9b_adc1_ain11 */
+#define PA9B_ADC1_AIN11 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9b_ptc_x1 */
+#define PA9B_PTC_X1 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9c_sercom0_pad1 */
+#define PA9C_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 9, c, periph)
+
+/* pa9d_sercom2_pad1 */
+#define PA9D_SERCOM2_PAD1 \
+	SAM_PINMUX(a, 9, d, periph)
+
+/* pa9e_tcc0_wo1 */
+#define PA9E_TCC0_WO1 \
+	SAM_PINMUX(a, 9, e, periph)
+
+/* pa9f_tcc1_wo3 */
+#define PA9F_TCC1_WO3 \
+	SAM_PINMUX(a, 9, f, periph)
+
+/* pa10_gpio */
+#define PA10_GPIO \
+	SAM_PINMUX(a, 10, gpio, gpio)
+
+/* pa10a_eic_extint10 */
+#define PA10A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 10, a, periph)
+
+/* pa10b_adc0_ain10 */
+#define PA10B_ADC0_AIN10 \
+	SAM_PINMUX(a, 10, b, periph)
+
+/* pa10b_ptc_x2 */
+#define PA10B_PTC_X2 \
+	SAM_PINMUX(a, 10, b, periph)
+
+/* pa10c_sercom0_pad2 */
+#define PA10C_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 10, c, periph)
+
+/* pa10d_sercom2_pad2 */
+#define PA10D_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 10, d, periph)
+
+/* pa10e_tcc1_wo0 */
+#define PA10E_TCC1_WO0 \
+	SAM_PINMUX(a, 10, e, periph)
+
+/* pa10f_tcc0_wo2 */
+#define PA10F_TCC0_WO2 \
+	SAM_PINMUX(a, 10, f, periph)
+
+/* pa10h_gclk_io4 */
+#define PA10H_GCLK_IO4 \
+	SAM_PINMUX(a, 10, h, periph)
+
+/* pa11_gpio */
+#define PA11_GPIO \
+	SAM_PINMUX(a, 11, gpio, gpio)
+
+/* pa11a_eic_extint11 */
+#define PA11A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 11, a, periph)
+
+/* pa11b_adc0_ain11 */
+#define PA11B_ADC0_AIN11 \
+	SAM_PINMUX(a, 11, b, periph)
+
+/* pa11b_ptc_x3 */
+#define PA11B_PTC_X3 \
+	SAM_PINMUX(a, 11, b, periph)
+
+/* pa11c_sercom0_pad3 */
+#define PA11C_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 11, c, periph)
+
+/* pa11d_sercom2_pad3 */
+#define PA11D_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 11, d, periph)
+
+/* pa11e_tcc1_wo1 */
+#define PA11E_TCC1_WO1 \
+	SAM_PINMUX(a, 11, e, periph)
+
+/* pa11f_tcc0_wo3 */
+#define PA11F_TCC0_WO3 \
+	SAM_PINMUX(a, 11, f, periph)
+
+/* pa11h_gclk_io5 */
+#define PA11H_GCLK_IO5 \
+	SAM_PINMUX(a, 11, h, periph)
+
+/* pa14_gpio */
+#define PA14_GPIO \
+	SAM_PINMUX(a, 14, gpio, gpio)
+
+/* pa14a_eic_extint14 */
+#define PA14A_EIC_EXTINT14 \
+	SAM_PINMUX(a, 14, a, periph)
+
+/* pa14c_sercom2_pad2 */
+#define PA14C_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 14, c, periph)
+
+/* pa14d_sercom4_pad2 */
+#define PA14D_SERCOM4_PAD2 \
+	SAM_PINMUX(a, 14, d, periph)
+
+/* pa14e_tc4_wo0 */
+#define PA14E_TC4_WO0 \
+	SAM_PINMUX(a, 14, e, periph)
+
+/* pa14f_tcc0_wo4 */
+#define PA14F_TCC0_WO4 \
+	SAM_PINMUX(a, 14, f, periph)
+
+/* pa14h_gclk_io0 */
+#define PA14H_GCLK_IO0 \
+	SAM_PINMUX(a, 14, h, periph)
+
+/* pa15_gpio */
+#define PA15_GPIO \
+	SAM_PINMUX(a, 15, gpio, gpio)
+
+/* pa15a_eic_extint15 */
+#define PA15A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 15, a, periph)
+
+/* pa15c_sercom2_pad3 */
+#define PA15C_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 15, c, periph)
+
+/* pa15d_sercom4_pad3 */
+#define PA15D_SERCOM4_PAD3 \
+	SAM_PINMUX(a, 15, d, periph)
+
+/* pa15e_tc4_wo1 */
+#define PA15E_TC4_WO1 \
+	SAM_PINMUX(a, 15, e, periph)
+
+/* pa15f_tcc0_wo5 */
+#define PA15F_TCC0_WO5 \
+	SAM_PINMUX(a, 15, f, periph)
+
+/* pa15h_gclk_io1 */
+#define PA15H_GCLK_IO1 \
+	SAM_PINMUX(a, 15, h, periph)
+
+/* pa16_gpio */
+#define PA16_GPIO \
+	SAM_PINMUX(a, 16, gpio, gpio)
+
+/* pa16a_eic_extint0 */
+#define PA16A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 16, a, periph)
+
+/* pa16b_ptc_x4 */
+#define PA16B_PTC_X4 \
+	SAM_PINMUX(a, 16, b, periph)
+
+/* pa16c_sercom1_pad0 */
+#define PA16C_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 16, c, periph)
+
+/* pa16d_sercom3_pad0 */
+#define PA16D_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 16, d, periph)
+
+/* pa16e_tcc2_wo0 */
+#define PA16E_TCC2_WO0 \
+	SAM_PINMUX(a, 16, e, periph)
+
+/* pa16f_tcc0_wo6 */
+#define PA16F_TCC0_WO6 \
+	SAM_PINMUX(a, 16, f, periph)
+
+/* pa16h_gclk_io2 */
+#define PA16H_GCLK_IO2 \
+	SAM_PINMUX(a, 16, h, periph)
+
+/* pa17_gpio */
+#define PA17_GPIO \
+	SAM_PINMUX(a, 17, gpio, gpio)
+
+/* pa17a_eic_extint1 */
+#define PA17A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 17, a, periph)
+
+/* pa17b_ptc_x5 */
+#define PA17B_PTC_X5 \
+	SAM_PINMUX(a, 17, b, periph)
+
+/* pa17c_sercom1_pad1 */
+#define PA17C_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 17, c, periph)
+
+/* pa17d_sercom3_pad1 */
+#define PA17D_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 17, d, periph)
+
+/* pa17e_tcc2_wo1 */
+#define PA17E_TCC2_WO1 \
+	SAM_PINMUX(a, 17, e, periph)
+
+/* pa17f_tcc0_wo7 */
+#define PA17F_TCC0_WO7 \
+	SAM_PINMUX(a, 17, f, periph)
+
+/* pa17h_gclk_io3 */
+#define PA17H_GCLK_IO3 \
+	SAM_PINMUX(a, 17, h, periph)
+
+/* pa18_gpio */
+#define PA18_GPIO \
+	SAM_PINMUX(a, 18, gpio, gpio)
+
+/* pa18a_eic_extint2 */
+#define PA18A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 18, a, periph)
+
+/* pa18b_ptc_x6 */
+#define PA18B_PTC_X6 \
+	SAM_PINMUX(a, 18, b, periph)
+
+/* pa18c_sercom1_pad2 */
+#define PA18C_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 18, c, periph)
+
+/* pa18d_sercom3_pad2 */
+#define PA18D_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 18, d, periph)
+
+/* pa18e_tc4_wo0 */
+#define PA18E_TC4_WO0 \
+	SAM_PINMUX(a, 18, e, periph)
+
+/* pa18f_tcc0_wo2 */
+#define PA18F_TCC0_WO2 \
+	SAM_PINMUX(a, 18, f, periph)
+
+/* pa18h_ac_cmp0 */
+#define PA18H_AC_CMP0 \
+	SAM_PINMUX(a, 18, h, periph)
+
+/* pa19_gpio */
+#define PA19_GPIO \
+	SAM_PINMUX(a, 19, gpio, gpio)
+
+/* pa19a_eic_extint3 */
+#define PA19A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 19, a, periph)
+
+/* pa19b_ptc_x7 */
+#define PA19B_PTC_X7 \
+	SAM_PINMUX(a, 19, b, periph)
+
+/* pa19c_sercom1_pad3 */
+#define PA19C_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 19, c, periph)
+
+/* pa19d_sercom3_pad3 */
+#define PA19D_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 19, d, periph)
+
+/* pa19e_tc4_wo1 */
+#define PA19E_TC4_WO1 \
+	SAM_PINMUX(a, 19, e, periph)
+
+/* pa19f_tcc0_wo3 */
+#define PA19F_TCC0_WO3 \
+	SAM_PINMUX(a, 19, f, periph)
+
+/* pa19h_ac_cmp1 */
+#define PA19H_AC_CMP1 \
+	SAM_PINMUX(a, 19, h, periph)
+
+/* pa22_gpio */
+#define PA22_GPIO \
+	SAM_PINMUX(a, 22, gpio, gpio)
+
+/* pa22a_eic_extint6 */
+#define PA22A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 22, a, periph)
+
+/* pa22b_ptc_x10 */
+#define PA22B_PTC_X10 \
+	SAM_PINMUX(a, 22, b, periph)
+
+/* pa22c_sercom3_pad0 */
+#define PA22C_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 22, c, periph)
+
+/* pa22d_sercom5_pad0 */
+#define PA22D_SERCOM5_PAD0 \
+	SAM_PINMUX(a, 22, d, periph)
+
+/* pa22e_tc0_wo0 */
+#define PA22E_TC0_WO0 \
+	SAM_PINMUX(a, 22, e, periph)
+
+/* pa22f_tcc0_wo4 */
+#define PA22F_TCC0_WO4 \
+	SAM_PINMUX(a, 22, f, periph)
+
+/* pa22h_gclk_io6 */
+#define PA22H_GCLK_IO6 \
+	SAM_PINMUX(a, 22, h, periph)
+
+/* pa23_gpio */
+#define PA23_GPIO \
+	SAM_PINMUX(a, 23, gpio, gpio)
+
+/* pa23a_eic_extint7 */
+#define PA23A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 23, a, periph)
+
+/* pa23b_ptc_x11 */
+#define PA23B_PTC_X11 \
+	SAM_PINMUX(a, 23, b, periph)
+
+/* pa23c_sercom3_pad1 */
+#define PA23C_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 23, c, periph)
+
+/* pa23d_sercom5_pad1 */
+#define PA23D_SERCOM5_PAD1 \
+	SAM_PINMUX(a, 23, d, periph)
+
+/* pa23e_tc0_wo1 */
+#define PA23E_TC0_WO1 \
+	SAM_PINMUX(a, 23, e, periph)
+
+/* pa23f_tcc0_wo5 */
+#define PA23F_TCC0_WO5 \
+	SAM_PINMUX(a, 23, f, periph)
+
+/* pa23h_gclk_io7 */
+#define PA23H_GCLK_IO7 \
+	SAM_PINMUX(a, 23, h, periph)
+
+/* pa24_gpio */
+#define PA24_GPIO \
+	SAM_PINMUX(a, 24, gpio, gpio)
+
+/* pa24a_eic_extint12 */
+#define PA24A_EIC_EXTINT12 \
+	SAM_PINMUX(a, 24, a, periph)
+
+/* pa24c_sercom3_pad2 */
+#define PA24C_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 24, c, periph)
+
+/* pa24d_sercom5_pad2 */
+#define PA24D_SERCOM5_PAD2 \
+	SAM_PINMUX(a, 24, d, periph)
+
+/* pa24e_tc1_wo0 */
+#define PA24E_TC1_WO0 \
+	SAM_PINMUX(a, 24, e, periph)
+
+/* pa24f_tcc1_wo2 */
+#define PA24F_TCC1_WO2 \
+	SAM_PINMUX(a, 24, f, periph)
+
+/* pa24g_can0_tx */
+#define PA24G_CAN0_TX \
+	SAM_PINMUX(a, 24, g, periph)
+
+/* pa24h_ac_cmp2 */
+#define PA24H_AC_CMP2 \
+	SAM_PINMUX(a, 24, h, periph)
+
+/* pa25_gpio */
+#define PA25_GPIO \
+	SAM_PINMUX(a, 25, gpio, gpio)
+
+/* pa25a_eic_extint13 */
+#define PA25A_EIC_EXTINT13 \
+	SAM_PINMUX(a, 25, a, periph)
+
+/* pa25c_sercom3_pad3 */
+#define PA25C_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 25, c, periph)
+
+/* pa25d_sercom5_pad3 */
+#define PA25D_SERCOM5_PAD3 \
+	SAM_PINMUX(a, 25, d, periph)
+
+/* pa25e_tc1_wo1 */
+#define PA25E_TC1_WO1 \
+	SAM_PINMUX(a, 25, e, periph)
+
+/* pa25f_tcc1_wo3 */
+#define PA25F_TCC1_WO3 \
+	SAM_PINMUX(a, 25, f, periph)
+
+/* pa25g_can0_rx */
+#define PA25G_CAN0_RX \
+	SAM_PINMUX(a, 25, g, periph)
+
+/* pa25h_ac_cmp3 */
+#define PA25H_AC_CMP3 \
+	SAM_PINMUX(a, 25, h, periph)
+
+/* pa27_gpio */
+#define PA27_GPIO \
+	SAM_PINMUX(a, 27, gpio, gpio)
+
+/* pa27a_eic_extint15 */
+#define PA27A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 27, a, periph)
+
+/* pa27h_gclk_io0 */
+#define PA27H_GCLK_IO0 \
+	SAM_PINMUX(a, 27, h, periph)
+
+/* pa28_gpio */
+#define PA28_GPIO \
+	SAM_PINMUX(a, 28, gpio, gpio)
+
+/* pa28a_eic_extint8 */
+#define PA28A_EIC_EXTINT8 \
+	SAM_PINMUX(a, 28, a, periph)
+
+/* pa28h_gclk_io0 */
+#define PA28H_GCLK_IO0 \
+	SAM_PINMUX(a, 28, h, periph)
+
+/* pa30_gpio */
+#define PA30_GPIO \
+	SAM_PINMUX(a, 30, gpio, gpio)
+
+/* pa30a_eic_extint10 */
+#define PA30A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 30, a, periph)
+
+/* pa30d_sercom1_pad2 */
+#define PA30D_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 30, d, periph)
+
+/* pa30e_tcc1_wo0 */
+#define PA30E_TCC1_WO0 \
+	SAM_PINMUX(a, 30, e, periph)
+
+/* pa30g_swd_clk */
+#define PA30G_SWD_CLK \
+	SAM_PINMUX(a, 30, g, periph)
+
+/* pa30h_gclk_io0 */
+#define PA30H_GCLK_IO0 \
+	SAM_PINMUX(a, 30, h, periph)
+
+/* pa31_gpio */
+#define PA31_GPIO \
+	SAM_PINMUX(a, 31, gpio, gpio)
+
+/* pa31a_eic_extint11 */
+#define PA31A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 31, a, periph)
+
+/* pa31d_sercom1_pad3 */
+#define PA31D_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 31, d, periph)
+
+/* pa31e_tcc1_wo1 */
+#define PA31E_TCC1_WO1 \
+	SAM_PINMUX(a, 31, e, periph)
+
+/* pa31g_swd_io */
+#define PA31G_SWD_IO \
+	SAM_PINMUX(a, 31, g, periph)
diff --git a/include/dt-bindings/pinctrl/samc21g-pinctrl.h b/include/dt-bindings/pinctrl/samc21g-pinctrl.h
new file mode 100644
index 0000000..02a4598
--- /dev/null
+++ b/include/dt-bindings/pinctrl/samc21g-pinctrl.h
@@ -0,0 +1,1079 @@
+/*
+ * Autogenerated file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/atmel_sam_pinctrl.h>
+
+/* pa0_gpio */
+#define PA0_GPIO \
+	SAM_PINMUX(a, 0, gpio, gpio)
+
+/* pa0a_eic_extint0 */
+#define PA0A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 0, a, periph)
+
+/* pa0d_sercom1_pad0 */
+#define PA0D_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 0, d, periph)
+
+/* pa0e_tc2_wo0 */
+#define PA0E_TC2_WO0 \
+	SAM_PINMUX(a, 0, e, periph)
+
+/* pa0h_ac_cmp2 */
+#define PA0H_AC_CMP2 \
+	SAM_PINMUX(a, 0, h, periph)
+
+/* pa1_gpio */
+#define PA1_GPIO \
+	SAM_PINMUX(a, 1, gpio, gpio)
+
+/* pa1a_eic_extint1 */
+#define PA1A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 1, a, periph)
+
+/* pa1d_sercom1_pad1 */
+#define PA1D_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 1, d, periph)
+
+/* pa1e_tc2_wo1 */
+#define PA1E_TC2_WO1 \
+	SAM_PINMUX(a, 1, e, periph)
+
+/* pa1h_ac_cmp3 */
+#define PA1H_AC_CMP3 \
+	SAM_PINMUX(a, 1, h, periph)
+
+/* pa2_gpio */
+#define PA2_GPIO \
+	SAM_PINMUX(a, 2, gpio, gpio)
+
+/* pa2a_eic_extint2 */
+#define PA2A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 2, a, periph)
+
+/* pa2b_adc0_ain0 */
+#define PA2B_ADC0_AIN0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ac_ain4 */
+#define PA2B_AC_AIN4 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ptc_y0 */
+#define PA2B_PTC_Y0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_dac_vout */
+#define PA2B_DAC_VOUT \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa3_gpio */
+#define PA3_GPIO \
+	SAM_PINMUX(a, 3, gpio, gpio)
+
+/* pa3a_eic_extint3 */
+#define PA3A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 3, a, periph)
+
+/* pa3b_anaref_vrefa */
+#define PA3B_ANAREF_VREFA \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_adc0_ain5 */
+#define PA3B_ADC0_AIN5 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ac_ain4 */
+#define PA3B_AC_AIN4 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ptc_y1 */
+#define PA3B_PTC_Y1 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa4_gpio */
+#define PA4_GPIO \
+	SAM_PINMUX(a, 4, gpio, gpio)
+
+/* pa4a_eic_extint4 */
+#define PA4A_EIC_EXTINT4 \
+	SAM_PINMUX(a, 4, a, periph)
+
+/* pa4b_anaref_vrefb */
+#define PA4B_ANAREF_VREFB \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_adc0_ain4 */
+#define PA4B_ADC0_AIN4 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ac_ain0 */
+#define PA4B_AC_AIN0 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ptc_y2 */
+#define PA4B_PTC_Y2 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4d_sercom0_pad0 */
+#define PA4D_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 4, d, periph)
+
+/* pa4e_tcc0_wo0 */
+#define PA4E_TCC0_WO0 \
+	SAM_PINMUX(a, 4, e, periph)
+
+/* pa5_gpio */
+#define PA5_GPIO \
+	SAM_PINMUX(a, 5, gpio, gpio)
+
+/* pa5a_eic_extint5 */
+#define PA5A_EIC_EXTINT5 \
+	SAM_PINMUX(a, 5, a, periph)
+
+/* pa5b_adc0_ain5 */
+#define PA5B_ADC0_AIN5 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ac_ain1 */
+#define PA5B_AC_AIN1 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ptc_y3 */
+#define PA5B_PTC_Y3 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5d_sercom0_pad1 */
+#define PA5D_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 5, d, periph)
+
+/* pa5e_tcc0_wo1 */
+#define PA5E_TCC0_WO1 \
+	SAM_PINMUX(a, 5, e, periph)
+
+/* pa6_gpio */
+#define PA6_GPIO \
+	SAM_PINMUX(a, 6, gpio, gpio)
+
+/* pa6a_eic_extint6 */
+#define PA6A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 6, a, periph)
+
+/* pa6b_adc0_ain6 */
+#define PA6B_ADC0_AIN6 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ac_ain2 */
+#define PA6B_AC_AIN2 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ptc_y4 */
+#define PA6B_PTC_Y4 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_sdadc0_ainn0 */
+#define PA6B_SDADC0_AINN0 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6d_sercom0_pad2 */
+#define PA6D_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 6, d, periph)
+
+/* pa6e_tcc1_wo0 */
+#define PA6E_TCC1_WO0 \
+	SAM_PINMUX(a, 6, e, periph)
+
+/* pa7_gpio */
+#define PA7_GPIO \
+	SAM_PINMUX(a, 7, gpio, gpio)
+
+/* pa7a_eic_extint7 */
+#define PA7A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 7, a, periph)
+
+/* pa7b_adc0_ain7 */
+#define PA7B_ADC0_AIN7 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ac_ain3 */
+#define PA7B_AC_AIN3 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ptc_y5 */
+#define PA7B_PTC_Y5 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_sdadc0_ainp0 */
+#define PA7B_SDADC0_AINP0 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7d_sercom0_pad3 */
+#define PA7D_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 7, d, periph)
+
+/* pa7e_tcc1_wo1 */
+#define PA7E_TCC1_WO1 \
+	SAM_PINMUX(a, 7, e, periph)
+
+/* pa8_gpio */
+#define PA8_GPIO \
+	SAM_PINMUX(a, 8, gpio, gpio)
+
+/* pa8a_eic_nmi */
+#define PA8A_EIC_NMI \
+	SAM_PINMUX(a, 8, a, periph)
+
+/* pa8b_adc0_ain8 */
+#define PA8B_ADC0_AIN8 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8b_adc1_ain10 */
+#define PA8B_ADC1_AIN10 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8b_ptc_xy16 */
+#define PA8B_PTC_XY16 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8c_sercom0_pad0 */
+#define PA8C_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 8, c, periph)
+
+/* pa8d_sercom2_pad0 */
+#define PA8D_SERCOM2_PAD0 \
+	SAM_PINMUX(a, 8, d, periph)
+
+/* pa8e_tcc0_wo0 */
+#define PA8E_TCC0_WO0 \
+	SAM_PINMUX(a, 8, e, periph)
+
+/* pa8f_tcc1_wo2 */
+#define PA8F_TCC1_WO2 \
+	SAM_PINMUX(a, 8, f, periph)
+
+/* pa9_gpio */
+#define PA9_GPIO \
+	SAM_PINMUX(a, 9, gpio, gpio)
+
+/* pa9a_eic_extint9 */
+#define PA9A_EIC_EXTINT9 \
+	SAM_PINMUX(a, 9, a, periph)
+
+/* pa9b_adc0_ain9 */
+#define PA9B_ADC0_AIN9 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9b_adc1_ain11 */
+#define PA9B_ADC1_AIN11 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9b_ptc_x1 */
+#define PA9B_PTC_X1 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9c_sercom0_pad1 */
+#define PA9C_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 9, c, periph)
+
+/* pa9d_sercom2_pad1 */
+#define PA9D_SERCOM2_PAD1 \
+	SAM_PINMUX(a, 9, d, periph)
+
+/* pa9e_tcc0_wo1 */
+#define PA9E_TCC0_WO1 \
+	SAM_PINMUX(a, 9, e, periph)
+
+/* pa9f_tcc1_wo3 */
+#define PA9F_TCC1_WO3 \
+	SAM_PINMUX(a, 9, f, periph)
+
+/* pa10_gpio */
+#define PA10_GPIO \
+	SAM_PINMUX(a, 10, gpio, gpio)
+
+/* pa10a_eic_extint10 */
+#define PA10A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 10, a, periph)
+
+/* pa10b_adc0_ain10 */
+#define PA10B_ADC0_AIN10 \
+	SAM_PINMUX(a, 10, b, periph)
+
+/* pa10b_ptc_x2 */
+#define PA10B_PTC_X2 \
+	SAM_PINMUX(a, 10, b, periph)
+
+/* pa10c_sercom0_pad2 */
+#define PA10C_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 10, c, periph)
+
+/* pa10d_sercom2_pad2 */
+#define PA10D_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 10, d, periph)
+
+/* pa10e_tcc1_wo0 */
+#define PA10E_TCC1_WO0 \
+	SAM_PINMUX(a, 10, e, periph)
+
+/* pa10f_tcc0_wo2 */
+#define PA10F_TCC0_WO2 \
+	SAM_PINMUX(a, 10, f, periph)
+
+/* pa10h_gclk_io4 */
+#define PA10H_GCLK_IO4 \
+	SAM_PINMUX(a, 10, h, periph)
+
+/* pa11_gpio */
+#define PA11_GPIO \
+	SAM_PINMUX(a, 11, gpio, gpio)
+
+/* pa11a_eic_extint11 */
+#define PA11A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 11, a, periph)
+
+/* pa11b_adc0_ain11 */
+#define PA11B_ADC0_AIN11 \
+	SAM_PINMUX(a, 11, b, periph)
+
+/* pa11b_ptc_x3 */
+#define PA11B_PTC_X3 \
+	SAM_PINMUX(a, 11, b, periph)
+
+/* pa11c_sercom0_pad3 */
+#define PA11C_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 11, c, periph)
+
+/* pa11d_sercom2_pad3 */
+#define PA11D_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 11, d, periph)
+
+/* pa11e_tcc1_wo1 */
+#define PA11E_TCC1_WO1 \
+	SAM_PINMUX(a, 11, e, periph)
+
+/* pa11f_tcc0_wo3 */
+#define PA11F_TCC0_WO3 \
+	SAM_PINMUX(a, 11, f, periph)
+
+/* pa11h_gclk_io5 */
+#define PA11H_GCLK_IO5 \
+	SAM_PINMUX(a, 11, h, periph)
+
+/* pa12_gpio */
+#define PA12_GPIO \
+	SAM_PINMUX(a, 12, gpio, gpio)
+
+/* pa12a_eic_extint12 */
+#define PA12A_EIC_EXTINT12 \
+	SAM_PINMUX(a, 12, a, periph)
+
+/* pa12c_sercom2_pad0 */
+#define PA12C_SERCOM2_PAD0 \
+	SAM_PINMUX(a, 12, c, periph)
+
+/* pa12d_sercom4_pad0 */
+#define PA12D_SERCOM4_PAD0 \
+	SAM_PINMUX(a, 12, d, periph)
+
+/* pa12e_tcc2_wo0 */
+#define PA12E_TCC2_WO0 \
+	SAM_PINMUX(a, 12, e, periph)
+
+/* pa12f_tcc0_wo6 */
+#define PA12F_TCC0_WO6 \
+	SAM_PINMUX(a, 12, f, periph)
+
+/* pa12h_ac_cmp0 */
+#define PA12H_AC_CMP0 \
+	SAM_PINMUX(a, 12, h, periph)
+
+/* pa13_gpio */
+#define PA13_GPIO \
+	SAM_PINMUX(a, 13, gpio, gpio)
+
+/* pa13a_eic_extint13 */
+#define PA13A_EIC_EXTINT13 \
+	SAM_PINMUX(a, 13, a, periph)
+
+/* pa13c_sercom2_pad1 */
+#define PA13C_SERCOM2_PAD1 \
+	SAM_PINMUX(a, 13, c, periph)
+
+/* pa13d_sercom4_pad1 */
+#define PA13D_SERCOM4_PAD1 \
+	SAM_PINMUX(a, 13, d, periph)
+
+/* pa13e_tcc2_wo1 */
+#define PA13E_TCC2_WO1 \
+	SAM_PINMUX(a, 13, e, periph)
+
+/* pa13f_tcc0_wo7 */
+#define PA13F_TCC0_WO7 \
+	SAM_PINMUX(a, 13, f, periph)
+
+/* pa13h_ac_cmp1 */
+#define PA13H_AC_CMP1 \
+	SAM_PINMUX(a, 13, h, periph)
+
+/* pa14_gpio */
+#define PA14_GPIO \
+	SAM_PINMUX(a, 14, gpio, gpio)
+
+/* pa14a_eic_extint14 */
+#define PA14A_EIC_EXTINT14 \
+	SAM_PINMUX(a, 14, a, periph)
+
+/* pa14c_sercom2_pad2 */
+#define PA14C_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 14, c, periph)
+
+/* pa14d_sercom4_pad2 */
+#define PA14D_SERCOM4_PAD2 \
+	SAM_PINMUX(a, 14, d, periph)
+
+/* pa14e_tc4_wo0 */
+#define PA14E_TC4_WO0 \
+	SAM_PINMUX(a, 14, e, periph)
+
+/* pa14f_tcc0_wo4 */
+#define PA14F_TCC0_WO4 \
+	SAM_PINMUX(a, 14, f, periph)
+
+/* pa14h_gclk_io0 */
+#define PA14H_GCLK_IO0 \
+	SAM_PINMUX(a, 14, h, periph)
+
+/* pa15_gpio */
+#define PA15_GPIO \
+	SAM_PINMUX(a, 15, gpio, gpio)
+
+/* pa15a_eic_extint15 */
+#define PA15A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 15, a, periph)
+
+/* pa15c_sercom2_pad3 */
+#define PA15C_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 15, c, periph)
+
+/* pa15d_sercom4_pad3 */
+#define PA15D_SERCOM4_PAD3 \
+	SAM_PINMUX(a, 15, d, periph)
+
+/* pa15e_tc4_wo1 */
+#define PA15E_TC4_WO1 \
+	SAM_PINMUX(a, 15, e, periph)
+
+/* pa15f_tcc0_wo5 */
+#define PA15F_TCC0_WO5 \
+	SAM_PINMUX(a, 15, f, periph)
+
+/* pa15h_gclk_io1 */
+#define PA15H_GCLK_IO1 \
+	SAM_PINMUX(a, 15, h, periph)
+
+/* pa16_gpio */
+#define PA16_GPIO \
+	SAM_PINMUX(a, 16, gpio, gpio)
+
+/* pa16a_eic_extint0 */
+#define PA16A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 16, a, periph)
+
+/* pa16b_ptc_x4 */
+#define PA16B_PTC_X4 \
+	SAM_PINMUX(a, 16, b, periph)
+
+/* pa16c_sercom1_pad0 */
+#define PA16C_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 16, c, periph)
+
+/* pa16d_sercom3_pad0 */
+#define PA16D_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 16, d, periph)
+
+/* pa16e_tcc2_wo0 */
+#define PA16E_TCC2_WO0 \
+	SAM_PINMUX(a, 16, e, periph)
+
+/* pa16f_tcc0_wo6 */
+#define PA16F_TCC0_WO6 \
+	SAM_PINMUX(a, 16, f, periph)
+
+/* pa16h_gclk_io2 */
+#define PA16H_GCLK_IO2 \
+	SAM_PINMUX(a, 16, h, periph)
+
+/* pa17_gpio */
+#define PA17_GPIO \
+	SAM_PINMUX(a, 17, gpio, gpio)
+
+/* pa17a_eic_extint1 */
+#define PA17A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 17, a, periph)
+
+/* pa17b_ptc_x5 */
+#define PA17B_PTC_X5 \
+	SAM_PINMUX(a, 17, b, periph)
+
+/* pa17c_sercom1_pad1 */
+#define PA17C_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 17, c, periph)
+
+/* pa17d_sercom3_pad1 */
+#define PA17D_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 17, d, periph)
+
+/* pa17e_tcc2_wo1 */
+#define PA17E_TCC2_WO1 \
+	SAM_PINMUX(a, 17, e, periph)
+
+/* pa17f_tcc0_wo7 */
+#define PA17F_TCC0_WO7 \
+	SAM_PINMUX(a, 17, f, periph)
+
+/* pa17h_gclk_io3 */
+#define PA17H_GCLK_IO3 \
+	SAM_PINMUX(a, 17, h, periph)
+
+/* pa18_gpio */
+#define PA18_GPIO \
+	SAM_PINMUX(a, 18, gpio, gpio)
+
+/* pa18a_eic_extint2 */
+#define PA18A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 18, a, periph)
+
+/* pa18b_ptc_x6 */
+#define PA18B_PTC_X6 \
+	SAM_PINMUX(a, 18, b, periph)
+
+/* pa18c_sercom1_pad2 */
+#define PA18C_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 18, c, periph)
+
+/* pa18d_sercom3_pad2 */
+#define PA18D_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 18, d, periph)
+
+/* pa18e_tc4_wo0 */
+#define PA18E_TC4_WO0 \
+	SAM_PINMUX(a, 18, e, periph)
+
+/* pa18f_tcc0_wo2 */
+#define PA18F_TCC0_WO2 \
+	SAM_PINMUX(a, 18, f, periph)
+
+/* pa18h_ac_cmp0 */
+#define PA18H_AC_CMP0 \
+	SAM_PINMUX(a, 18, h, periph)
+
+/* pa19_gpio */
+#define PA19_GPIO \
+	SAM_PINMUX(a, 19, gpio, gpio)
+
+/* pa19a_eic_extint3 */
+#define PA19A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 19, a, periph)
+
+/* pa19b_ptc_x7 */
+#define PA19B_PTC_X7 \
+	SAM_PINMUX(a, 19, b, periph)
+
+/* pa19c_sercom1_pad3 */
+#define PA19C_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 19, c, periph)
+
+/* pa19d_sercom3_pad3 */
+#define PA19D_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 19, d, periph)
+
+/* pa19e_tc4_wo1 */
+#define PA19E_TC4_WO1 \
+	SAM_PINMUX(a, 19, e, periph)
+
+/* pa19f_tcc0_wo3 */
+#define PA19F_TCC0_WO3 \
+	SAM_PINMUX(a, 19, f, periph)
+
+/* pa19h_ac_cmp1 */
+#define PA19H_AC_CMP1 \
+	SAM_PINMUX(a, 19, h, periph)
+
+/* pa20_gpio */
+#define PA20_GPIO \
+	SAM_PINMUX(a, 20, gpio, gpio)
+
+/* pa20a_eic_extint4 */
+#define PA20A_EIC_EXTINT4 \
+	SAM_PINMUX(a, 20, a, periph)
+
+/* pa20b_ptc_x8 */
+#define PA20B_PTC_X8 \
+	SAM_PINMUX(a, 20, b, periph)
+
+/* pa20c_sercom5_pad2 */
+#define PA20C_SERCOM5_PAD2 \
+	SAM_PINMUX(a, 20, c, periph)
+
+/* pa20d_sercom3_pad2 */
+#define PA20D_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 20, d, periph)
+
+/* pa20e_tc3_wo0 */
+#define PA20E_TC3_WO0 \
+	SAM_PINMUX(a, 20, e, periph)
+
+/* pa20f_tcc0_wo6 */
+#define PA20F_TCC0_WO6 \
+	SAM_PINMUX(a, 20, f, periph)
+
+/* pa20h_gclk_io4 */
+#define PA20H_GCLK_IO4 \
+	SAM_PINMUX(a, 20, h, periph)
+
+/* pa21_gpio */
+#define PA21_GPIO \
+	SAM_PINMUX(a, 21, gpio, gpio)
+
+/* pa21a_eic_extint5 */
+#define PA21A_EIC_EXTINT5 \
+	SAM_PINMUX(a, 21, a, periph)
+
+/* pa21b_ptc_x9 */
+#define PA21B_PTC_X9 \
+	SAM_PINMUX(a, 21, b, periph)
+
+/* pa21c_sercom5_pad3 */
+#define PA21C_SERCOM5_PAD3 \
+	SAM_PINMUX(a, 21, c, periph)
+
+/* pa21d_sercom3_pad3 */
+#define PA21D_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 21, d, periph)
+
+/* pa21e_tc3_wo1 */
+#define PA21E_TC3_WO1 \
+	SAM_PINMUX(a, 21, e, periph)
+
+/* pa21f_tcc0_wo7 */
+#define PA21F_TCC0_WO7 \
+	SAM_PINMUX(a, 21, f, periph)
+
+/* pa21h_gclk_io5 */
+#define PA21H_GCLK_IO5 \
+	SAM_PINMUX(a, 21, h, periph)
+
+/* pa22_gpio */
+#define PA22_GPIO \
+	SAM_PINMUX(a, 22, gpio, gpio)
+
+/* pa22a_eic_extint6 */
+#define PA22A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 22, a, periph)
+
+/* pa22b_ptc_x10 */
+#define PA22B_PTC_X10 \
+	SAM_PINMUX(a, 22, b, periph)
+
+/* pa22c_sercom3_pad0 */
+#define PA22C_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 22, c, periph)
+
+/* pa22d_sercom5_pad0 */
+#define PA22D_SERCOM5_PAD0 \
+	SAM_PINMUX(a, 22, d, periph)
+
+/* pa22e_tc0_wo0 */
+#define PA22E_TC0_WO0 \
+	SAM_PINMUX(a, 22, e, periph)
+
+/* pa22f_tcc0_wo4 */
+#define PA22F_TCC0_WO4 \
+	SAM_PINMUX(a, 22, f, periph)
+
+/* pa22h_gclk_io6 */
+#define PA22H_GCLK_IO6 \
+	SAM_PINMUX(a, 22, h, periph)
+
+/* pa23_gpio */
+#define PA23_GPIO \
+	SAM_PINMUX(a, 23, gpio, gpio)
+
+/* pa23a_eic_extint7 */
+#define PA23A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 23, a, periph)
+
+/* pa23b_ptc_x11 */
+#define PA23B_PTC_X11 \
+	SAM_PINMUX(a, 23, b, periph)
+
+/* pa23c_sercom3_pad1 */
+#define PA23C_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 23, c, periph)
+
+/* pa23d_sercom5_pad1 */
+#define PA23D_SERCOM5_PAD1 \
+	SAM_PINMUX(a, 23, d, periph)
+
+/* pa23e_tc0_wo1 */
+#define PA23E_TC0_WO1 \
+	SAM_PINMUX(a, 23, e, periph)
+
+/* pa23f_tcc0_wo5 */
+#define PA23F_TCC0_WO5 \
+	SAM_PINMUX(a, 23, f, periph)
+
+/* pa23h_gclk_io7 */
+#define PA23H_GCLK_IO7 \
+	SAM_PINMUX(a, 23, h, periph)
+
+/* pa24_gpio */
+#define PA24_GPIO \
+	SAM_PINMUX(a, 24, gpio, gpio)
+
+/* pa24a_eic_extint12 */
+#define PA24A_EIC_EXTINT12 \
+	SAM_PINMUX(a, 24, a, periph)
+
+/* pa24c_sercom3_pad2 */
+#define PA24C_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 24, c, periph)
+
+/* pa24d_sercom5_pad2 */
+#define PA24D_SERCOM5_PAD2 \
+	SAM_PINMUX(a, 24, d, periph)
+
+/* pa24e_tc1_wo0 */
+#define PA24E_TC1_WO0 \
+	SAM_PINMUX(a, 24, e, periph)
+
+/* pa24f_tcc1_wo2 */
+#define PA24F_TCC1_WO2 \
+	SAM_PINMUX(a, 24, f, periph)
+
+/* pa24g_can0_tx */
+#define PA24G_CAN0_TX \
+	SAM_PINMUX(a, 24, g, periph)
+
+/* pa24h_ac_cmp2 */
+#define PA24H_AC_CMP2 \
+	SAM_PINMUX(a, 24, h, periph)
+
+/* pa25_gpio */
+#define PA25_GPIO \
+	SAM_PINMUX(a, 25, gpio, gpio)
+
+/* pa25a_eic_extint13 */
+#define PA25A_EIC_EXTINT13 \
+	SAM_PINMUX(a, 25, a, periph)
+
+/* pa25c_sercom3_pad3 */
+#define PA25C_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 25, c, periph)
+
+/* pa25d_sercom5_pad3 */
+#define PA25D_SERCOM5_PAD3 \
+	SAM_PINMUX(a, 25, d, periph)
+
+/* pa25e_tc1_wo1 */
+#define PA25E_TC1_WO1 \
+	SAM_PINMUX(a, 25, e, periph)
+
+/* pa25f_tcc1_wo3 */
+#define PA25F_TCC1_WO3 \
+	SAM_PINMUX(a, 25, f, periph)
+
+/* pa25g_can0_rx */
+#define PA25G_CAN0_RX \
+	SAM_PINMUX(a, 25, g, periph)
+
+/* pa25h_ac_cmp3 */
+#define PA25H_AC_CMP3 \
+	SAM_PINMUX(a, 25, h, periph)
+
+/* pa27_gpio */
+#define PA27_GPIO \
+	SAM_PINMUX(a, 27, gpio, gpio)
+
+/* pa27a_eic_extint15 */
+#define PA27A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 27, a, periph)
+
+/* pa27h_gclk_io0 */
+#define PA27H_GCLK_IO0 \
+	SAM_PINMUX(a, 27, h, periph)
+
+/* pa28_gpio */
+#define PA28_GPIO \
+	SAM_PINMUX(a, 28, gpio, gpio)
+
+/* pa28a_eic_extint8 */
+#define PA28A_EIC_EXTINT8 \
+	SAM_PINMUX(a, 28, a, periph)
+
+/* pa28h_gclk_io0 */
+#define PA28H_GCLK_IO0 \
+	SAM_PINMUX(a, 28, h, periph)
+
+/* pa30_gpio */
+#define PA30_GPIO \
+	SAM_PINMUX(a, 30, gpio, gpio)
+
+/* pa30a_eic_extint10 */
+#define PA30A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 30, a, periph)
+
+/* pa30d_sercom1_pad2 */
+#define PA30D_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 30, d, periph)
+
+/* pa30e_tcc1_wo0 */
+#define PA30E_TCC1_WO0 \
+	SAM_PINMUX(a, 30, e, periph)
+
+/* pa30g_swd_clk */
+#define PA30G_SWD_CLK \
+	SAM_PINMUX(a, 30, g, periph)
+
+/* pa30h_gclk_io0 */
+#define PA30H_GCLK_IO0 \
+	SAM_PINMUX(a, 30, h, periph)
+
+/* pa31_gpio */
+#define PA31_GPIO \
+	SAM_PINMUX(a, 31, gpio, gpio)
+
+/* pa31a_eic_extint11 */
+#define PA31A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 31, a, periph)
+
+/* pa31d_sercom1_pad3 */
+#define PA31D_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 31, d, periph)
+
+/* pa31e_tcc1_wo1 */
+#define PA31E_TCC1_WO1 \
+	SAM_PINMUX(a, 31, e, periph)
+
+/* pa31g_swd_io */
+#define PA31G_SWD_IO \
+	SAM_PINMUX(a, 31, g, periph)
+
+/* pb2_gpio */
+#define PB2_GPIO \
+	SAM_PINMUX(b, 2, gpio, gpio)
+
+/* pb2a_eic_extint2 */
+#define PB2A_EIC_EXTINT2 \
+	SAM_PINMUX(b, 2, a, periph)
+
+/* pb2b_adc1_ain2 */
+#define PB2B_ADC1_AIN2 \
+	SAM_PINMUX(b, 2, b, periph)
+
+/* pb2b_ptc_y8 */
+#define PB2B_PTC_Y8 \
+	SAM_PINMUX(b, 2, b, periph)
+
+/* pb2d_sercom5_pad0 */
+#define PB2D_SERCOM5_PAD0 \
+	SAM_PINMUX(b, 2, d, periph)
+
+/* pb2e_tc2_wo0 */
+#define PB2E_TC2_WO0 \
+	SAM_PINMUX(b, 2, e, periph)
+
+/* pb3_gpio */
+#define PB3_GPIO \
+	SAM_PINMUX(b, 3, gpio, gpio)
+
+/* pb3a_eic_extint3 */
+#define PB3A_EIC_EXTINT3 \
+	SAM_PINMUX(b, 3, a, periph)
+
+/* pb3b_adc1_ain3 */
+#define PB3B_ADC1_AIN3 \
+	SAM_PINMUX(b, 3, b, periph)
+
+/* pb3b_ptc_y9 */
+#define PB3B_PTC_Y9 \
+	SAM_PINMUX(b, 3, b, periph)
+
+/* pb3d_sercom5_pad1 */
+#define PB3D_SERCOM5_PAD1 \
+	SAM_PINMUX(b, 3, d, periph)
+
+/* pb3e_tc2_wo1 */
+#define PB3E_TC2_WO1 \
+	SAM_PINMUX(b, 3, e, periph)
+
+/* pb8_gpio */
+#define PB8_GPIO \
+	SAM_PINMUX(b, 8, gpio, gpio)
+
+/* pb8a_eic_extint8 */
+#define PB8A_EIC_EXTINT8 \
+	SAM_PINMUX(b, 8, a, periph)
+
+/* pb8b_adc0_ain2 */
+#define PB8B_ADC0_AIN2 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8b_adc1_ain4 */
+#define PB8B_ADC1_AIN4 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8b_ptc_y14 */
+#define PB8B_PTC_Y14 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8b_sdadc0_ainn1 */
+#define PB8B_SDADC0_AINN1 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8d_sercom4_pad0 */
+#define PB8D_SERCOM4_PAD0 \
+	SAM_PINMUX(b, 8, d, periph)
+
+/* pb8e_tc0_wo0 */
+#define PB8E_TC0_WO0 \
+	SAM_PINMUX(b, 8, e, periph)
+
+/* pb9_gpio */
+#define PB9_GPIO \
+	SAM_PINMUX(b, 9, gpio, gpio)
+
+/* pb9a_eic_extint9 */
+#define PB9A_EIC_EXTINT9 \
+	SAM_PINMUX(b, 9, a, periph)
+
+/* pb9b_adc0_ain3 */
+#define PB9B_ADC0_AIN3 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9b_adc1_ain5 */
+#define PB9B_ADC1_AIN5 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9b_ptc_y15 */
+#define PB9B_PTC_Y15 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9b_sdadc0_ainp1 */
+#define PB9B_SDADC0_AINP1 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9d_sercom4_pad1 */
+#define PB9D_SERCOM4_PAD1 \
+	SAM_PINMUX(b, 9, d, periph)
+
+/* pb9e_tc0_wo1 */
+#define PB9E_TC0_WO1 \
+	SAM_PINMUX(b, 9, e, periph)
+
+/* pb10_gpio */
+#define PB10_GPIO \
+	SAM_PINMUX(b, 10, gpio, gpio)
+
+/* pb10a_eic_extint10 */
+#define PB10A_EIC_EXTINT10 \
+	SAM_PINMUX(b, 10, a, periph)
+
+/* pb10d_sercom4_pad2 */
+#define PB10D_SERCOM4_PAD2 \
+	SAM_PINMUX(b, 10, d, periph)
+
+/* pb10e_tc1_wo0 */
+#define PB10E_TC1_WO0 \
+	SAM_PINMUX(b, 10, e, periph)
+
+/* pb10f_tcc0_wo4 */
+#define PB10F_TCC0_WO4 \
+	SAM_PINMUX(b, 10, f, periph)
+
+/* pb10g_can1_tx */
+#define PB10G_CAN1_TX \
+	SAM_PINMUX(b, 10, g, periph)
+
+/* pb10h_gclk_io4 */
+#define PB10H_GCLK_IO4 \
+	SAM_PINMUX(b, 10, h, periph)
+
+/* pb11_gpio */
+#define PB11_GPIO \
+	SAM_PINMUX(b, 11, gpio, gpio)
+
+/* pb11a_eic_extint11 */
+#define PB11A_EIC_EXTINT11 \
+	SAM_PINMUX(b, 11, a, periph)
+
+/* pb11d_sercom4_pad3 */
+#define PB11D_SERCOM4_PAD3 \
+	SAM_PINMUX(b, 11, d, periph)
+
+/* pb11e_tc1_wo1 */
+#define PB11E_TC1_WO1 \
+	SAM_PINMUX(b, 11, e, periph)
+
+/* pb11f_tcc0_wo5 */
+#define PB11F_TCC0_WO5 \
+	SAM_PINMUX(b, 11, f, periph)
+
+/* pb11g_can1_rx */
+#define PB11G_CAN1_RX \
+	SAM_PINMUX(b, 11, g, periph)
+
+/* pb11h_gclk_io5 */
+#define PB11H_GCLK_IO5 \
+	SAM_PINMUX(b, 11, h, periph)
+
+/* pb22_gpio */
+#define PB22_GPIO \
+	SAM_PINMUX(b, 22, gpio, gpio)
+
+/* pb22a_eic_extint6 */
+#define PB22A_EIC_EXTINT6 \
+	SAM_PINMUX(b, 22, a, periph)
+
+/* pb22d_sercom5_pad2 */
+#define PB22D_SERCOM5_PAD2 \
+	SAM_PINMUX(b, 22, d, periph)
+
+/* pb22e_tc3_wo0 */
+#define PB22E_TC3_WO0 \
+	SAM_PINMUX(b, 22, e, periph)
+
+/* pb22g_can0_tx */
+#define PB22G_CAN0_TX \
+	SAM_PINMUX(b, 22, g, periph)
+
+/* pb22h_gclk_io0 */
+#define PB22H_GCLK_IO0 \
+	SAM_PINMUX(b, 22, h, periph)
+
+/* pb23_gpio */
+#define PB23_GPIO \
+	SAM_PINMUX(b, 23, gpio, gpio)
+
+/* pb23a_eic_extint7 */
+#define PB23A_EIC_EXTINT7 \
+	SAM_PINMUX(b, 23, a, periph)
+
+/* pb23d_sercom5_pad3 */
+#define PB23D_SERCOM5_PAD3 \
+	SAM_PINMUX(b, 23, d, periph)
+
+/* pb23e_tc3_wo1 */
+#define PB23E_TC3_WO1 \
+	SAM_PINMUX(b, 23, e, periph)
+
+/* pb23g_can0_rx */
+#define PB23G_CAN0_RX \
+	SAM_PINMUX(b, 23, g, periph)
+
+/* pb23h_gclk_io1 */
+#define PB23H_GCLK_IO1 \
+	SAM_PINMUX(b, 23, h, periph)
diff --git a/include/dt-bindings/pinctrl/samc21j-pinctrl.h b/include/dt-bindings/pinctrl/samc21j-pinctrl.h
new file mode 100644
index 0000000..a7be1fb
--- /dev/null
+++ b/include/dt-bindings/pinctrl/samc21j-pinctrl.h
@@ -0,0 +1,1415 @@
+/*
+ * Autogenerated file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/atmel_sam_pinctrl.h>
+
+/* pa0_gpio */
+#define PA0_GPIO \
+	SAM_PINMUX(a, 0, gpio, gpio)
+
+/* pa0a_eic_extint0 */
+#define PA0A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 0, a, periph)
+
+/* pa0d_sercom1_pad0 */
+#define PA0D_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 0, d, periph)
+
+/* pa0e_tc2_wo0 */
+#define PA0E_TC2_WO0 \
+	SAM_PINMUX(a, 0, e, periph)
+
+/* pa0h_ac_cmp2 */
+#define PA0H_AC_CMP2 \
+	SAM_PINMUX(a, 0, h, periph)
+
+/* pa1_gpio */
+#define PA1_GPIO \
+	SAM_PINMUX(a, 1, gpio, gpio)
+
+/* pa1a_eic_extint1 */
+#define PA1A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 1, a, periph)
+
+/* pa1d_sercom1_pad1 */
+#define PA1D_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 1, d, periph)
+
+/* pa1e_tc2_wo1 */
+#define PA1E_TC2_WO1 \
+	SAM_PINMUX(a, 1, e, periph)
+
+/* pa1h_ac_cmp3 */
+#define PA1H_AC_CMP3 \
+	SAM_PINMUX(a, 1, h, periph)
+
+/* pa2_gpio */
+#define PA2_GPIO \
+	SAM_PINMUX(a, 2, gpio, gpio)
+
+/* pa2a_eic_extint2 */
+#define PA2A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 2, a, periph)
+
+/* pa2b_adc0_ain0 */
+#define PA2B_ADC0_AIN0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ac_ain4 */
+#define PA2B_AC_AIN4 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ptc_y0 */
+#define PA2B_PTC_Y0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_dac_vout */
+#define PA2B_DAC_VOUT \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa3_gpio */
+#define PA3_GPIO \
+	SAM_PINMUX(a, 3, gpio, gpio)
+
+/* pa3a_eic_extint3 */
+#define PA3A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 3, a, periph)
+
+/* pa3b_anaref_vrefa */
+#define PA3B_ANAREF_VREFA \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_adc0_ain5 */
+#define PA3B_ADC0_AIN5 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ac_ain4 */
+#define PA3B_AC_AIN4 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ptc_y1 */
+#define PA3B_PTC_Y1 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa4_gpio */
+#define PA4_GPIO \
+	SAM_PINMUX(a, 4, gpio, gpio)
+
+/* pa4a_eic_extint4 */
+#define PA4A_EIC_EXTINT4 \
+	SAM_PINMUX(a, 4, a, periph)
+
+/* pa4b_anaref_vrefb */
+#define PA4B_ANAREF_VREFB \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_adc0_ain4 */
+#define PA4B_ADC0_AIN4 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ac_ain0 */
+#define PA4B_AC_AIN0 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ptc_y2 */
+#define PA4B_PTC_Y2 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4d_sercom0_pad0 */
+#define PA4D_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 4, d, periph)
+
+/* pa4e_tcc0_wo0 */
+#define PA4E_TCC0_WO0 \
+	SAM_PINMUX(a, 4, e, periph)
+
+/* pa5_gpio */
+#define PA5_GPIO \
+	SAM_PINMUX(a, 5, gpio, gpio)
+
+/* pa5a_eic_extint5 */
+#define PA5A_EIC_EXTINT5 \
+	SAM_PINMUX(a, 5, a, periph)
+
+/* pa5b_adc0_ain5 */
+#define PA5B_ADC0_AIN5 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ac_ain1 */
+#define PA5B_AC_AIN1 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ptc_y3 */
+#define PA5B_PTC_Y3 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5d_sercom0_pad1 */
+#define PA5D_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 5, d, periph)
+
+/* pa5e_tcc0_wo1 */
+#define PA5E_TCC0_WO1 \
+	SAM_PINMUX(a, 5, e, periph)
+
+/* pa6_gpio */
+#define PA6_GPIO \
+	SAM_PINMUX(a, 6, gpio, gpio)
+
+/* pa6a_eic_extint6 */
+#define PA6A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 6, a, periph)
+
+/* pa6b_adc0_ain6 */
+#define PA6B_ADC0_AIN6 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ac_ain2 */
+#define PA6B_AC_AIN2 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ptc_y4 */
+#define PA6B_PTC_Y4 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_sdadc0_ainn0 */
+#define PA6B_SDADC0_AINN0 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6d_sercom0_pad2 */
+#define PA6D_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 6, d, periph)
+
+/* pa6e_tcc1_wo0 */
+#define PA6E_TCC1_WO0 \
+	SAM_PINMUX(a, 6, e, periph)
+
+/* pa7_gpio */
+#define PA7_GPIO \
+	SAM_PINMUX(a, 7, gpio, gpio)
+
+/* pa7a_eic_extint7 */
+#define PA7A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 7, a, periph)
+
+/* pa7b_adc0_ain7 */
+#define PA7B_ADC0_AIN7 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ac_ain3 */
+#define PA7B_AC_AIN3 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ptc_y5 */
+#define PA7B_PTC_Y5 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_sdadc0_ainp0 */
+#define PA7B_SDADC0_AINP0 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7d_sercom0_pad3 */
+#define PA7D_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 7, d, periph)
+
+/* pa7e_tcc1_wo1 */
+#define PA7E_TCC1_WO1 \
+	SAM_PINMUX(a, 7, e, periph)
+
+/* pa8_gpio */
+#define PA8_GPIO \
+	SAM_PINMUX(a, 8, gpio, gpio)
+
+/* pa8a_eic_nmi */
+#define PA8A_EIC_NMI \
+	SAM_PINMUX(a, 8, a, periph)
+
+/* pa8b_adc0_ain8 */
+#define PA8B_ADC0_AIN8 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8b_adc1_ain10 */
+#define PA8B_ADC1_AIN10 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8b_ptc_xy16 */
+#define PA8B_PTC_XY16 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8c_sercom0_pad0 */
+#define PA8C_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 8, c, periph)
+
+/* pa8d_sercom2_pad0 */
+#define PA8D_SERCOM2_PAD0 \
+	SAM_PINMUX(a, 8, d, periph)
+
+/* pa8e_tcc0_wo0 */
+#define PA8E_TCC0_WO0 \
+	SAM_PINMUX(a, 8, e, periph)
+
+/* pa8f_tcc1_wo2 */
+#define PA8F_TCC1_WO2 \
+	SAM_PINMUX(a, 8, f, periph)
+
+/* pa9_gpio */
+#define PA9_GPIO \
+	SAM_PINMUX(a, 9, gpio, gpio)
+
+/* pa9a_eic_extint9 */
+#define PA9A_EIC_EXTINT9 \
+	SAM_PINMUX(a, 9, a, periph)
+
+/* pa9b_adc0_ain9 */
+#define PA9B_ADC0_AIN9 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9b_adc1_ain11 */
+#define PA9B_ADC1_AIN11 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9b_ptc_x1 */
+#define PA9B_PTC_X1 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9c_sercom0_pad1 */
+#define PA9C_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 9, c, periph)
+
+/* pa9d_sercom2_pad1 */
+#define PA9D_SERCOM2_PAD1 \
+	SAM_PINMUX(a, 9, d, periph)
+
+/* pa9e_tcc0_wo1 */
+#define PA9E_TCC0_WO1 \
+	SAM_PINMUX(a, 9, e, periph)
+
+/* pa9f_tcc1_wo3 */
+#define PA9F_TCC1_WO3 \
+	SAM_PINMUX(a, 9, f, periph)
+
+/* pa10_gpio */
+#define PA10_GPIO \
+	SAM_PINMUX(a, 10, gpio, gpio)
+
+/* pa10a_eic_extint10 */
+#define PA10A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 10, a, periph)
+
+/* pa10b_adc0_ain10 */
+#define PA10B_ADC0_AIN10 \
+	SAM_PINMUX(a, 10, b, periph)
+
+/* pa10b_ptc_x2 */
+#define PA10B_PTC_X2 \
+	SAM_PINMUX(a, 10, b, periph)
+
+/* pa10c_sercom0_pad2 */
+#define PA10C_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 10, c, periph)
+
+/* pa10d_sercom2_pad2 */
+#define PA10D_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 10, d, periph)
+
+/* pa10e_tcc1_wo0 */
+#define PA10E_TCC1_WO0 \
+	SAM_PINMUX(a, 10, e, periph)
+
+/* pa10f_tcc0_wo2 */
+#define PA10F_TCC0_WO2 \
+	SAM_PINMUX(a, 10, f, periph)
+
+/* pa10h_gclk_io4 */
+#define PA10H_GCLK_IO4 \
+	SAM_PINMUX(a, 10, h, periph)
+
+/* pa11_gpio */
+#define PA11_GPIO \
+	SAM_PINMUX(a, 11, gpio, gpio)
+
+/* pa11a_eic_extint11 */
+#define PA11A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 11, a, periph)
+
+/* pa11b_adc0_ain11 */
+#define PA11B_ADC0_AIN11 \
+	SAM_PINMUX(a, 11, b, periph)
+
+/* pa11b_ptc_x3 */
+#define PA11B_PTC_X3 \
+	SAM_PINMUX(a, 11, b, periph)
+
+/* pa11c_sercom0_pad3 */
+#define PA11C_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 11, c, periph)
+
+/* pa11d_sercom2_pad3 */
+#define PA11D_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 11, d, periph)
+
+/* pa11e_tcc1_wo1 */
+#define PA11E_TCC1_WO1 \
+	SAM_PINMUX(a, 11, e, periph)
+
+/* pa11f_tcc0_wo3 */
+#define PA11F_TCC0_WO3 \
+	SAM_PINMUX(a, 11, f, periph)
+
+/* pa11h_gclk_io5 */
+#define PA11H_GCLK_IO5 \
+	SAM_PINMUX(a, 11, h, periph)
+
+/* pa12_gpio */
+#define PA12_GPIO \
+	SAM_PINMUX(a, 12, gpio, gpio)
+
+/* pa12a_eic_extint12 */
+#define PA12A_EIC_EXTINT12 \
+	SAM_PINMUX(a, 12, a, periph)
+
+/* pa12c_sercom2_pad0 */
+#define PA12C_SERCOM2_PAD0 \
+	SAM_PINMUX(a, 12, c, periph)
+
+/* pa12d_sercom4_pad0 */
+#define PA12D_SERCOM4_PAD0 \
+	SAM_PINMUX(a, 12, d, periph)
+
+/* pa12e_tcc2_wo0 */
+#define PA12E_TCC2_WO0 \
+	SAM_PINMUX(a, 12, e, periph)
+
+/* pa12f_tcc0_wo6 */
+#define PA12F_TCC0_WO6 \
+	SAM_PINMUX(a, 12, f, periph)
+
+/* pa12h_ac_cmp0 */
+#define PA12H_AC_CMP0 \
+	SAM_PINMUX(a, 12, h, periph)
+
+/* pa13_gpio */
+#define PA13_GPIO \
+	SAM_PINMUX(a, 13, gpio, gpio)
+
+/* pa13a_eic_extint13 */
+#define PA13A_EIC_EXTINT13 \
+	SAM_PINMUX(a, 13, a, periph)
+
+/* pa13c_sercom2_pad1 */
+#define PA13C_SERCOM2_PAD1 \
+	SAM_PINMUX(a, 13, c, periph)
+
+/* pa13d_sercom4_pad1 */
+#define PA13D_SERCOM4_PAD1 \
+	SAM_PINMUX(a, 13, d, periph)
+
+/* pa13e_tcc2_wo1 */
+#define PA13E_TCC2_WO1 \
+	SAM_PINMUX(a, 13, e, periph)
+
+/* pa13f_tcc0_wo7 */
+#define PA13F_TCC0_WO7 \
+	SAM_PINMUX(a, 13, f, periph)
+
+/* pa13h_ac_cmp1 */
+#define PA13H_AC_CMP1 \
+	SAM_PINMUX(a, 13, h, periph)
+
+/* pa14_gpio */
+#define PA14_GPIO \
+	SAM_PINMUX(a, 14, gpio, gpio)
+
+/* pa14a_eic_extint14 */
+#define PA14A_EIC_EXTINT14 \
+	SAM_PINMUX(a, 14, a, periph)
+
+/* pa14c_sercom2_pad2 */
+#define PA14C_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 14, c, periph)
+
+/* pa14d_sercom4_pad2 */
+#define PA14D_SERCOM4_PAD2 \
+	SAM_PINMUX(a, 14, d, periph)
+
+/* pa14e_tc4_wo0 */
+#define PA14E_TC4_WO0 \
+	SAM_PINMUX(a, 14, e, periph)
+
+/* pa14f_tcc0_wo4 */
+#define PA14F_TCC0_WO4 \
+	SAM_PINMUX(a, 14, f, periph)
+
+/* pa14h_gclk_io0 */
+#define PA14H_GCLK_IO0 \
+	SAM_PINMUX(a, 14, h, periph)
+
+/* pa15_gpio */
+#define PA15_GPIO \
+	SAM_PINMUX(a, 15, gpio, gpio)
+
+/* pa15a_eic_extint15 */
+#define PA15A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 15, a, periph)
+
+/* pa15c_sercom2_pad3 */
+#define PA15C_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 15, c, periph)
+
+/* pa15d_sercom4_pad3 */
+#define PA15D_SERCOM4_PAD3 \
+	SAM_PINMUX(a, 15, d, periph)
+
+/* pa15e_tc4_wo1 */
+#define PA15E_TC4_WO1 \
+	SAM_PINMUX(a, 15, e, periph)
+
+/* pa15f_tcc0_wo5 */
+#define PA15F_TCC0_WO5 \
+	SAM_PINMUX(a, 15, f, periph)
+
+/* pa15h_gclk_io1 */
+#define PA15H_GCLK_IO1 \
+	SAM_PINMUX(a, 15, h, periph)
+
+/* pa16_gpio */
+#define PA16_GPIO \
+	SAM_PINMUX(a, 16, gpio, gpio)
+
+/* pa16a_eic_extint0 */
+#define PA16A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 16, a, periph)
+
+/* pa16b_ptc_x4 */
+#define PA16B_PTC_X4 \
+	SAM_PINMUX(a, 16, b, periph)
+
+/* pa16c_sercom1_pad0 */
+#define PA16C_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 16, c, periph)
+
+/* pa16d_sercom3_pad0 */
+#define PA16D_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 16, d, periph)
+
+/* pa16e_tcc2_wo0 */
+#define PA16E_TCC2_WO0 \
+	SAM_PINMUX(a, 16, e, periph)
+
+/* pa16f_tcc0_wo6 */
+#define PA16F_TCC0_WO6 \
+	SAM_PINMUX(a, 16, f, periph)
+
+/* pa16h_gclk_io2 */
+#define PA16H_GCLK_IO2 \
+	SAM_PINMUX(a, 16, h, periph)
+
+/* pa17_gpio */
+#define PA17_GPIO \
+	SAM_PINMUX(a, 17, gpio, gpio)
+
+/* pa17a_eic_extint1 */
+#define PA17A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 17, a, periph)
+
+/* pa17b_ptc_x5 */
+#define PA17B_PTC_X5 \
+	SAM_PINMUX(a, 17, b, periph)
+
+/* pa17c_sercom1_pad1 */
+#define PA17C_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 17, c, periph)
+
+/* pa17d_sercom3_pad1 */
+#define PA17D_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 17, d, periph)
+
+/* pa17e_tcc2_wo1 */
+#define PA17E_TCC2_WO1 \
+	SAM_PINMUX(a, 17, e, periph)
+
+/* pa17f_tcc0_wo7 */
+#define PA17F_TCC0_WO7 \
+	SAM_PINMUX(a, 17, f, periph)
+
+/* pa17h_gclk_io3 */
+#define PA17H_GCLK_IO3 \
+	SAM_PINMUX(a, 17, h, periph)
+
+/* pa18_gpio */
+#define PA18_GPIO \
+	SAM_PINMUX(a, 18, gpio, gpio)
+
+/* pa18a_eic_extint2 */
+#define PA18A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 18, a, periph)
+
+/* pa18b_ptc_x6 */
+#define PA18B_PTC_X6 \
+	SAM_PINMUX(a, 18, b, periph)
+
+/* pa18c_sercom1_pad2 */
+#define PA18C_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 18, c, periph)
+
+/* pa18d_sercom3_pad2 */
+#define PA18D_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 18, d, periph)
+
+/* pa18e_tc4_wo0 */
+#define PA18E_TC4_WO0 \
+	SAM_PINMUX(a, 18, e, periph)
+
+/* pa18f_tcc0_wo2 */
+#define PA18F_TCC0_WO2 \
+	SAM_PINMUX(a, 18, f, periph)
+
+/* pa18h_ac_cmp0 */
+#define PA18H_AC_CMP0 \
+	SAM_PINMUX(a, 18, h, periph)
+
+/* pa19_gpio */
+#define PA19_GPIO \
+	SAM_PINMUX(a, 19, gpio, gpio)
+
+/* pa19a_eic_extint3 */
+#define PA19A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 19, a, periph)
+
+/* pa19b_ptc_x7 */
+#define PA19B_PTC_X7 \
+	SAM_PINMUX(a, 19, b, periph)
+
+/* pa19c_sercom1_pad3 */
+#define PA19C_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 19, c, periph)
+
+/* pa19d_sercom3_pad3 */
+#define PA19D_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 19, d, periph)
+
+/* pa19e_tc4_wo1 */
+#define PA19E_TC4_WO1 \
+	SAM_PINMUX(a, 19, e, periph)
+
+/* pa19f_tcc0_wo3 */
+#define PA19F_TCC0_WO3 \
+	SAM_PINMUX(a, 19, f, periph)
+
+/* pa19h_ac_cmp1 */
+#define PA19H_AC_CMP1 \
+	SAM_PINMUX(a, 19, h, periph)
+
+/* pa20_gpio */
+#define PA20_GPIO \
+	SAM_PINMUX(a, 20, gpio, gpio)
+
+/* pa20a_eic_extint4 */
+#define PA20A_EIC_EXTINT4 \
+	SAM_PINMUX(a, 20, a, periph)
+
+/* pa20b_ptc_x8 */
+#define PA20B_PTC_X8 \
+	SAM_PINMUX(a, 20, b, periph)
+
+/* pa20c_sercom5_pad2 */
+#define PA20C_SERCOM5_PAD2 \
+	SAM_PINMUX(a, 20, c, periph)
+
+/* pa20d_sercom3_pad2 */
+#define PA20D_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 20, d, periph)
+
+/* pa20e_tc3_wo0 */
+#define PA20E_TC3_WO0 \
+	SAM_PINMUX(a, 20, e, periph)
+
+/* pa20f_tcc0_wo6 */
+#define PA20F_TCC0_WO6 \
+	SAM_PINMUX(a, 20, f, periph)
+
+/* pa20h_gclk_io4 */
+#define PA20H_GCLK_IO4 \
+	SAM_PINMUX(a, 20, h, periph)
+
+/* pa21_gpio */
+#define PA21_GPIO \
+	SAM_PINMUX(a, 21, gpio, gpio)
+
+/* pa21a_eic_extint5 */
+#define PA21A_EIC_EXTINT5 \
+	SAM_PINMUX(a, 21, a, periph)
+
+/* pa21b_ptc_x9 */
+#define PA21B_PTC_X9 \
+	SAM_PINMUX(a, 21, b, periph)
+
+/* pa21c_sercom5_pad3 */
+#define PA21C_SERCOM5_PAD3 \
+	SAM_PINMUX(a, 21, c, periph)
+
+/* pa21d_sercom3_pad3 */
+#define PA21D_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 21, d, periph)
+
+/* pa21e_tc3_wo1 */
+#define PA21E_TC3_WO1 \
+	SAM_PINMUX(a, 21, e, periph)
+
+/* pa21f_tcc0_wo7 */
+#define PA21F_TCC0_WO7 \
+	SAM_PINMUX(a, 21, f, periph)
+
+/* pa21h_gclk_io5 */
+#define PA21H_GCLK_IO5 \
+	SAM_PINMUX(a, 21, h, periph)
+
+/* pa22_gpio */
+#define PA22_GPIO \
+	SAM_PINMUX(a, 22, gpio, gpio)
+
+/* pa22a_eic_extint6 */
+#define PA22A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 22, a, periph)
+
+/* pa22b_ptc_x10 */
+#define PA22B_PTC_X10 \
+	SAM_PINMUX(a, 22, b, periph)
+
+/* pa22c_sercom3_pad0 */
+#define PA22C_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 22, c, periph)
+
+/* pa22d_sercom5_pad0 */
+#define PA22D_SERCOM5_PAD0 \
+	SAM_PINMUX(a, 22, d, periph)
+
+/* pa22e_tc0_wo0 */
+#define PA22E_TC0_WO0 \
+	SAM_PINMUX(a, 22, e, periph)
+
+/* pa22f_tcc0_wo4 */
+#define PA22F_TCC0_WO4 \
+	SAM_PINMUX(a, 22, f, periph)
+
+/* pa22h_gclk_io6 */
+#define PA22H_GCLK_IO6 \
+	SAM_PINMUX(a, 22, h, periph)
+
+/* pa23_gpio */
+#define PA23_GPIO \
+	SAM_PINMUX(a, 23, gpio, gpio)
+
+/* pa23a_eic_extint7 */
+#define PA23A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 23, a, periph)
+
+/* pa23b_ptc_x11 */
+#define PA23B_PTC_X11 \
+	SAM_PINMUX(a, 23, b, periph)
+
+/* pa23c_sercom3_pad1 */
+#define PA23C_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 23, c, periph)
+
+/* pa23d_sercom5_pad1 */
+#define PA23D_SERCOM5_PAD1 \
+	SAM_PINMUX(a, 23, d, periph)
+
+/* pa23e_tc0_wo1 */
+#define PA23E_TC0_WO1 \
+	SAM_PINMUX(a, 23, e, periph)
+
+/* pa23f_tcc0_wo5 */
+#define PA23F_TCC0_WO5 \
+	SAM_PINMUX(a, 23, f, periph)
+
+/* pa23h_gclk_io7 */
+#define PA23H_GCLK_IO7 \
+	SAM_PINMUX(a, 23, h, periph)
+
+/* pa24_gpio */
+#define PA24_GPIO \
+	SAM_PINMUX(a, 24, gpio, gpio)
+
+/* pa24a_eic_extint12 */
+#define PA24A_EIC_EXTINT12 \
+	SAM_PINMUX(a, 24, a, periph)
+
+/* pa24c_sercom3_pad2 */
+#define PA24C_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 24, c, periph)
+
+/* pa24d_sercom5_pad2 */
+#define PA24D_SERCOM5_PAD2 \
+	SAM_PINMUX(a, 24, d, periph)
+
+/* pa24e_tc1_wo0 */
+#define PA24E_TC1_WO0 \
+	SAM_PINMUX(a, 24, e, periph)
+
+/* pa24f_tcc1_wo2 */
+#define PA24F_TCC1_WO2 \
+	SAM_PINMUX(a, 24, f, periph)
+
+/* pa24g_can0_tx */
+#define PA24G_CAN0_TX \
+	SAM_PINMUX(a, 24, g, periph)
+
+/* pa24h_ac_cmp2 */
+#define PA24H_AC_CMP2 \
+	SAM_PINMUX(a, 24, h, periph)
+
+/* pa25_gpio */
+#define PA25_GPIO \
+	SAM_PINMUX(a, 25, gpio, gpio)
+
+/* pa25a_eic_extint13 */
+#define PA25A_EIC_EXTINT13 \
+	SAM_PINMUX(a, 25, a, periph)
+
+/* pa25c_sercom3_pad3 */
+#define PA25C_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 25, c, periph)
+
+/* pa25d_sercom5_pad3 */
+#define PA25D_SERCOM5_PAD3 \
+	SAM_PINMUX(a, 25, d, periph)
+
+/* pa25e_tc1_wo1 */
+#define PA25E_TC1_WO1 \
+	SAM_PINMUX(a, 25, e, periph)
+
+/* pa25f_tcc1_wo3 */
+#define PA25F_TCC1_WO3 \
+	SAM_PINMUX(a, 25, f, periph)
+
+/* pa25g_can0_rx */
+#define PA25G_CAN0_RX \
+	SAM_PINMUX(a, 25, g, periph)
+
+/* pa25h_ac_cmp3 */
+#define PA25H_AC_CMP3 \
+	SAM_PINMUX(a, 25, h, periph)
+
+/* pa27_gpio */
+#define PA27_GPIO \
+	SAM_PINMUX(a, 27, gpio, gpio)
+
+/* pa27a_eic_extint15 */
+#define PA27A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 27, a, periph)
+
+/* pa27h_gclk_io0 */
+#define PA27H_GCLK_IO0 \
+	SAM_PINMUX(a, 27, h, periph)
+
+/* pa28_gpio */
+#define PA28_GPIO \
+	SAM_PINMUX(a, 28, gpio, gpio)
+
+/* pa28a_eic_extint8 */
+#define PA28A_EIC_EXTINT8 \
+	SAM_PINMUX(a, 28, a, periph)
+
+/* pa28h_gclk_io0 */
+#define PA28H_GCLK_IO0 \
+	SAM_PINMUX(a, 28, h, periph)
+
+/* pa30_gpio */
+#define PA30_GPIO \
+	SAM_PINMUX(a, 30, gpio, gpio)
+
+/* pa30a_eic_extint10 */
+#define PA30A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 30, a, periph)
+
+/* pa30d_sercom1_pad2 */
+#define PA30D_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 30, d, periph)
+
+/* pa30e_tcc1_wo0 */
+#define PA30E_TCC1_WO0 \
+	SAM_PINMUX(a, 30, e, periph)
+
+/* pa30g_swd_clk */
+#define PA30G_SWD_CLK \
+	SAM_PINMUX(a, 30, g, periph)
+
+/* pa30h_gclk_io0 */
+#define PA30H_GCLK_IO0 \
+	SAM_PINMUX(a, 30, h, periph)
+
+/* pa31_gpio */
+#define PA31_GPIO \
+	SAM_PINMUX(a, 31, gpio, gpio)
+
+/* pa31a_eic_extint11 */
+#define PA31A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 31, a, periph)
+
+/* pa31d_sercom1_pad3 */
+#define PA31D_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 31, d, periph)
+
+/* pa31e_tcc1_wo1 */
+#define PA31E_TCC1_WO1 \
+	SAM_PINMUX(a, 31, e, periph)
+
+/* pa31g_swd_io */
+#define PA31G_SWD_IO \
+	SAM_PINMUX(a, 31, g, periph)
+
+/* pb0_gpio */
+#define PB0_GPIO \
+	SAM_PINMUX(b, 0, gpio, gpio)
+
+/* pb0a_eic_extint0 */
+#define PB0A_EIC_EXTINT0 \
+	SAM_PINMUX(b, 0, a, periph)
+
+/* pb0b_adc1_ain0 */
+#define PB0B_ADC1_AIN0 \
+	SAM_PINMUX(b, 0, b, periph)
+
+/* pb0b_ptc_y6 */
+#define PB0B_PTC_Y6 \
+	SAM_PINMUX(b, 0, b, periph)
+
+/* pb0d_sercom5_pad2 */
+#define PB0D_SERCOM5_PAD2 \
+	SAM_PINMUX(b, 0, d, periph)
+
+/* pb0e_tc3_wo0 */
+#define PB0E_TC3_WO0 \
+	SAM_PINMUX(b, 0, e, periph)
+
+/* pb1_gpio */
+#define PB1_GPIO \
+	SAM_PINMUX(b, 1, gpio, gpio)
+
+/* pb1a_eic_extint1 */
+#define PB1A_EIC_EXTINT1 \
+	SAM_PINMUX(b, 1, a, periph)
+
+/* pb1b_adc1_ain1 */
+#define PB1B_ADC1_AIN1 \
+	SAM_PINMUX(b, 1, b, periph)
+
+/* pb1b_ptc_y7 */
+#define PB1B_PTC_Y7 \
+	SAM_PINMUX(b, 1, b, periph)
+
+/* pb1d_sercom5_pad3 */
+#define PB1D_SERCOM5_PAD3 \
+	SAM_PINMUX(b, 1, d, periph)
+
+/* pb1e_tc3_wo1 */
+#define PB1E_TC3_WO1 \
+	SAM_PINMUX(b, 1, e, periph)
+
+/* pb2_gpio */
+#define PB2_GPIO \
+	SAM_PINMUX(b, 2, gpio, gpio)
+
+/* pb2a_eic_extint2 */
+#define PB2A_EIC_EXTINT2 \
+	SAM_PINMUX(b, 2, a, periph)
+
+/* pb2b_adc1_ain2 */
+#define PB2B_ADC1_AIN2 \
+	SAM_PINMUX(b, 2, b, periph)
+
+/* pb2b_ptc_y8 */
+#define PB2B_PTC_Y8 \
+	SAM_PINMUX(b, 2, b, periph)
+
+/* pb2d_sercom5_pad0 */
+#define PB2D_SERCOM5_PAD0 \
+	SAM_PINMUX(b, 2, d, periph)
+
+/* pb2e_tc2_wo0 */
+#define PB2E_TC2_WO0 \
+	SAM_PINMUX(b, 2, e, periph)
+
+/* pb3_gpio */
+#define PB3_GPIO \
+	SAM_PINMUX(b, 3, gpio, gpio)
+
+/* pb3a_eic_extint3 */
+#define PB3A_EIC_EXTINT3 \
+	SAM_PINMUX(b, 3, a, periph)
+
+/* pb3b_adc1_ain3 */
+#define PB3B_ADC1_AIN3 \
+	SAM_PINMUX(b, 3, b, periph)
+
+/* pb3b_ptc_y9 */
+#define PB3B_PTC_Y9 \
+	SAM_PINMUX(b, 3, b, periph)
+
+/* pb3d_sercom5_pad1 */
+#define PB3D_SERCOM5_PAD1 \
+	SAM_PINMUX(b, 3, d, periph)
+
+/* pb3e_tc2_wo1 */
+#define PB3E_TC2_WO1 \
+	SAM_PINMUX(b, 3, e, periph)
+
+/* pb4_gpio */
+#define PB4_GPIO \
+	SAM_PINMUX(b, 4, gpio, gpio)
+
+/* pb4a_eic_extint4 */
+#define PB4A_EIC_EXTINT4 \
+	SAM_PINMUX(b, 4, a, periph)
+
+/* pb4b_adc0_ain6 */
+#define PB4B_ADC0_AIN6 \
+	SAM_PINMUX(b, 4, b, periph)
+
+/* pb4b_ptc_y10 */
+#define PB4B_PTC_Y10 \
+	SAM_PINMUX(b, 4, b, periph)
+
+/* pb5_gpio */
+#define PB5_GPIO \
+	SAM_PINMUX(b, 5, gpio, gpio)
+
+/* pb5a_eic_extint5 */
+#define PB5A_EIC_EXTINT5 \
+	SAM_PINMUX(b, 5, a, periph)
+
+/* pb5b_adc0_ain7 */
+#define PB5B_ADC0_AIN7 \
+	SAM_PINMUX(b, 5, b, periph)
+
+/* pb5b_ac_ain6 */
+#define PB5B_AC_AIN6 \
+	SAM_PINMUX(b, 5, b, periph)
+
+/* pb5b_ptc_y11 */
+#define PB5B_PTC_Y11 \
+	SAM_PINMUX(b, 5, b, periph)
+
+/* pb6_gpio */
+#define PB6_GPIO \
+	SAM_PINMUX(b, 6, gpio, gpio)
+
+/* pb6a_eic_extint6 */
+#define PB6A_EIC_EXTINT6 \
+	SAM_PINMUX(b, 6, a, periph)
+
+/* pb6b_adc0_ain8 */
+#define PB6B_ADC0_AIN8 \
+	SAM_PINMUX(b, 6, b, periph)
+
+/* pb6b_ac_ain7 */
+#define PB6B_AC_AIN7 \
+	SAM_PINMUX(b, 6, b, periph)
+
+/* pb6b_ptc_y12 */
+#define PB6B_PTC_Y12 \
+	SAM_PINMUX(b, 6, b, periph)
+
+/* pb6b_sdadc0_ainn2 */
+#define PB6B_SDADC0_AINN2 \
+	SAM_PINMUX(b, 6, b, periph)
+
+/* pb7_gpio */
+#define PB7_GPIO \
+	SAM_PINMUX(b, 7, gpio, gpio)
+
+/* pb7a_eic_extint7 */
+#define PB7A_EIC_EXTINT7 \
+	SAM_PINMUX(b, 7, a, periph)
+
+/* pb7b_adc0_ain9 */
+#define PB7B_ADC0_AIN9 \
+	SAM_PINMUX(b, 7, b, periph)
+
+/* pb7b_ptc_y13 */
+#define PB7B_PTC_Y13 \
+	SAM_PINMUX(b, 7, b, periph)
+
+/* pb7b_sdadc0_ainp2 */
+#define PB7B_SDADC0_AINP2 \
+	SAM_PINMUX(b, 7, b, periph)
+
+/* pb8_gpio */
+#define PB8_GPIO \
+	SAM_PINMUX(b, 8, gpio, gpio)
+
+/* pb8a_eic_extint8 */
+#define PB8A_EIC_EXTINT8 \
+	SAM_PINMUX(b, 8, a, periph)
+
+/* pb8b_adc0_ain2 */
+#define PB8B_ADC0_AIN2 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8b_adc1_ain4 */
+#define PB8B_ADC1_AIN4 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8b_ptc_y14 */
+#define PB8B_PTC_Y14 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8b_sdadc0_ainn1 */
+#define PB8B_SDADC0_AINN1 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8d_sercom4_pad0 */
+#define PB8D_SERCOM4_PAD0 \
+	SAM_PINMUX(b, 8, d, periph)
+
+/* pb8e_tc0_wo0 */
+#define PB8E_TC0_WO0 \
+	SAM_PINMUX(b, 8, e, periph)
+
+/* pb9_gpio */
+#define PB9_GPIO \
+	SAM_PINMUX(b, 9, gpio, gpio)
+
+/* pb9a_eic_extint9 */
+#define PB9A_EIC_EXTINT9 \
+	SAM_PINMUX(b, 9, a, periph)
+
+/* pb9b_adc0_ain3 */
+#define PB9B_ADC0_AIN3 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9b_adc1_ain5 */
+#define PB9B_ADC1_AIN5 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9b_ptc_y15 */
+#define PB9B_PTC_Y15 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9b_sdadc0_ainp1 */
+#define PB9B_SDADC0_AINP1 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9d_sercom4_pad1 */
+#define PB9D_SERCOM4_PAD1 \
+	SAM_PINMUX(b, 9, d, periph)
+
+/* pb9e_tc0_wo1 */
+#define PB9E_TC0_WO1 \
+	SAM_PINMUX(b, 9, e, periph)
+
+/* pb10_gpio */
+#define PB10_GPIO \
+	SAM_PINMUX(b, 10, gpio, gpio)
+
+/* pb10a_eic_extint10 */
+#define PB10A_EIC_EXTINT10 \
+	SAM_PINMUX(b, 10, a, periph)
+
+/* pb10d_sercom4_pad2 */
+#define PB10D_SERCOM4_PAD2 \
+	SAM_PINMUX(b, 10, d, periph)
+
+/* pb10e_tc1_wo0 */
+#define PB10E_TC1_WO0 \
+	SAM_PINMUX(b, 10, e, periph)
+
+/* pb10f_tcc0_wo4 */
+#define PB10F_TCC0_WO4 \
+	SAM_PINMUX(b, 10, f, periph)
+
+/* pb10g_can1_tx */
+#define PB10G_CAN1_TX \
+	SAM_PINMUX(b, 10, g, periph)
+
+/* pb10h_gclk_io4 */
+#define PB10H_GCLK_IO4 \
+	SAM_PINMUX(b, 10, h, periph)
+
+/* pb11_gpio */
+#define PB11_GPIO \
+	SAM_PINMUX(b, 11, gpio, gpio)
+
+/* pb11a_eic_extint11 */
+#define PB11A_EIC_EXTINT11 \
+	SAM_PINMUX(b, 11, a, periph)
+
+/* pb11d_sercom4_pad3 */
+#define PB11D_SERCOM4_PAD3 \
+	SAM_PINMUX(b, 11, d, periph)
+
+/* pb11e_tc1_wo1 */
+#define PB11E_TC1_WO1 \
+	SAM_PINMUX(b, 11, e, periph)
+
+/* pb11f_tcc0_wo5 */
+#define PB11F_TCC0_WO5 \
+	SAM_PINMUX(b, 11, f, periph)
+
+/* pb11g_can1_rx */
+#define PB11G_CAN1_RX \
+	SAM_PINMUX(b, 11, g, periph)
+
+/* pb11h_gclk_io5 */
+#define PB11H_GCLK_IO5 \
+	SAM_PINMUX(b, 11, h, periph)
+
+/* pb12_gpio */
+#define PB12_GPIO \
+	SAM_PINMUX(b, 12, gpio, gpio)
+
+/* pb12a_eic_extint12 */
+#define PB12A_EIC_EXTINT12 \
+	SAM_PINMUX(b, 12, a, periph)
+
+/* pb12b_ptc_x12 */
+#define PB12B_PTC_X12 \
+	SAM_PINMUX(b, 12, b, periph)
+
+/* pb12c_sercom4_pad0 */
+#define PB12C_SERCOM4_PAD0 \
+	SAM_PINMUX(b, 12, c, periph)
+
+/* pb12e_tc0_wo0 */
+#define PB12E_TC0_WO0 \
+	SAM_PINMUX(b, 12, e, periph)
+
+/* pb12f_tcc0_wo6 */
+#define PB12F_TCC0_WO6 \
+	SAM_PINMUX(b, 12, f, periph)
+
+/* pb12h_gclk_io6 */
+#define PB12H_GCLK_IO6 \
+	SAM_PINMUX(b, 12, h, periph)
+
+/* pb13_gpio */
+#define PB13_GPIO \
+	SAM_PINMUX(b, 13, gpio, gpio)
+
+/* pb13a_eic_extint13 */
+#define PB13A_EIC_EXTINT13 \
+	SAM_PINMUX(b, 13, a, periph)
+
+/* pb13b_ptc_x13 */
+#define PB13B_PTC_X13 \
+	SAM_PINMUX(b, 13, b, periph)
+
+/* pb13c_sercom4_pad1 */
+#define PB13C_SERCOM4_PAD1 \
+	SAM_PINMUX(b, 13, c, periph)
+
+/* pb13e_tc0_wo1 */
+#define PB13E_TC0_WO1 \
+	SAM_PINMUX(b, 13, e, periph)
+
+/* pb13f_tcc0_wo7 */
+#define PB13F_TCC0_WO7 \
+	SAM_PINMUX(b, 13, f, periph)
+
+/* pb13h_gclk_io7 */
+#define PB13H_GCLK_IO7 \
+	SAM_PINMUX(b, 13, h, periph)
+
+/* pb14_gpio */
+#define PB14_GPIO \
+	SAM_PINMUX(b, 14, gpio, gpio)
+
+/* pb14a_eic_extint14 */
+#define PB14A_EIC_EXTINT14 \
+	SAM_PINMUX(b, 14, a, periph)
+
+/* pb14b_ptc_x14 */
+#define PB14B_PTC_X14 \
+	SAM_PINMUX(b, 14, b, periph)
+
+/* pb14c_sercom4_pad2 */
+#define PB14C_SERCOM4_PAD2 \
+	SAM_PINMUX(b, 14, c, periph)
+
+/* pb14e_tc1_wo0 */
+#define PB14E_TC1_WO0 \
+	SAM_PINMUX(b, 14, e, periph)
+
+/* pb14g_can1_tx */
+#define PB14G_CAN1_TX \
+	SAM_PINMUX(b, 14, g, periph)
+
+/* pb14h_gclk_io0 */
+#define PB14H_GCLK_IO0 \
+	SAM_PINMUX(b, 14, h, periph)
+
+/* pb15_gpio */
+#define PB15_GPIO \
+	SAM_PINMUX(b, 15, gpio, gpio)
+
+/* pb15a_eic_extint15 */
+#define PB15A_EIC_EXTINT15 \
+	SAM_PINMUX(b, 15, a, periph)
+
+/* pb15b_ptc_x15 */
+#define PB15B_PTC_X15 \
+	SAM_PINMUX(b, 15, b, periph)
+
+/* pb15c_sercom4_pad3 */
+#define PB15C_SERCOM4_PAD3 \
+	SAM_PINMUX(b, 15, c, periph)
+
+/* pb15e_tc1_wo1 */
+#define PB15E_TC1_WO1 \
+	SAM_PINMUX(b, 15, e, periph)
+
+/* pb15g_can1_rx */
+#define PB15G_CAN1_RX \
+	SAM_PINMUX(b, 15, g, periph)
+
+/* pb15h_gclk_io1 */
+#define PB15H_GCLK_IO1 \
+	SAM_PINMUX(b, 15, h, periph)
+
+/* pb16_gpio */
+#define PB16_GPIO \
+	SAM_PINMUX(b, 16, gpio, gpio)
+
+/* pb16a_eic_extint0 */
+#define PB16A_EIC_EXTINT0 \
+	SAM_PINMUX(b, 16, a, periph)
+
+/* pb16c_sercom5_pad0 */
+#define PB16C_SERCOM5_PAD0 \
+	SAM_PINMUX(b, 16, c, periph)
+
+/* pb16e_tc2_wo0 */
+#define PB16E_TC2_WO0 \
+	SAM_PINMUX(b, 16, e, periph)
+
+/* pb16f_tcc0_wo4 */
+#define PB16F_TCC0_WO4 \
+	SAM_PINMUX(b, 16, f, periph)
+
+/* pb16h_gclk_io2 */
+#define PB16H_GCLK_IO2 \
+	SAM_PINMUX(b, 16, h, periph)
+
+/* pb17_gpio */
+#define PB17_GPIO \
+	SAM_PINMUX(b, 17, gpio, gpio)
+
+/* pb17a_eic_extint1 */
+#define PB17A_EIC_EXTINT1 \
+	SAM_PINMUX(b, 17, a, periph)
+
+/* pb17c_sercom5_pad1 */
+#define PB17C_SERCOM5_PAD1 \
+	SAM_PINMUX(b, 17, c, periph)
+
+/* pb17e_tc2_wo1 */
+#define PB17E_TC2_WO1 \
+	SAM_PINMUX(b, 17, e, periph)
+
+/* pb17f_tcc0_wo5 */
+#define PB17F_TCC0_WO5 \
+	SAM_PINMUX(b, 17, f, periph)
+
+/* pb17h_gclk_io3 */
+#define PB17H_GCLK_IO3 \
+	SAM_PINMUX(b, 17, h, periph)
+
+/* pb22_gpio */
+#define PB22_GPIO \
+	SAM_PINMUX(b, 22, gpio, gpio)
+
+/* pb22a_eic_extint6 */
+#define PB22A_EIC_EXTINT6 \
+	SAM_PINMUX(b, 22, a, periph)
+
+/* pb22d_sercom5_pad2 */
+#define PB22D_SERCOM5_PAD2 \
+	SAM_PINMUX(b, 22, d, periph)
+
+/* pb22e_tc3_wo0 */
+#define PB22E_TC3_WO0 \
+	SAM_PINMUX(b, 22, e, periph)
+
+/* pb22g_can0_tx */
+#define PB22G_CAN0_TX \
+	SAM_PINMUX(b, 22, g, periph)
+
+/* pb22h_gclk_io0 */
+#define PB22H_GCLK_IO0 \
+	SAM_PINMUX(b, 22, h, periph)
+
+/* pb23_gpio */
+#define PB23_GPIO \
+	SAM_PINMUX(b, 23, gpio, gpio)
+
+/* pb23a_eic_extint7 */
+#define PB23A_EIC_EXTINT7 \
+	SAM_PINMUX(b, 23, a, periph)
+
+/* pb23d_sercom5_pad3 */
+#define PB23D_SERCOM5_PAD3 \
+	SAM_PINMUX(b, 23, d, periph)
+
+/* pb23e_tc3_wo1 */
+#define PB23E_TC3_WO1 \
+	SAM_PINMUX(b, 23, e, periph)
+
+/* pb23g_can0_rx */
+#define PB23G_CAN0_RX \
+	SAM_PINMUX(b, 23, g, periph)
+
+/* pb23h_gclk_io1 */
+#define PB23H_GCLK_IO1 \
+	SAM_PINMUX(b, 23, h, periph)
+
+/* pb30_gpio */
+#define PB30_GPIO \
+	SAM_PINMUX(b, 30, gpio, gpio)
+
+/* pb30a_eic_extint14 */
+#define PB30A_EIC_EXTINT14 \
+	SAM_PINMUX(b, 30, a, periph)
+
+/* pb30d_sercom5_pad0 */
+#define PB30D_SERCOM5_PAD0 \
+	SAM_PINMUX(b, 30, d, periph)
+
+/* pb30e_tcc0_wo0 */
+#define PB30E_TCC0_WO0 \
+	SAM_PINMUX(b, 30, e, periph)
+
+/* pb30f_tcc1_wo2 */
+#define PB30F_TCC1_WO2 \
+	SAM_PINMUX(b, 30, f, periph)
+
+/* pb30h_ac_cmp2 */
+#define PB30H_AC_CMP2 \
+	SAM_PINMUX(b, 30, h, periph)
+
+/* pb31_gpio */
+#define PB31_GPIO \
+	SAM_PINMUX(b, 31, gpio, gpio)
+
+/* pb31a_eic_extint15 */
+#define PB31A_EIC_EXTINT15 \
+	SAM_PINMUX(b, 31, a, periph)
+
+/* pb31d_sercom5_pad1 */
+#define PB31D_SERCOM5_PAD1 \
+	SAM_PINMUX(b, 31, d, periph)
+
+/* pb31e_tcc0_wo1 */
+#define PB31E_TCC0_WO1 \
+	SAM_PINMUX(b, 31, e, periph)
+
+/* pb31f_tcc1_wo3 */
+#define PB31F_TCC1_WO3 \
+	SAM_PINMUX(b, 31, f, periph)
+
+/* pb31h_ac_cmp3 */
+#define PB31H_AC_CMP3 \
+	SAM_PINMUX(b, 31, h, periph)
diff --git a/include/dt-bindings/pinctrl/samc21n-pinctrl.h b/include/dt-bindings/pinctrl/samc21n-pinctrl.h
new file mode 100644
index 0000000..c3d078a
--- /dev/null
+++ b/include/dt-bindings/pinctrl/samc21n-pinctrl.h
@@ -0,0 +1,1863 @@
+/*
+ * Autogenerated file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/atmel_sam_pinctrl.h>
+
+/* pa0_gpio */
+#define PA0_GPIO \
+	SAM_PINMUX(a, 0, gpio, gpio)
+
+/* pa0a_eic_extint0 */
+#define PA0A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 0, a, periph)
+
+/* pa0d_sercom1_pad0 */
+#define PA0D_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 0, d, periph)
+
+/* pa0e_tc2_wo0 */
+#define PA0E_TC2_WO0 \
+	SAM_PINMUX(a, 0, e, periph)
+
+/* pa0h_ac_cmp2 */
+#define PA0H_AC_CMP2 \
+	SAM_PINMUX(a, 0, h, periph)
+
+/* pa1_gpio */
+#define PA1_GPIO \
+	SAM_PINMUX(a, 1, gpio, gpio)
+
+/* pa1a_eic_extint1 */
+#define PA1A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 1, a, periph)
+
+/* pa1d_sercom1_pad1 */
+#define PA1D_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 1, d, periph)
+
+/* pa1e_tc2_wo1 */
+#define PA1E_TC2_WO1 \
+	SAM_PINMUX(a, 1, e, periph)
+
+/* pa1h_ac_cmp3 */
+#define PA1H_AC_CMP3 \
+	SAM_PINMUX(a, 1, h, periph)
+
+/* pa2_gpio */
+#define PA2_GPIO \
+	SAM_PINMUX(a, 2, gpio, gpio)
+
+/* pa2a_eic_extint2 */
+#define PA2A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 2, a, periph)
+
+/* pa2b_adc0_ain0 */
+#define PA2B_ADC0_AIN0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ac_ain4 */
+#define PA2B_AC_AIN4 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_ptc_y0 */
+#define PA2B_PTC_Y0 \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa2b_dac_vout */
+#define PA2B_DAC_VOUT \
+	SAM_PINMUX(a, 2, b, periph)
+
+/* pa3_gpio */
+#define PA3_GPIO \
+	SAM_PINMUX(a, 3, gpio, gpio)
+
+/* pa3a_eic_extint3 */
+#define PA3A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 3, a, periph)
+
+/* pa3b_anaref_vrefa */
+#define PA3B_ANAREF_VREFA \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_adc0_ain5 */
+#define PA3B_ADC0_AIN5 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ac_ain4 */
+#define PA3B_AC_AIN4 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa3b_ptc_y1 */
+#define PA3B_PTC_Y1 \
+	SAM_PINMUX(a, 3, b, periph)
+
+/* pa4_gpio */
+#define PA4_GPIO \
+	SAM_PINMUX(a, 4, gpio, gpio)
+
+/* pa4a_eic_extint4 */
+#define PA4A_EIC_EXTINT4 \
+	SAM_PINMUX(a, 4, a, periph)
+
+/* pa4b_anaref_vrefb */
+#define PA4B_ANAREF_VREFB \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_adc0_ain4 */
+#define PA4B_ADC0_AIN4 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ac_ain0 */
+#define PA4B_AC_AIN0 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4b_ptc_y2 */
+#define PA4B_PTC_Y2 \
+	SAM_PINMUX(a, 4, b, periph)
+
+/* pa4d_sercom0_pad0 */
+#define PA4D_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 4, d, periph)
+
+/* pa4e_tc0_wo0 */
+#define PA4E_TC0_WO0 \
+	SAM_PINMUX(a, 4, e, periph)
+
+/* pa5_gpio */
+#define PA5_GPIO \
+	SAM_PINMUX(a, 5, gpio, gpio)
+
+/* pa5a_eic_extint5 */
+#define PA5A_EIC_EXTINT5 \
+	SAM_PINMUX(a, 5, a, periph)
+
+/* pa5b_adc0_ain5 */
+#define PA5B_ADC0_AIN5 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ac_ain1 */
+#define PA5B_AC_AIN1 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5b_ptc_y3 */
+#define PA5B_PTC_Y3 \
+	SAM_PINMUX(a, 5, b, periph)
+
+/* pa5d_sercom0_pad1 */
+#define PA5D_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 5, d, periph)
+
+/* pa5e_tc0_wo1 */
+#define PA5E_TC0_WO1 \
+	SAM_PINMUX(a, 5, e, periph)
+
+/* pa6_gpio */
+#define PA6_GPIO \
+	SAM_PINMUX(a, 6, gpio, gpio)
+
+/* pa6a_eic_extint6 */
+#define PA6A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 6, a, periph)
+
+/* pa6b_adc0_ain6 */
+#define PA6B_ADC0_AIN6 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ac_ain2 */
+#define PA6B_AC_AIN2 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_ptc_y4 */
+#define PA6B_PTC_Y4 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6b_sdadc0_ainn0 */
+#define PA6B_SDADC0_AINN0 \
+	SAM_PINMUX(a, 6, b, periph)
+
+/* pa6d_sercom0_pad2 */
+#define PA6D_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 6, d, periph)
+
+/* pa6e_tcc1_wo0 */
+#define PA6E_TCC1_WO0 \
+	SAM_PINMUX(a, 6, e, periph)
+
+/* pa7_gpio */
+#define PA7_GPIO \
+	SAM_PINMUX(a, 7, gpio, gpio)
+
+/* pa7a_eic_extint7 */
+#define PA7A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 7, a, periph)
+
+/* pa7b_adc0_ain7 */
+#define PA7B_ADC0_AIN7 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ac_ain3 */
+#define PA7B_AC_AIN3 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_ptc_y5 */
+#define PA7B_PTC_Y5 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7b_sdadc0_ainp0 */
+#define PA7B_SDADC0_AINP0 \
+	SAM_PINMUX(a, 7, b, periph)
+
+/* pa7d_sercom0_pad3 */
+#define PA7D_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 7, d, periph)
+
+/* pa7e_tcc1_wo1 */
+#define PA7E_TCC1_WO1 \
+	SAM_PINMUX(a, 7, e, periph)
+
+/* pa8_gpio */
+#define PA8_GPIO \
+	SAM_PINMUX(a, 8, gpio, gpio)
+
+/* pa8a_eic_nmi */
+#define PA8A_EIC_NMI \
+	SAM_PINMUX(a, 8, a, periph)
+
+/* pa8b_adc1_ain10 */
+#define PA8B_ADC1_AIN10 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8b_ptc_xy16 */
+#define PA8B_PTC_XY16 \
+	SAM_PINMUX(a, 8, b, periph)
+
+/* pa8c_sercom0_pad0 */
+#define PA8C_SERCOM0_PAD0 \
+	SAM_PINMUX(a, 8, c, periph)
+
+/* pa8d_sercom2_pad0 */
+#define PA8D_SERCOM2_PAD0 \
+	SAM_PINMUX(a, 8, d, periph)
+
+/* pa8e_tc0_wo0 */
+#define PA8E_TC0_WO0 \
+	SAM_PINMUX(a, 8, e, periph)
+
+/* pa8f_tcc0_wo0 */
+#define PA8F_TCC0_WO0 \
+	SAM_PINMUX(a, 8, f, periph)
+
+/* pa9_gpio */
+#define PA9_GPIO \
+	SAM_PINMUX(a, 9, gpio, gpio)
+
+/* pa9a_eic_extint9 */
+#define PA9A_EIC_EXTINT9 \
+	SAM_PINMUX(a, 9, a, periph)
+
+/* pa9b_adc1_ain11 */
+#define PA9B_ADC1_AIN11 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9b_ptc_x1 */
+#define PA9B_PTC_X1 \
+	SAM_PINMUX(a, 9, b, periph)
+
+/* pa9c_sercom0_pad1 */
+#define PA9C_SERCOM0_PAD1 \
+	SAM_PINMUX(a, 9, c, periph)
+
+/* pa9d_sercom2_pad1 */
+#define PA9D_SERCOM2_PAD1 \
+	SAM_PINMUX(a, 9, d, periph)
+
+/* pa9e_tc0_wo1 */
+#define PA9E_TC0_WO1 \
+	SAM_PINMUX(a, 9, e, periph)
+
+/* pa9f_tcc0_wo1 */
+#define PA9F_TCC0_WO1 \
+	SAM_PINMUX(a, 9, f, periph)
+
+/* pa10_gpio */
+#define PA10_GPIO \
+	SAM_PINMUX(a, 10, gpio, gpio)
+
+/* pa10a_eic_extint10 */
+#define PA10A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 10, a, periph)
+
+/* pa10b_ptc_x2 */
+#define PA10B_PTC_X2 \
+	SAM_PINMUX(a, 10, b, periph)
+
+/* pa10c_sercom0_pad2 */
+#define PA10C_SERCOM0_PAD2 \
+	SAM_PINMUX(a, 10, c, periph)
+
+/* pa10d_sercom2_pad2 */
+#define PA10D_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 10, d, periph)
+
+/* pa10e_tc1_wo0 */
+#define PA10E_TC1_WO0 \
+	SAM_PINMUX(a, 10, e, periph)
+
+/* pa10f_tcc0_wo2 */
+#define PA10F_TCC0_WO2 \
+	SAM_PINMUX(a, 10, f, periph)
+
+/* pa10h_gclk_io4 */
+#define PA10H_GCLK_IO4 \
+	SAM_PINMUX(a, 10, h, periph)
+
+/* pa11_gpio */
+#define PA11_GPIO \
+	SAM_PINMUX(a, 11, gpio, gpio)
+
+/* pa11a_eic_extint11 */
+#define PA11A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 11, a, periph)
+
+/* pa11b_ptc_x3 */
+#define PA11B_PTC_X3 \
+	SAM_PINMUX(a, 11, b, periph)
+
+/* pa11c_sercom0_pad3 */
+#define PA11C_SERCOM0_PAD3 \
+	SAM_PINMUX(a, 11, c, periph)
+
+/* pa11d_sercom2_pad3 */
+#define PA11D_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 11, d, periph)
+
+/* pa11e_tc1_wo1 */
+#define PA11E_TC1_WO1 \
+	SAM_PINMUX(a, 11, e, periph)
+
+/* pa11f_tcc0_wo3 */
+#define PA11F_TCC0_WO3 \
+	SAM_PINMUX(a, 11, f, periph)
+
+/* pa11h_gclk_io5 */
+#define PA11H_GCLK_IO5 \
+	SAM_PINMUX(a, 11, h, periph)
+
+/* pa12_gpio */
+#define PA12_GPIO \
+	SAM_PINMUX(a, 12, gpio, gpio)
+
+/* pa12a_eic_extint12 */
+#define PA12A_EIC_EXTINT12 \
+	SAM_PINMUX(a, 12, a, periph)
+
+/* pa12c_sercom2_pad0 */
+#define PA12C_SERCOM2_PAD0 \
+	SAM_PINMUX(a, 12, c, periph)
+
+/* pa12d_sercom4_pad0 */
+#define PA12D_SERCOM4_PAD0 \
+	SAM_PINMUX(a, 12, d, periph)
+
+/* pa12e_tcc2_wo0 */
+#define PA12E_TCC2_WO0 \
+	SAM_PINMUX(a, 12, e, periph)
+
+/* pa12f_tcc0_wo6 */
+#define PA12F_TCC0_WO6 \
+	SAM_PINMUX(a, 12, f, periph)
+
+/* pa12h_ac_cmp0 */
+#define PA12H_AC_CMP0 \
+	SAM_PINMUX(a, 12, h, periph)
+
+/* pa13_gpio */
+#define PA13_GPIO \
+	SAM_PINMUX(a, 13, gpio, gpio)
+
+/* pa13a_eic_extint13 */
+#define PA13A_EIC_EXTINT13 \
+	SAM_PINMUX(a, 13, a, periph)
+
+/* pa13c_sercom2_pad1 */
+#define PA13C_SERCOM2_PAD1 \
+	SAM_PINMUX(a, 13, c, periph)
+
+/* pa13d_sercom4_pad1 */
+#define PA13D_SERCOM4_PAD1 \
+	SAM_PINMUX(a, 13, d, periph)
+
+/* pa13e_tcc2_wo1 */
+#define PA13E_TCC2_WO1 \
+	SAM_PINMUX(a, 13, e, periph)
+
+/* pa13f_tcc0_wo7 */
+#define PA13F_TCC0_WO7 \
+	SAM_PINMUX(a, 13, f, periph)
+
+/* pa13h_ac_cmp1 */
+#define PA13H_AC_CMP1 \
+	SAM_PINMUX(a, 13, h, periph)
+
+/* pa14_gpio */
+#define PA14_GPIO \
+	SAM_PINMUX(a, 14, gpio, gpio)
+
+/* pa14a_eic_extint14 */
+#define PA14A_EIC_EXTINT14 \
+	SAM_PINMUX(a, 14, a, periph)
+
+/* pa14c_sercom2_pad2 */
+#define PA14C_SERCOM2_PAD2 \
+	SAM_PINMUX(a, 14, c, periph)
+
+/* pa14d_sercom4_pad2 */
+#define PA14D_SERCOM4_PAD2 \
+	SAM_PINMUX(a, 14, d, periph)
+
+/* pa14e_tc3_wo0 */
+#define PA14E_TC3_WO0 \
+	SAM_PINMUX(a, 14, e, periph)
+
+/* pa14h_gclk_io0 */
+#define PA14H_GCLK_IO0 \
+	SAM_PINMUX(a, 14, h, periph)
+
+/* pa15_gpio */
+#define PA15_GPIO \
+	SAM_PINMUX(a, 15, gpio, gpio)
+
+/* pa15a_eic_extint15 */
+#define PA15A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 15, a, periph)
+
+/* pa15c_sercom2_pad3 */
+#define PA15C_SERCOM2_PAD3 \
+	SAM_PINMUX(a, 15, c, periph)
+
+/* pa15d_sercom4_pad3 */
+#define PA15D_SERCOM4_PAD3 \
+	SAM_PINMUX(a, 15, d, periph)
+
+/* pa15e_tc3_wo1 */
+#define PA15E_TC3_WO1 \
+	SAM_PINMUX(a, 15, e, periph)
+
+/* pa15h_gclk_io1 */
+#define PA15H_GCLK_IO1 \
+	SAM_PINMUX(a, 15, h, periph)
+
+/* pa16_gpio */
+#define PA16_GPIO \
+	SAM_PINMUX(a, 16, gpio, gpio)
+
+/* pa16a_eic_extint0 */
+#define PA16A_EIC_EXTINT0 \
+	SAM_PINMUX(a, 16, a, periph)
+
+/* pa16b_ptc_x4 */
+#define PA16B_PTC_X4 \
+	SAM_PINMUX(a, 16, b, periph)
+
+/* pa16c_sercom1_pad0 */
+#define PA16C_SERCOM1_PAD0 \
+	SAM_PINMUX(a, 16, c, periph)
+
+/* pa16d_sercom3_pad0 */
+#define PA16D_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 16, d, periph)
+
+/* pa16e_tcc2_wo0 */
+#define PA16E_TCC2_WO0 \
+	SAM_PINMUX(a, 16, e, periph)
+
+/* pa16f_tcc1_wo6 */
+#define PA16F_TCC1_WO6 \
+	SAM_PINMUX(a, 16, f, periph)
+
+/* pa16h_gclk_io2 */
+#define PA16H_GCLK_IO2 \
+	SAM_PINMUX(a, 16, h, periph)
+
+/* pa17_gpio */
+#define PA17_GPIO \
+	SAM_PINMUX(a, 17, gpio, gpio)
+
+/* pa17a_eic_extint1 */
+#define PA17A_EIC_EXTINT1 \
+	SAM_PINMUX(a, 17, a, periph)
+
+/* pa17b_ptc_x5 */
+#define PA17B_PTC_X5 \
+	SAM_PINMUX(a, 17, b, periph)
+
+/* pa17c_sercom1_pad1 */
+#define PA17C_SERCOM1_PAD1 \
+	SAM_PINMUX(a, 17, c, periph)
+
+/* pa17d_sercom3_pad1 */
+#define PA17D_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 17, d, periph)
+
+/* pa17e_tcc2_wo1 */
+#define PA17E_TCC2_WO1 \
+	SAM_PINMUX(a, 17, e, periph)
+
+/* pa17f_tcc1_wo7 */
+#define PA17F_TCC1_WO7 \
+	SAM_PINMUX(a, 17, f, periph)
+
+/* pa17h_gclk_io3 */
+#define PA17H_GCLK_IO3 \
+	SAM_PINMUX(a, 17, h, periph)
+
+/* pa18_gpio */
+#define PA18_GPIO \
+	SAM_PINMUX(a, 18, gpio, gpio)
+
+/* pa18a_eic_extint2 */
+#define PA18A_EIC_EXTINT2 \
+	SAM_PINMUX(a, 18, a, periph)
+
+/* pa18b_ptc_x6 */
+#define PA18B_PTC_X6 \
+	SAM_PINMUX(a, 18, b, periph)
+
+/* pa18c_sercom1_pad2 */
+#define PA18C_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 18, c, periph)
+
+/* pa18d_sercom3_pad2 */
+#define PA18D_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 18, d, periph)
+
+/* pa18e_tc3_wo0 */
+#define PA18E_TC3_WO0 \
+	SAM_PINMUX(a, 18, e, periph)
+
+/* pa18f_tcc1_wo2 */
+#define PA18F_TCC1_WO2 \
+	SAM_PINMUX(a, 18, f, periph)
+
+/* pa18h_ac_cmp0 */
+#define PA18H_AC_CMP0 \
+	SAM_PINMUX(a, 18, h, periph)
+
+/* pa19_gpio */
+#define PA19_GPIO \
+	SAM_PINMUX(a, 19, gpio, gpio)
+
+/* pa19a_eic_extint3 */
+#define PA19A_EIC_EXTINT3 \
+	SAM_PINMUX(a, 19, a, periph)
+
+/* pa19b_ptc_x7 */
+#define PA19B_PTC_X7 \
+	SAM_PINMUX(a, 19, b, periph)
+
+/* pa19c_sercom1_pad3 */
+#define PA19C_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 19, c, periph)
+
+/* pa19d_sercom3_pad3 */
+#define PA19D_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 19, d, periph)
+
+/* pa19e_tc3_wo1 */
+#define PA19E_TC3_WO1 \
+	SAM_PINMUX(a, 19, e, periph)
+
+/* pa19f_tcc1_wo3 */
+#define PA19F_TCC1_WO3 \
+	SAM_PINMUX(a, 19, f, periph)
+
+/* pa19h_ac_cmp1 */
+#define PA19H_AC_CMP1 \
+	SAM_PINMUX(a, 19, h, periph)
+
+/* pa20_gpio */
+#define PA20_GPIO \
+	SAM_PINMUX(a, 20, gpio, gpio)
+
+/* pa20a_eic_extint4 */
+#define PA20A_EIC_EXTINT4 \
+	SAM_PINMUX(a, 20, a, periph)
+
+/* pa20b_ptc_x8 */
+#define PA20B_PTC_X8 \
+	SAM_PINMUX(a, 20, b, periph)
+
+/* pa20c_sercom5_pad2 */
+#define PA20C_SERCOM5_PAD2 \
+	SAM_PINMUX(a, 20, c, periph)
+
+/* pa20d_sercom3_pad2 */
+#define PA20D_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 20, d, periph)
+
+/* pa20e_tc7_wo0 */
+#define PA20E_TC7_WO0 \
+	SAM_PINMUX(a, 20, e, periph)
+
+/* pa20f_tcc2_wo0 */
+#define PA20F_TCC2_WO0 \
+	SAM_PINMUX(a, 20, f, periph)
+
+/* pa20h_gclk_io4 */
+#define PA20H_GCLK_IO4 \
+	SAM_PINMUX(a, 20, h, periph)
+
+/* pa21_gpio */
+#define PA21_GPIO \
+	SAM_PINMUX(a, 21, gpio, gpio)
+
+/* pa21a_eic_extint5 */
+#define PA21A_EIC_EXTINT5 \
+	SAM_PINMUX(a, 21, a, periph)
+
+/* pa21b_ptc_x9 */
+#define PA21B_PTC_X9 \
+	SAM_PINMUX(a, 21, b, periph)
+
+/* pa21c_sercom5_pad3 */
+#define PA21C_SERCOM5_PAD3 \
+	SAM_PINMUX(a, 21, c, periph)
+
+/* pa21d_sercom3_pad3 */
+#define PA21D_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 21, d, periph)
+
+/* pa21e_tc7_wo1 */
+#define PA21E_TC7_WO1 \
+	SAM_PINMUX(a, 21, e, periph)
+
+/* pa21f_tcc2_wo1 */
+#define PA21F_TCC2_WO1 \
+	SAM_PINMUX(a, 21, f, periph)
+
+/* pa21h_gclk_io5 */
+#define PA21H_GCLK_IO5 \
+	SAM_PINMUX(a, 21, h, periph)
+
+/* pa22_gpio */
+#define PA22_GPIO \
+	SAM_PINMUX(a, 22, gpio, gpio)
+
+/* pa22a_eic_extint6 */
+#define PA22A_EIC_EXTINT6 \
+	SAM_PINMUX(a, 22, a, periph)
+
+/* pa22b_ptc_x10 */
+#define PA22B_PTC_X10 \
+	SAM_PINMUX(a, 22, b, periph)
+
+/* pa22c_sercom3_pad0 */
+#define PA22C_SERCOM3_PAD0 \
+	SAM_PINMUX(a, 22, c, periph)
+
+/* pa22d_sercom5_pad0 */
+#define PA22D_SERCOM5_PAD0 \
+	SAM_PINMUX(a, 22, d, periph)
+
+/* pa22e_tc4_wo0 */
+#define PA22E_TC4_WO0 \
+	SAM_PINMUX(a, 22, e, periph)
+
+/* pa22f_tcc1_wo0 */
+#define PA22F_TCC1_WO0 \
+	SAM_PINMUX(a, 22, f, periph)
+
+/* pa22g_can0_tx */
+#define PA22G_CAN0_TX \
+	SAM_PINMUX(a, 22, g, periph)
+
+/* pa22h_gclk_io6 */
+#define PA22H_GCLK_IO6 \
+	SAM_PINMUX(a, 22, h, periph)
+
+/* pa23_gpio */
+#define PA23_GPIO \
+	SAM_PINMUX(a, 23, gpio, gpio)
+
+/* pa23a_eic_extint7 */
+#define PA23A_EIC_EXTINT7 \
+	SAM_PINMUX(a, 23, a, periph)
+
+/* pa23b_ptc_x11 */
+#define PA23B_PTC_X11 \
+	SAM_PINMUX(a, 23, b, periph)
+
+/* pa23c_sercom3_pad1 */
+#define PA23C_SERCOM3_PAD1 \
+	SAM_PINMUX(a, 23, c, periph)
+
+/* pa23d_sercom5_pad1 */
+#define PA23D_SERCOM5_PAD1 \
+	SAM_PINMUX(a, 23, d, periph)
+
+/* pa23e_tc4_wo1 */
+#define PA23E_TC4_WO1 \
+	SAM_PINMUX(a, 23, e, periph)
+
+/* pa23f_tcc1_wo1 */
+#define PA23F_TCC1_WO1 \
+	SAM_PINMUX(a, 23, f, periph)
+
+/* pa23g_can0_rx */
+#define PA23G_CAN0_RX \
+	SAM_PINMUX(a, 23, g, periph)
+
+/* pa23h_gclk_io7 */
+#define PA23H_GCLK_IO7 \
+	SAM_PINMUX(a, 23, h, periph)
+
+/* pa24_gpio */
+#define PA24_GPIO \
+	SAM_PINMUX(a, 24, gpio, gpio)
+
+/* pa24a_eic_extint12 */
+#define PA24A_EIC_EXTINT12 \
+	SAM_PINMUX(a, 24, a, periph)
+
+/* pa24c_sercom3_pad2 */
+#define PA24C_SERCOM3_PAD2 \
+	SAM_PINMUX(a, 24, c, periph)
+
+/* pa24d_sercom5_pad2 */
+#define PA24D_SERCOM5_PAD2 \
+	SAM_PINMUX(a, 24, d, periph)
+
+/* pa24e_tc5_wo0 */
+#define PA24E_TC5_WO0 \
+	SAM_PINMUX(a, 24, e, periph)
+
+/* pa24f_tcc2_wo0 */
+#define PA24F_TCC2_WO0 \
+	SAM_PINMUX(a, 24, f, periph)
+
+/* pa24g_can0_tx */
+#define PA24G_CAN0_TX \
+	SAM_PINMUX(a, 24, g, periph)
+
+/* pa24h_ac_cmp2 */
+#define PA24H_AC_CMP2 \
+	SAM_PINMUX(a, 24, h, periph)
+
+/* pa25_gpio */
+#define PA25_GPIO \
+	SAM_PINMUX(a, 25, gpio, gpio)
+
+/* pa25a_eic_extint13 */
+#define PA25A_EIC_EXTINT13 \
+	SAM_PINMUX(a, 25, a, periph)
+
+/* pa25c_sercom3_pad3 */
+#define PA25C_SERCOM3_PAD3 \
+	SAM_PINMUX(a, 25, c, periph)
+
+/* pa25d_sercom5_pad3 */
+#define PA25D_SERCOM5_PAD3 \
+	SAM_PINMUX(a, 25, d, periph)
+
+/* pa25e_tc5_wo1 */
+#define PA25E_TC5_WO1 \
+	SAM_PINMUX(a, 25, e, periph)
+
+/* pa25f_tcc2_wo1 */
+#define PA25F_TCC2_WO1 \
+	SAM_PINMUX(a, 25, f, periph)
+
+/* pa25g_can0_rx */
+#define PA25G_CAN0_RX \
+	SAM_PINMUX(a, 25, g, periph)
+
+/* pa25h_ac_cmp3 */
+#define PA25H_AC_CMP3 \
+	SAM_PINMUX(a, 25, h, periph)
+
+/* pa27_gpio */
+#define PA27_GPIO \
+	SAM_PINMUX(a, 27, gpio, gpio)
+
+/* pa27a_eic_extint15 */
+#define PA27A_EIC_EXTINT15 \
+	SAM_PINMUX(a, 27, a, periph)
+
+/* pa27h_gclk_io0 */
+#define PA27H_GCLK_IO0 \
+	SAM_PINMUX(a, 27, h, periph)
+
+/* pa28_gpio */
+#define PA28_GPIO \
+	SAM_PINMUX(a, 28, gpio, gpio)
+
+/* pa28a_eic_extint8 */
+#define PA28A_EIC_EXTINT8 \
+	SAM_PINMUX(a, 28, a, periph)
+
+/* pa28h_gclk_io0 */
+#define PA28H_GCLK_IO0 \
+	SAM_PINMUX(a, 28, h, periph)
+
+/* pa30_gpio */
+#define PA30_GPIO \
+	SAM_PINMUX(a, 30, gpio, gpio)
+
+/* pa30a_eic_extint10 */
+#define PA30A_EIC_EXTINT10 \
+	SAM_PINMUX(a, 30, a, periph)
+
+/* pa30d_sercom1_pad2 */
+#define PA30D_SERCOM1_PAD2 \
+	SAM_PINMUX(a, 30, d, periph)
+
+/* pa30e_tc1_wo0 */
+#define PA30E_TC1_WO0 \
+	SAM_PINMUX(a, 30, e, periph)
+
+/* pa30g_swd_clk */
+#define PA30G_SWD_CLK \
+	SAM_PINMUX(a, 30, g, periph)
+
+/* pa30h_gclk_io0 */
+#define PA30H_GCLK_IO0 \
+	SAM_PINMUX(a, 30, h, periph)
+
+/* pa31_gpio */
+#define PA31_GPIO \
+	SAM_PINMUX(a, 31, gpio, gpio)
+
+/* pa31a_eic_extint11 */
+#define PA31A_EIC_EXTINT11 \
+	SAM_PINMUX(a, 31, a, periph)
+
+/* pa31d_sercom1_pad3 */
+#define PA31D_SERCOM1_PAD3 \
+	SAM_PINMUX(a, 31, d, periph)
+
+/* pa31e_tc1_wo1 */
+#define PA31E_TC1_WO1 \
+	SAM_PINMUX(a, 31, e, periph)
+
+/* pa31g_swd_io */
+#define PA31G_SWD_IO \
+	SAM_PINMUX(a, 31, g, periph)
+
+/* pb0_gpio */
+#define PB0_GPIO \
+	SAM_PINMUX(b, 0, gpio, gpio)
+
+/* pb0a_eic_extint0 */
+#define PB0A_EIC_EXTINT0 \
+	SAM_PINMUX(b, 0, a, periph)
+
+/* pb0b_adc1_ain0 */
+#define PB0B_ADC1_AIN0 \
+	SAM_PINMUX(b, 0, b, periph)
+
+/* pb0b_ptc_y6 */
+#define PB0B_PTC_Y6 \
+	SAM_PINMUX(b, 0, b, periph)
+
+/* pb0d_sercom5_pad2 */
+#define PB0D_SERCOM5_PAD2 \
+	SAM_PINMUX(b, 0, d, periph)
+
+/* pb0e_tc7_wo0 */
+#define PB0E_TC7_WO0 \
+	SAM_PINMUX(b, 0, e, periph)
+
+/* pb1_gpio */
+#define PB1_GPIO \
+	SAM_PINMUX(b, 1, gpio, gpio)
+
+/* pb1a_eic_extint1 */
+#define PB1A_EIC_EXTINT1 \
+	SAM_PINMUX(b, 1, a, periph)
+
+/* pb1b_adc1_ain1 */
+#define PB1B_ADC1_AIN1 \
+	SAM_PINMUX(b, 1, b, periph)
+
+/* pb1b_ptc_y7 */
+#define PB1B_PTC_Y7 \
+	SAM_PINMUX(b, 1, b, periph)
+
+/* pb1d_sercom5_pad3 */
+#define PB1D_SERCOM5_PAD3 \
+	SAM_PINMUX(b, 1, d, periph)
+
+/* pb1e_tc7_wo1 */
+#define PB1E_TC7_WO1 \
+	SAM_PINMUX(b, 1, e, periph)
+
+/* pb2_gpio */
+#define PB2_GPIO \
+	SAM_PINMUX(b, 2, gpio, gpio)
+
+/* pb2a_eic_extint2 */
+#define PB2A_EIC_EXTINT2 \
+	SAM_PINMUX(b, 2, a, periph)
+
+/* pb2b_adc1_ain2 */
+#define PB2B_ADC1_AIN2 \
+	SAM_PINMUX(b, 2, b, periph)
+
+/* pb2b_ptc_y8 */
+#define PB2B_PTC_Y8 \
+	SAM_PINMUX(b, 2, b, periph)
+
+/* pb2d_sercom5_pad0 */
+#define PB2D_SERCOM5_PAD0 \
+	SAM_PINMUX(b, 2, d, periph)
+
+/* pb2e_tc6_wo0 */
+#define PB2E_TC6_WO0 \
+	SAM_PINMUX(b, 2, e, periph)
+
+/* pb3_gpio */
+#define PB3_GPIO \
+	SAM_PINMUX(b, 3, gpio, gpio)
+
+/* pb3a_eic_extint3 */
+#define PB3A_EIC_EXTINT3 \
+	SAM_PINMUX(b, 3, a, periph)
+
+/* pb3b_adc1_ain3 */
+#define PB3B_ADC1_AIN3 \
+	SAM_PINMUX(b, 3, b, periph)
+
+/* pb3b_ptc_y9 */
+#define PB3B_PTC_Y9 \
+	SAM_PINMUX(b, 3, b, periph)
+
+/* pb3d_sercom5_pad1 */
+#define PB3D_SERCOM5_PAD1 \
+	SAM_PINMUX(b, 3, d, periph)
+
+/* pb3e_tc6_wo1 */
+#define PB3E_TC6_WO1 \
+	SAM_PINMUX(b, 3, e, periph)
+
+/* pb4_gpio */
+#define PB4_GPIO \
+	SAM_PINMUX(b, 4, gpio, gpio)
+
+/* pb4a_eic_extint4 */
+#define PB4A_EIC_EXTINT4 \
+	SAM_PINMUX(b, 4, a, periph)
+
+/* pb4b_adc0_ain6 */
+#define PB4B_ADC0_AIN6 \
+	SAM_PINMUX(b, 4, b, periph)
+
+/* pb4b_ptc_y10 */
+#define PB4B_PTC_Y10 \
+	SAM_PINMUX(b, 4, b, periph)
+
+/* pb5_gpio */
+#define PB5_GPIO \
+	SAM_PINMUX(b, 5, gpio, gpio)
+
+/* pb5a_eic_extint5 */
+#define PB5A_EIC_EXTINT5 \
+	SAM_PINMUX(b, 5, a, periph)
+
+/* pb5b_adc0_ain7 */
+#define PB5B_ADC0_AIN7 \
+	SAM_PINMUX(b, 5, b, periph)
+
+/* pb5b_ac_ain6 */
+#define PB5B_AC_AIN6 \
+	SAM_PINMUX(b, 5, b, periph)
+
+/* pb5b_ptc_y11 */
+#define PB5B_PTC_Y11 \
+	SAM_PINMUX(b, 5, b, periph)
+
+/* pb6_gpio */
+#define PB6_GPIO \
+	SAM_PINMUX(b, 6, gpio, gpio)
+
+/* pb6a_eic_extint6 */
+#define PB6A_EIC_EXTINT6 \
+	SAM_PINMUX(b, 6, a, periph)
+
+/* pb6b_adc0_ain8 */
+#define PB6B_ADC0_AIN8 \
+	SAM_PINMUX(b, 6, b, periph)
+
+/* pb6b_ac_ain7 */
+#define PB6B_AC_AIN7 \
+	SAM_PINMUX(b, 6, b, periph)
+
+/* pb6b_ptc_y12 */
+#define PB6B_PTC_Y12 \
+	SAM_PINMUX(b, 6, b, periph)
+
+/* pb6b_sdadc0_ainn2 */
+#define PB6B_SDADC0_AINN2 \
+	SAM_PINMUX(b, 6, b, periph)
+
+/* pb6c_sercom7_pad1 */
+#define PB6C_SERCOM7_PAD1 \
+	SAM_PINMUX(b, 6, c, periph)
+
+/* pb7_gpio */
+#define PB7_GPIO \
+	SAM_PINMUX(b, 7, gpio, gpio)
+
+/* pb7a_eic_extint7 */
+#define PB7A_EIC_EXTINT7 \
+	SAM_PINMUX(b, 7, a, periph)
+
+/* pb7b_adc0_ain9 */
+#define PB7B_ADC0_AIN9 \
+	SAM_PINMUX(b, 7, b, periph)
+
+/* pb7b_ptc_y13 */
+#define PB7B_PTC_Y13 \
+	SAM_PINMUX(b, 7, b, periph)
+
+/* pb7b_sdadc0_ainp2 */
+#define PB7B_SDADC0_AINP2 \
+	SAM_PINMUX(b, 7, b, periph)
+
+/* pb7c_sercom7_pad3 */
+#define PB7C_SERCOM7_PAD3 \
+	SAM_PINMUX(b, 7, c, periph)
+
+/* pb7d_sercom7_pad2 */
+#define PB7D_SERCOM7_PAD2 \
+	SAM_PINMUX(b, 7, d, periph)
+
+/* pb8_gpio */
+#define PB8_GPIO \
+	SAM_PINMUX(b, 8, gpio, gpio)
+
+/* pb8a_eic_extint8 */
+#define PB8A_EIC_EXTINT8 \
+	SAM_PINMUX(b, 8, a, periph)
+
+/* pb8b_adc0_ain2 */
+#define PB8B_ADC0_AIN2 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8b_adc1_ain4 */
+#define PB8B_ADC1_AIN4 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8b_ptc_y14 */
+#define PB8B_PTC_Y14 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8b_sdadc0_ainn1 */
+#define PB8B_SDADC0_AINN1 \
+	SAM_PINMUX(b, 8, b, periph)
+
+/* pb8c_sercom7_pad2 */
+#define PB8C_SERCOM7_PAD2 \
+	SAM_PINMUX(b, 8, c, periph)
+
+/* pb8d_sercom7_pad3 */
+#define PB8D_SERCOM7_PAD3 \
+	SAM_PINMUX(b, 8, d, periph)
+
+/* pb8e_tc4_wo0 */
+#define PB8E_TC4_WO0 \
+	SAM_PINMUX(b, 8, e, periph)
+
+/* pb9_gpio */
+#define PB9_GPIO \
+	SAM_PINMUX(b, 9, gpio, gpio)
+
+/* pb9a_eic_extint9 */
+#define PB9A_EIC_EXTINT9 \
+	SAM_PINMUX(b, 9, a, periph)
+
+/* pb9b_adc0_ain3 */
+#define PB9B_ADC0_AIN3 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9b_adc1_ain5 */
+#define PB9B_ADC1_AIN5 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9b_ptc_y15 */
+#define PB9B_PTC_Y15 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9b_sdadc0_ainp1 */
+#define PB9B_SDADC0_AINP1 \
+	SAM_PINMUX(b, 9, b, periph)
+
+/* pb9d_sercom4_pad1 */
+#define PB9D_SERCOM4_PAD1 \
+	SAM_PINMUX(b, 9, d, periph)
+
+/* pb9e_tc4_wo1 */
+#define PB9E_TC4_WO1 \
+	SAM_PINMUX(b, 9, e, periph)
+
+/* pb10_gpio */
+#define PB10_GPIO \
+	SAM_PINMUX(b, 10, gpio, gpio)
+
+/* pb10a_eic_extint10 */
+#define PB10A_EIC_EXTINT10 \
+	SAM_PINMUX(b, 10, a, periph)
+
+/* pb10d_sercom4_pad2 */
+#define PB10D_SERCOM4_PAD2 \
+	SAM_PINMUX(b, 10, d, periph)
+
+/* pb10e_tc5_wo0 */
+#define PB10E_TC5_WO0 \
+	SAM_PINMUX(b, 10, e, periph)
+
+/* pb10f_tcc0_wo4 */
+#define PB10F_TCC0_WO4 \
+	SAM_PINMUX(b, 10, f, periph)
+
+/* pb10h_gclk_io4 */
+#define PB10H_GCLK_IO4 \
+	SAM_PINMUX(b, 10, h, periph)
+
+/* pb11_gpio */
+#define PB11_GPIO \
+	SAM_PINMUX(b, 11, gpio, gpio)
+
+/* pb11a_eic_extint11 */
+#define PB11A_EIC_EXTINT11 \
+	SAM_PINMUX(b, 11, a, periph)
+
+/* pb11d_sercom4_pad3 */
+#define PB11D_SERCOM4_PAD3 \
+	SAM_PINMUX(b, 11, d, periph)
+
+/* pb11e_tc5_wo1 */
+#define PB11E_TC5_WO1 \
+	SAM_PINMUX(b, 11, e, periph)
+
+/* pb11f_tcc0_wo5 */
+#define PB11F_TCC0_WO5 \
+	SAM_PINMUX(b, 11, f, periph)
+
+/* pb11h_gclk_io5 */
+#define PB11H_GCLK_IO5 \
+	SAM_PINMUX(b, 11, h, periph)
+
+/* pb12_gpio */
+#define PB12_GPIO \
+	SAM_PINMUX(b, 12, gpio, gpio)
+
+/* pb12a_eic_extint12 */
+#define PB12A_EIC_EXTINT12 \
+	SAM_PINMUX(b, 12, a, periph)
+
+/* pb12b_ptc_x12 */
+#define PB12B_PTC_X12 \
+	SAM_PINMUX(b, 12, b, periph)
+
+/* pb12c_sercom4_pad0 */
+#define PB12C_SERCOM4_PAD0 \
+	SAM_PINMUX(b, 12, c, periph)
+
+/* pb12e_tc4_wo0 */
+#define PB12E_TC4_WO0 \
+	SAM_PINMUX(b, 12, e, periph)
+
+/* pb12f_tcc0_wo6 */
+#define PB12F_TCC0_WO6 \
+	SAM_PINMUX(b, 12, f, periph)
+
+/* pb12g_can1_tx */
+#define PB12G_CAN1_TX \
+	SAM_PINMUX(b, 12, g, periph)
+
+/* pb12h_gclk_io6 */
+#define PB12H_GCLK_IO6 \
+	SAM_PINMUX(b, 12, h, periph)
+
+/* pb13_gpio */
+#define PB13_GPIO \
+	SAM_PINMUX(b, 13, gpio, gpio)
+
+/* pb13a_eic_extint13 */
+#define PB13A_EIC_EXTINT13 \
+	SAM_PINMUX(b, 13, a, periph)
+
+/* pb13b_ptc_x13 */
+#define PB13B_PTC_X13 \
+	SAM_PINMUX(b, 13, b, periph)
+
+/* pb13c_sercom4_pad1 */
+#define PB13C_SERCOM4_PAD1 \
+	SAM_PINMUX(b, 13, c, periph)
+
+/* pb13e_tc4_wo1 */
+#define PB13E_TC4_WO1 \
+	SAM_PINMUX(b, 13, e, periph)
+
+/* pb13f_tcc0_wo7 */
+#define PB13F_TCC0_WO7 \
+	SAM_PINMUX(b, 13, f, periph)
+
+/* pb13g_can1_rx */
+#define PB13G_CAN1_RX \
+	SAM_PINMUX(b, 13, g, periph)
+
+/* pb13h_gclk_io7 */
+#define PB13H_GCLK_IO7 \
+	SAM_PINMUX(b, 13, h, periph)
+
+/* pb14_gpio */
+#define PB14_GPIO \
+	SAM_PINMUX(b, 14, gpio, gpio)
+
+/* pb14a_eic_extint14 */
+#define PB14A_EIC_EXTINT14 \
+	SAM_PINMUX(b, 14, a, periph)
+
+/* pb14b_ptc_x14 */
+#define PB14B_PTC_X14 \
+	SAM_PINMUX(b, 14, b, periph)
+
+/* pb14c_sercom4_pad2 */
+#define PB14C_SERCOM4_PAD2 \
+	SAM_PINMUX(b, 14, c, periph)
+
+/* pb14e_tc5_wo0 */
+#define PB14E_TC5_WO0 \
+	SAM_PINMUX(b, 14, e, periph)
+
+/* pb14g_can1_tx */
+#define PB14G_CAN1_TX \
+	SAM_PINMUX(b, 14, g, periph)
+
+/* pb14h_gclk_io0 */
+#define PB14H_GCLK_IO0 \
+	SAM_PINMUX(b, 14, h, periph)
+
+/* pb15_gpio */
+#define PB15_GPIO \
+	SAM_PINMUX(b, 15, gpio, gpio)
+
+/* pb15a_eic_extint15 */
+#define PB15A_EIC_EXTINT15 \
+	SAM_PINMUX(b, 15, a, periph)
+
+/* pb15b_ptc_x15 */
+#define PB15B_PTC_X15 \
+	SAM_PINMUX(b, 15, b, periph)
+
+/* pb15c_sercom4_pad3 */
+#define PB15C_SERCOM4_PAD3 \
+	SAM_PINMUX(b, 15, c, periph)
+
+/* pb15e_tc5_wo1 */
+#define PB15E_TC5_WO1 \
+	SAM_PINMUX(b, 15, e, periph)
+
+/* pb15g_can1_rx */
+#define PB15G_CAN1_RX \
+	SAM_PINMUX(b, 15, g, periph)
+
+/* pb15h_gclk_io1 */
+#define PB15H_GCLK_IO1 \
+	SAM_PINMUX(b, 15, h, periph)
+
+/* pb16_gpio */
+#define PB16_GPIO \
+	SAM_PINMUX(b, 16, gpio, gpio)
+
+/* pb16a_eic_extint0 */
+#define PB16A_EIC_EXTINT0 \
+	SAM_PINMUX(b, 16, a, periph)
+
+/* pb16c_sercom5_pad0 */
+#define PB16C_SERCOM5_PAD0 \
+	SAM_PINMUX(b, 16, c, periph)
+
+/* pb16e_tc6_wo0 */
+#define PB16E_TC6_WO0 \
+	SAM_PINMUX(b, 16, e, periph)
+
+/* pb16h_gclk_io2 */
+#define PB16H_GCLK_IO2 \
+	SAM_PINMUX(b, 16, h, periph)
+
+/* pb17_gpio */
+#define PB17_GPIO \
+	SAM_PINMUX(b, 17, gpio, gpio)
+
+/* pb17a_eic_extint1 */
+#define PB17A_EIC_EXTINT1 \
+	SAM_PINMUX(b, 17, a, periph)
+
+/* pb17c_sercom5_pad1 */
+#define PB17C_SERCOM5_PAD1 \
+	SAM_PINMUX(b, 17, c, periph)
+
+/* pb17e_tc6_wo1 */
+#define PB17E_TC6_WO1 \
+	SAM_PINMUX(b, 17, e, periph)
+
+/* pb17h_gclk_io3 */
+#define PB17H_GCLK_IO3 \
+	SAM_PINMUX(b, 17, h, periph)
+
+/* pb18_gpio */
+#define PB18_GPIO \
+	SAM_PINMUX(b, 18, gpio, gpio)
+
+/* pb18a_eic_extint2 */
+#define PB18A_EIC_EXTINT2 \
+	SAM_PINMUX(b, 18, a, periph)
+
+/* pb18c_sercom5_pad2 */
+#define PB18C_SERCOM5_PAD2 \
+	SAM_PINMUX(b, 18, c, periph)
+
+/* pb18d_sercom3_pad2 */
+#define PB18D_SERCOM3_PAD2 \
+	SAM_PINMUX(b, 18, d, periph)
+
+/* pb18h_gclk_io4 */
+#define PB18H_GCLK_IO4 \
+	SAM_PINMUX(b, 18, h, periph)
+
+/* pb19_gpio */
+#define PB19_GPIO \
+	SAM_PINMUX(b, 19, gpio, gpio)
+
+/* pb19a_eic_extint3 */
+#define PB19A_EIC_EXTINT3 \
+	SAM_PINMUX(b, 19, a, periph)
+
+/* pb19c_sercom5_pad3 */
+#define PB19C_SERCOM5_PAD3 \
+	SAM_PINMUX(b, 19, c, periph)
+
+/* pb19d_sercom3_pad3 */
+#define PB19D_SERCOM3_PAD3 \
+	SAM_PINMUX(b, 19, d, periph)
+
+/* pb19h_gclk_io5 */
+#define PB19H_GCLK_IO5 \
+	SAM_PINMUX(b, 19, h, periph)
+
+/* pb20_gpio */
+#define PB20_GPIO \
+	SAM_PINMUX(b, 20, gpio, gpio)
+
+/* pb20a_eic_extint4 */
+#define PB20A_EIC_EXTINT4 \
+	SAM_PINMUX(b, 20, a, periph)
+
+/* pb20c_sercom3_pad0 */
+#define PB20C_SERCOM3_PAD0 \
+	SAM_PINMUX(b, 20, c, periph)
+
+/* pb20d_sercom2_pad0 */
+#define PB20D_SERCOM2_PAD0 \
+	SAM_PINMUX(b, 20, d, periph)
+
+/* pb20h_gclk_io6 */
+#define PB20H_GCLK_IO6 \
+	SAM_PINMUX(b, 20, h, periph)
+
+/* pb21_gpio */
+#define PB21_GPIO \
+	SAM_PINMUX(b, 21, gpio, gpio)
+
+/* pb21a_eic_extint5 */
+#define PB21A_EIC_EXTINT5 \
+	SAM_PINMUX(b, 21, a, periph)
+
+/* pb21c_sercom3_pad1 */
+#define PB21C_SERCOM3_PAD1 \
+	SAM_PINMUX(b, 21, c, periph)
+
+/* pb21d_sercom2_pad2 */
+#define PB21D_SERCOM2_PAD2 \
+	SAM_PINMUX(b, 21, d, periph)
+
+/* pb21h_gclk_io7 */
+#define PB21H_GCLK_IO7 \
+	SAM_PINMUX(b, 21, h, periph)
+
+/* pb22_gpio */
+#define PB22_GPIO \
+	SAM_PINMUX(b, 22, gpio, gpio)
+
+/* pb22a_eic_extint6 */
+#define PB22A_EIC_EXTINT6 \
+	SAM_PINMUX(b, 22, a, periph)
+
+/* pb22c_sercom0_pad2 */
+#define PB22C_SERCOM0_PAD2 \
+	SAM_PINMUX(b, 22, c, periph)
+
+/* pb22d_sercom5_pad2 */
+#define PB22D_SERCOM5_PAD2 \
+	SAM_PINMUX(b, 22, d, periph)
+
+/* pb22e_tc7_wo0 */
+#define PB22E_TC7_WO0 \
+	SAM_PINMUX(b, 22, e, periph)
+
+/* pb22f_tcc1_wo2 */
+#define PB22F_TCC1_WO2 \
+	SAM_PINMUX(b, 22, f, periph)
+
+/* pb22h_gclk_io0 */
+#define PB22H_GCLK_IO0 \
+	SAM_PINMUX(b, 22, h, periph)
+
+/* pb23_gpio */
+#define PB23_GPIO \
+	SAM_PINMUX(b, 23, gpio, gpio)
+
+/* pb23a_eic_extint7 */
+#define PB23A_EIC_EXTINT7 \
+	SAM_PINMUX(b, 23, a, periph)
+
+/* pb23c_sercom0_pad3 */
+#define PB23C_SERCOM0_PAD3 \
+	SAM_PINMUX(b, 23, c, periph)
+
+/* pb23d_sercom5_pad3 */
+#define PB23D_SERCOM5_PAD3 \
+	SAM_PINMUX(b, 23, d, periph)
+
+/* pb23e_tc7_wo1 */
+#define PB23E_TC7_WO1 \
+	SAM_PINMUX(b, 23, e, periph)
+
+/* pb23f_tcc1_wo3 */
+#define PB23F_TCC1_WO3 \
+	SAM_PINMUX(b, 23, f, periph)
+
+/* pb23h_gclk_io1 */
+#define PB23H_GCLK_IO1 \
+	SAM_PINMUX(b, 23, h, periph)
+
+/* pb24_gpio */
+#define PB24_GPIO \
+	SAM_PINMUX(b, 24, gpio, gpio)
+
+/* pb24a_eic_extint7 */
+#define PB24A_EIC_EXTINT7 \
+	SAM_PINMUX(b, 24, a, periph)
+
+/* pb24c_sercom0_pad0 */
+#define PB24C_SERCOM0_PAD0 \
+	SAM_PINMUX(b, 24, c, periph)
+
+/* pb24d_sercom4_pad0 */
+#define PB24D_SERCOM4_PAD0 \
+	SAM_PINMUX(b, 24, d, periph)
+
+/* pb24h_ac_cmp0 */
+#define PB24H_AC_CMP0 \
+	SAM_PINMUX(b, 24, h, periph)
+
+/* pb25_gpio */
+#define PB25_GPIO \
+	SAM_PINMUX(b, 25, gpio, gpio)
+
+/* pb25a_eic_extint8 */
+#define PB25A_EIC_EXTINT8 \
+	SAM_PINMUX(b, 25, a, periph)
+
+/* pb25c_sercom0_pad1 */
+#define PB25C_SERCOM0_PAD1 \
+	SAM_PINMUX(b, 25, c, periph)
+
+/* pb25d_sercom4_pad1 */
+#define PB25D_SERCOM4_PAD1 \
+	SAM_PINMUX(b, 25, d, periph)
+
+/* pb25h_ac_cmp1 */
+#define PB25H_AC_CMP1 \
+	SAM_PINMUX(b, 25, h, periph)
+
+/* pb30_gpio */
+#define PB30_GPIO \
+	SAM_PINMUX(b, 30, gpio, gpio)
+
+/* pb30a_eic_extint14 */
+#define PB30A_EIC_EXTINT14 \
+	SAM_PINMUX(b, 30, a, periph)
+
+/* pb30d_sercom5_pad0 */
+#define PB30D_SERCOM5_PAD0 \
+	SAM_PINMUX(b, 30, d, periph)
+
+/* pb30e_tc0_wo0 */
+#define PB30E_TC0_WO0 \
+	SAM_PINMUX(b, 30, e, periph)
+
+/* pb30h_ac_cmp2 */
+#define PB30H_AC_CMP2 \
+	SAM_PINMUX(b, 30, h, periph)
+
+/* pb31_gpio */
+#define PB31_GPIO \
+	SAM_PINMUX(b, 31, gpio, gpio)
+
+/* pb31a_eic_extint15 */
+#define PB31A_EIC_EXTINT15 \
+	SAM_PINMUX(b, 31, a, periph)
+
+/* pb31d_sercom5_pad1 */
+#define PB31D_SERCOM5_PAD1 \
+	SAM_PINMUX(b, 31, d, periph)
+
+/* pb31e_tc0_wo1 */
+#define PB31E_TC0_WO1 \
+	SAM_PINMUX(b, 31, e, periph)
+
+/* pb31h_ac_cmp3 */
+#define PB31H_AC_CMP3 \
+	SAM_PINMUX(b, 31, h, periph)
+
+/* pc0_gpio */
+#define PC0_GPIO \
+	SAM_PINMUX(c, 0, gpio, gpio)
+
+/* pc0a_eic_extint8 */
+#define PC0A_EIC_EXTINT8 \
+	SAM_PINMUX(c, 0, a, periph)
+
+/* pc0b_adc0_ain8 */
+#define PC0B_ADC0_AIN8 \
+	SAM_PINMUX(c, 0, b, periph)
+
+/* pc1_gpio */
+#define PC1_GPIO \
+	SAM_PINMUX(c, 1, gpio, gpio)
+
+/* pc1a_eic_extint9 */
+#define PC1A_EIC_EXTINT9 \
+	SAM_PINMUX(c, 1, a, periph)
+
+/* pc1b_adc0_ain9 */
+#define PC1B_ADC0_AIN9 \
+	SAM_PINMUX(c, 1, b, periph)
+
+/* pc2_gpio */
+#define PC2_GPIO \
+	SAM_PINMUX(c, 2, gpio, gpio)
+
+/* pc2a_eic_extint10 */
+#define PC2A_EIC_EXTINT10 \
+	SAM_PINMUX(c, 2, a, periph)
+
+/* pc2b_adc0_ain10 */
+#define PC2B_ADC0_AIN10 \
+	SAM_PINMUX(c, 2, b, periph)
+
+/* pc3_gpio */
+#define PC3_GPIO \
+	SAM_PINMUX(c, 3, gpio, gpio)
+
+/* pc3a_eic_extint11 */
+#define PC3A_EIC_EXTINT11 \
+	SAM_PINMUX(c, 3, a, periph)
+
+/* pc3b_adc0_ain11 */
+#define PC3B_ADC0_AIN11 \
+	SAM_PINMUX(c, 3, b, periph)
+
+/* pc3c_sercom7_pad0 */
+#define PC3C_SERCOM7_PAD0 \
+	SAM_PINMUX(c, 3, c, periph)
+
+/* pc3f_tcc2_wo0 */
+#define PC3F_TCC2_WO0 \
+	SAM_PINMUX(c, 3, f, periph)
+
+/* pc5_gpio */
+#define PC5_GPIO \
+	SAM_PINMUX(c, 5, gpio, gpio)
+
+/* pc5a_eic_extint13 */
+#define PC5A_EIC_EXTINT13 \
+	SAM_PINMUX(c, 5, a, periph)
+
+/* pc5c_sercom6_pad3 */
+#define PC5C_SERCOM6_PAD3 \
+	SAM_PINMUX(c, 5, c, periph)
+
+/* pc5f_tcc2_wo1 */
+#define PC5F_TCC2_WO1 \
+	SAM_PINMUX(c, 5, f, periph)
+
+/* pc6_gpio */
+#define PC6_GPIO \
+	SAM_PINMUX(c, 6, gpio, gpio)
+
+/* pc6a_eic_extint14 */
+#define PC6A_EIC_EXTINT14 \
+	SAM_PINMUX(c, 6, a, periph)
+
+/* pc6c_sercom6_pad0 */
+#define PC6C_SERCOM6_PAD0 \
+	SAM_PINMUX(c, 6, c, periph)
+
+/* pc7_gpio */
+#define PC7_GPIO \
+	SAM_PINMUX(c, 7, gpio, gpio)
+
+/* pc7a_eic_extint15 */
+#define PC7A_EIC_EXTINT15 \
+	SAM_PINMUX(c, 7, a, periph)
+
+/* pc7c_sercom6_pad1 */
+#define PC7C_SERCOM6_PAD1 \
+	SAM_PINMUX(c, 7, c, periph)
+
+/* pc8_gpio */
+#define PC8_GPIO \
+	SAM_PINMUX(c, 8, gpio, gpio)
+
+/* pc8a_eic_extint0 */
+#define PC8A_EIC_EXTINT0 \
+	SAM_PINMUX(c, 8, a, periph)
+
+/* pc8c_sercom6_pad0 */
+#define PC8C_SERCOM6_PAD0 \
+	SAM_PINMUX(c, 8, c, periph)
+
+/* pc8d_sercom7_pad0 */
+#define PC8D_SERCOM7_PAD0 \
+	SAM_PINMUX(c, 8, d, periph)
+
+/* pc9_gpio */
+#define PC9_GPIO \
+	SAM_PINMUX(c, 9, gpio, gpio)
+
+/* pc9a_eic_extint1 */
+#define PC9A_EIC_EXTINT1 \
+	SAM_PINMUX(c, 9, a, periph)
+
+/* pc9c_sercom6_pad1 */
+#define PC9C_SERCOM6_PAD1 \
+	SAM_PINMUX(c, 9, c, periph)
+
+/* pc9d_sercom7_pad1 */
+#define PC9D_SERCOM7_PAD1 \
+	SAM_PINMUX(c, 9, d, periph)
+
+/* pc10_gpio */
+#define PC10_GPIO \
+	SAM_PINMUX(c, 10, gpio, gpio)
+
+/* pc10a_eic_extint2 */
+#define PC10A_EIC_EXTINT2 \
+	SAM_PINMUX(c, 10, a, periph)
+
+/* pc10c_sercom6_pad2 */
+#define PC10C_SERCOM6_PAD2 \
+	SAM_PINMUX(c, 10, c, periph)
+
+/* pc10d_sercom7_pad2 */
+#define PC10D_SERCOM7_PAD2 \
+	SAM_PINMUX(c, 10, d, periph)
+
+/* pc11_gpio */
+#define PC11_GPIO \
+	SAM_PINMUX(c, 11, gpio, gpio)
+
+/* pc11a_eic_extint3 */
+#define PC11A_EIC_EXTINT3 \
+	SAM_PINMUX(c, 11, a, periph)
+
+/* pc11c_sercom6_pad3 */
+#define PC11C_SERCOM6_PAD3 \
+	SAM_PINMUX(c, 11, c, periph)
+
+/* pc11d_sercom7_pad3 */
+#define PC11D_SERCOM7_PAD3 \
+	SAM_PINMUX(c, 11, d, periph)
+
+/* pc12_gpio */
+#define PC12_GPIO \
+	SAM_PINMUX(c, 12, gpio, gpio)
+
+/* pc12a_eic_extint4 */
+#define PC12A_EIC_EXTINT4 \
+	SAM_PINMUX(c, 12, a, periph)
+
+/* pc12c_sercom7_pad0 */
+#define PC12C_SERCOM7_PAD0 \
+	SAM_PINMUX(c, 12, c, periph)
+
+/* pc13_gpio */
+#define PC13_GPIO \
+	SAM_PINMUX(c, 13, gpio, gpio)
+
+/* pc13a_eic_extint5 */
+#define PC13A_EIC_EXTINT5 \
+	SAM_PINMUX(c, 13, a, periph)
+
+/* pc13c_sercom7_pad1 */
+#define PC13C_SERCOM7_PAD1 \
+	SAM_PINMUX(c, 13, c, periph)
+
+/* pc14_gpio */
+#define PC14_GPIO \
+	SAM_PINMUX(c, 14, gpio, gpio)
+
+/* pc14a_eic_extint6 */
+#define PC14A_EIC_EXTINT6 \
+	SAM_PINMUX(c, 14, a, periph)
+
+/* pc14c_sercom7_pad2 */
+#define PC14C_SERCOM7_PAD2 \
+	SAM_PINMUX(c, 14, c, periph)
+
+/* pc15_gpio */
+#define PC15_GPIO \
+	SAM_PINMUX(c, 15, gpio, gpio)
+
+/* pc15a_eic_extint7 */
+#define PC15A_EIC_EXTINT7 \
+	SAM_PINMUX(c, 15, a, periph)
+
+/* pc15c_sercom7_pad3 */
+#define PC15C_SERCOM7_PAD3 \
+	SAM_PINMUX(c, 15, c, periph)
+
+/* pc16_gpio */
+#define PC16_GPIO \
+	SAM_PINMUX(c, 16, gpio, gpio)
+
+/* pc16a_eic_extint8 */
+#define PC16A_EIC_EXTINT8 \
+	SAM_PINMUX(c, 16, a, periph)
+
+/* pc16c_sercom6_pad0 */
+#define PC16C_SERCOM6_PAD0 \
+	SAM_PINMUX(c, 16, c, periph)
+
+/* pc17_gpio */
+#define PC17_GPIO \
+	SAM_PINMUX(c, 17, gpio, gpio)
+
+/* pc17a_eic_extint9 */
+#define PC17A_EIC_EXTINT9 \
+	SAM_PINMUX(c, 17, a, periph)
+
+/* pc17c_sercom6_pad1 */
+#define PC17C_SERCOM6_PAD1 \
+	SAM_PINMUX(c, 17, c, periph)
+
+/* pc18_gpio */
+#define PC18_GPIO \
+	SAM_PINMUX(c, 18, gpio, gpio)
+
+/* pc18a_eic_extint10 */
+#define PC18A_EIC_EXTINT10 \
+	SAM_PINMUX(c, 18, a, periph)
+
+/* pc18c_sercom6_pad2 */
+#define PC18C_SERCOM6_PAD2 \
+	SAM_PINMUX(c, 18, c, periph)
+
+/* pc19_gpio */
+#define PC19_GPIO \
+	SAM_PINMUX(c, 19, gpio, gpio)
+
+/* pc19a_eic_extint11 */
+#define PC19A_EIC_EXTINT11 \
+	SAM_PINMUX(c, 19, a, periph)
+
+/* pc19c_sercom6_pad3 */
+#define PC19C_SERCOM6_PAD3 \
+	SAM_PINMUX(c, 19, c, periph)
+
+/* pc20_gpio */
+#define PC20_GPIO \
+	SAM_PINMUX(c, 20, gpio, gpio)
+
+/* pc20a_eic_extint12 */
+#define PC20A_EIC_EXTINT12 \
+	SAM_PINMUX(c, 20, a, periph)
+
+/* pc21_gpio */
+#define PC21_GPIO \
+	SAM_PINMUX(c, 21, gpio, gpio)
+
+/* pc21a_eic_extint13 */
+#define PC21A_EIC_EXTINT13 \
+	SAM_PINMUX(c, 21, a, periph)
+
+/* pc24_gpio */
+#define PC24_GPIO \
+	SAM_PINMUX(c, 24, gpio, gpio)
+
+/* pc24a_eic_extint0 */
+#define PC24A_EIC_EXTINT0 \
+	SAM_PINMUX(c, 24, a, periph)
+
+/* pc24c_sercom0_pad2 */
+#define PC24C_SERCOM0_PAD2 \
+	SAM_PINMUX(c, 24, c, periph)
+
+/* pc24d_sercom4_pad2 */
+#define PC24D_SERCOM4_PAD2 \
+	SAM_PINMUX(c, 24, d, periph)
+
+/* pc25_gpio */
+#define PC25_GPIO \
+	SAM_PINMUX(c, 25, gpio, gpio)
+
+/* pc25a_eic_extint1 */
+#define PC25A_EIC_EXTINT1 \
+	SAM_PINMUX(c, 25, a, periph)
+
+/* pc25c_sercom0_pad3 */
+#define PC25C_SERCOM0_PAD3 \
+	SAM_PINMUX(c, 25, c, periph)
+
+/* pc25d_sercom4_pad3 */
+#define PC25D_SERCOM4_PAD3 \
+	SAM_PINMUX(c, 25, d, periph)
+
+/* pc26_gpio */
+#define PC26_GPIO \
+	SAM_PINMUX(c, 26, gpio, gpio)
+
+/* pc26a_eic_extint2 */
+#define PC26A_EIC_EXTINT2 \
+	SAM_PINMUX(c, 26, a, periph)
+
+/* pc27_gpio */
+#define PC27_GPIO \
+	SAM_PINMUX(c, 27, gpio, gpio)
+
+/* pc27a_eic_extint3 */
+#define PC27A_EIC_EXTINT3 \
+	SAM_PINMUX(c, 27, a, periph)
+
+/* pc27d_sercom1_pad0 */
+#define PC27D_SERCOM1_PAD0 \
+	SAM_PINMUX(c, 27, d, periph)
+
+/* pc28_gpio */
+#define PC28_GPIO \
+	SAM_PINMUX(c, 28, gpio, gpio)
+
+/* pc28a_eic_extint4 */
+#define PC28A_EIC_EXTINT4 \
+	SAM_PINMUX(c, 28, a, periph)
+
+/* pc28d_sercom1_pad1 */
+#define PC28D_SERCOM1_PAD1 \
+	SAM_PINMUX(c, 28, d, periph)
diff --git a/pinconfigs/sam-c2x.yml b/pinconfigs/sam-c2x.yml
new file mode 100644
index 0000000..e0465f1
--- /dev/null
+++ b/pinconfigs/sam-c2x.yml
@@ -0,0 +1,735 @@
+# Copyright (c) 2022 Kamil Serwus
+# SPDX-License-Identifier: Apache-2.0
+#
+# Sources:
+# - SAM_C20_C21_Family_Data_Sheet_DS60001479D (Revision D - 01/2020)
+#
+# Pin codes:
+#
+# - 32      pins: e
+# - 48      pins: g
+# - 64      pins: j
+# - 100     pins: n
+#
+# SoC Revision (variant) supported:
+#
+# - SAMC20
+# - A = Default Variant
+#
+# - SAMC21
+# - A = Default Variant
+
+model: atmel,sam
+
+family: c2x
+
+map: SAM_PINMUX
+
+series: [c20, c21]
+
+variants:
+  - pincode: e
+    series: [c20, c21]
+  - pincode: g
+    series: [c20, c21]
+  - pincode: j
+    series: [c20, c21]
+  - pincode: n
+    series: [c20, c21]
+
+pins:
+  pa00:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint0]
+      - [d, sercom1, pad0]
+      - [e, tc2, wo0]
+      - [h, ac, cmp2]
+  pa01:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint1]
+      - [d, sercom1, pad1]
+      - [e, tc2, wo1]
+      - [h, ac, cmp3]
+  pc00:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint8]
+      - [b, adc0, ain8]
+  pc01:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint9]
+      - [b, adc0, ain9]
+  pc02:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint10]
+      - [b, adc0, ain10]
+  pc03:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint11]
+      - [b, adc0, ain11]
+      - [c, sercom7, pad0]
+      - [f, tcc2, wo0]
+  pa02:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint2]
+      - [b, adc0, ain0]
+      - [b, ac, ain4]
+      - [b, ptc, y0]
+      - [b, dac, vout, [c20]]
+  pa03:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint3]
+      - [b, anaref, vrefa]
+      - [b, adc0, ain5]
+      - [b, ac, ain4]
+      - [b, ptc, y1]
+  pb04:
+    pincodes: [j, n]
+    periph:
+      - [a, eic, extint4]
+      - [b, adc0, ain6]
+      - [b, ptc, y10]
+  pb05:
+    pincodes: [j, n]
+    periph:
+      - [a, eic, extint5]
+      - [b, adc0, ain7]
+      - [b, ac, ain6]
+      - [b, ptc, y11]
+  pb06:
+    pincodes: [j, n]
+    periph:
+      - [a, eic, extint6]
+      - [b, adc0, ain8]
+      - [b, ac, ain7]
+      - [b, ptc, y12]
+      - [b, sdadc0, ainn2, [c20]]
+      - [c, sercom7, pad1, [j]]
+  pb07:
+    pincodes: [j, n]
+    periph:
+      - [a, eic, extint7]
+      - [b, adc0, ain9]
+      - [b, ptc, y13]
+      - [b, sdadc0, ainp2, [c20]]
+      - [c, sercom7, pad3, [j]]
+      - [d, sercom7, pad2, [j]]
+  pb08:
+    pincodes: [g, j, n]
+    periph:
+      - [a, eic, extint8]
+      - [b, adc0, ain2]
+      - [b, adc1, ain4, [c20]]
+      - [b, ptc, y14]
+      - [b, sdadc0, ainn1, [c20]]
+      - [c, sercom7, pad2, [g, j]]
+      - [d, sercom4, pad0, [n]]
+      - [d, sercom7, pad3, [g, j]]
+      - [e, tc0, wo0, [n]]
+      - [e, tc4, wo0, [g, j]]
+  pb09:
+    pincodes: [g, j, n]
+    periph:
+      - [a, eic, extint9]
+      - [b, adc0, ain3]
+      - [b, adc1, ain5, [c20]]
+      - [b, ptc, y15]
+      - [b, sdadc0, ainp1, [c20]]
+      - [d, sercom4, pad1]
+      - [e, tc0, wo1, [n]]
+      - [e, tc4, wo1, [g, j]]
+  pa04:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint4]
+      - [b, anaref, vrefb]
+      - [b, adc0, ain4]
+      - [b, ac, ain0]
+      - [b, ptc, y2]
+      - [d, sercom0, pad0]
+      - [e, tcc0, wo0, [n]]
+      - [e, tc0, wo0, [e, g, j]]
+  pa05:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint5]
+      - [b, adc0, ain5]
+      - [b, ac, ain1]
+      - [b, ptc, y3]
+      - [d, sercom0, pad1]
+      - [e, tcc0, wo1, [n]]
+      - [e, tc0, wo1, [e, g, j]]
+  pa06:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint6]
+      - [b, adc0, ain6]
+      - [b, ac, ain2]
+      - [b, ptc, y4]
+      - [b, sdadc0, ainn0, [c20]]
+      - [d, sercom0, pad2]
+      - [e, tcc1, wo0]
+  pa07:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint7]
+      - [b, adc0, ain7]
+      - [b, ac, ain3]
+      - [b, ptc, y5]
+      - [b, sdadc0, ainp0, [c20]]
+      - [d, sercom0, pad3]
+      - [e, tcc1, wo1]
+  pc05:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint13]
+      - [c, sercom6, pad3]
+      - [f, tcc2, wo1]
+  pc06:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint14]
+      - [c, sercom6, pad0]
+  pc07:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint15]
+      - [c, sercom6, pad1]
+  pa08:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, nmi]
+      - [b, adc0, ain8, [n]]
+      - [b, adc1, ain10, [c20]]
+      - [b, ptc, xy16]
+      - [c, sercom0, pad0]
+      - [d, sercom2, pad0]
+      - [e, tcc0, wo0, [n]]
+      - [e, tc0, wo0, [e, g, j]]
+      - [f, tcc1, wo2, [n]]
+      - [f, tcc0, wo0, [e, g, j]]
+  pa09:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint9]
+      - [b, adc0, ain9, [n]]
+      - [b, adc1, ain11, [c20]]
+      - [b, ptc, x1]
+      - [c, sercom0, pad1]
+      - [d, sercom2, pad1]
+      - [e, tcc0, wo1, [n]]
+      - [e, tc0, wo1, [e, g, j]]
+      - [f, tcc1, wo3, [n]]
+      - [f, tcc0, wo1, [e, g, j]]
+  pa10:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint10]
+      - [b, adc0, ain10, [n]]
+      - [b, ptc, x2]
+      - [c, sercom0, pad2]
+      - [d, sercom2, pad2]
+      - [e, tcc1, wo0, [n]]
+      - [e, tc1, wo0, [e, g, j]]
+      - [f, tcc0, wo2]
+      - [h, gclk, io4]
+  pa11:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint11]
+      - [b, adc0, ain11, [n]]
+      - [b, ptc, x3]
+      - [c, sercom0, pad3]
+      - [d, sercom2, pad3]
+      - [e, tcc1, wo1, [n]]
+      - [e, tc1, wo1, [e, g, j]]
+      - [f, tcc0, wo3]
+      - [h, gclk, io5]
+  pb10:
+    pincodes: [g, j, n]
+    periph:
+      - [a, eic, extint10]
+      - [d, sercom4, pad2]
+      - [e, tc1, wo0, [n]]
+      - [e, tc5, wo0, [g, j]]
+      - [f, tcc0, wo4]
+      - [g, can1, tx, [c20, n]]
+      - [h, gclk, io4]
+  pb11:
+    pincodes: [g, j, n]
+    periph:
+      - [a, eic, extint11]
+      - [d, sercom4, pad3]
+      - [e, tc1, wo1, [n]]
+      - [e, tc5, wo1, [g, j]]
+      - [f, tcc0, wo5]
+      - [g, can1, rx, [c20, n]]
+      - [h, gclk, io5]
+  pb12:
+    pincodes: [j, n]
+    periph:
+      - [a, eic, extint12]
+      - [b, ptc, x12]
+      - [c, sercom4, pad0]
+      - [e, tc0, wo0, [n]]
+      - [e, tc4, wo0, [j]]
+      - [f, tcc0, wo6]
+      - [g, can1, tx, [c20, j]]
+      - [h, gclk, io6]
+  pb13:
+    pincodes: [j, n]
+    periph:
+      - [a, eic, extint13]
+      - [b, ptc, x13]
+      - [c, sercom4, pad1]
+      - [e, tc0, wo1, [n]]
+      - [e, tc4, wo1, [j]]
+      - [f, tcc0, wo7]
+      - [g, can1, rx, [c20, j]]
+      - [h, gclk, io7]
+  pb14:
+    pincodes: [j, n]
+    periph:
+      - [a, eic, extint14]
+      - [b, ptc, x14]
+      - [c, sercom4, pad2]
+      - [e, tc1, wo0, [n]]
+      - [e, tc5, wo0, [j]]
+      - [g, can1, tx, [c20]]
+      - [h, gclk, io0]
+  pb15:
+    pincodes: [j, n]
+    periph:
+      - [a, eic, extint15]
+      - [b, ptc, x15]
+      - [c, sercom4, pad3]
+      - [e, tc1, wo1, [n]]
+      - [e, tc5, wo1, [j]]
+      - [g, can1, rx, [c20]]
+      - [h, gclk, io1]
+  pc08:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint0]
+      - [c, sercom6, pad0]
+      - [d, sercom7, pad0]
+  pc09:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint1]
+      - [c, sercom6, pad1]
+      - [d, sercom7, pad1]
+  pc10:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint2]
+      - [c, sercom6, pad2]
+      - [d, sercom7, pad2]
+  pc11:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint3]
+      - [c, sercom6, pad3]
+      - [d, sercom7, pad3]
+  pc12:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint4]
+      - [c, sercom7, pad0]
+  pc13:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint5]
+      - [c, sercom7, pad1]  
+  pc14:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint6]
+      - [c, sercom7, pad2]
+  pc15:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint7]
+      - [c, sercom7, pad3]
+  pa12:
+    pincodes: [g, j, n]
+    periph:
+      - [a, eic, extint12]
+      - [c, sercom2, pad0]
+      - [d, sercom4, pad0]
+      - [e, tcc2, wo0]
+      - [f, tcc0, wo6]
+      - [h, ac, cmp0]
+  pa13:
+    pincodes: [g, j, n]
+    periph:
+      - [a, eic, extint13]
+      - [c, sercom2, pad1]
+      - [d, sercom4, pad1]
+      - [e, tcc2, wo1]
+      - [f, tcc0, wo7]
+      - [h, ac, cmp1]
+  pa14:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint14]
+      - [c, sercom2, pad2]
+      - [d, sercom4, pad2]
+      - [e, tc4, wo0, [n]]
+      - [e, tc3, wo0, [e, g, j]]
+      - [f, tcc0, wo4, [n]]
+      - [h, gclk, io0]
+  pa15:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint15]
+      - [c, sercom2, pad3]
+      - [d, sercom4, pad3]
+      - [e, tc4, wo1, [n]]
+      - [e, tc3, wo1, [e, g, j]]
+      - [f, tcc0, wo5, [n]]
+      - [h, gclk, io1]
+  pa16:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint0]
+      - [b, ptc, x4]
+      - [c, sercom1, pad0]
+      - [d, sercom3, pad0]
+      - [e, tcc2, wo0]
+      - [f, tcc0, wo6, [n]]
+      - [f, tcc1, wo6, [e, g, j]]
+      - [h, gclk, io2]
+  pa17:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint1]
+      - [b, ptc, x5]
+      - [c, sercom1, pad1]
+      - [d, sercom3, pad1]
+      - [e, tcc2, wo1]
+      - [f, tcc0, wo7, [n]]
+      - [f, tcc1, wo7, [e, g, j]]
+      - [h, gclk, io3]
+  pa18:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint2]
+      - [b, ptc, x6]
+      - [c, sercom1, pad2]
+      - [d, sercom3, pad2]
+      - [e, tc4, wo0, [n]]
+      - [e, tc3, wo0, [e, g, j]]
+      - [f, tcc0, wo2, [n]]
+      - [f, tcc1, wo2, [e, g, j]]
+      - [h, ac, cmp0]
+  pa19:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint3]
+      - [b, ptc, x7]
+      - [c, sercom1, pad3]
+      - [d, sercom3, pad3]
+      - [e, tc4, wo1, [n]]
+      - [e, tc3, wo1, [e, g, j]]
+      - [f, tcc0, wo3, [n]]
+      - [f, tcc1, wo3, [e, g, j]]
+      - [h, ac, cmp1]
+  pc16:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint8]
+      - [c, sercom6, pad0]
+  pc17:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint9]
+      - [c, sercom6, pad1]  
+  pc18:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint10]
+      - [c, sercom6, pad2]
+  pc19:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint11]
+      - [c, sercom6, pad3]
+  pc20:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint12]
+  pc21:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint13]
+  pb16:
+    pincodes: [j, n]
+    periph:
+      - [a, eic, extint0]
+      - [c, sercom5, pad0]
+      - [e, tc2, wo0, [n]]
+      - [e, tc6, wo0, [j]]
+      - [f, tcc0, wo4, [n]]
+      - [h, gclk, io2]
+  pb17:
+    pincodes: [j, n]
+    periph:
+      - [a, eic, extint1]
+      - [c, sercom5, pad1]
+      - [e, tc2, wo1, [n]]
+      - [e, tc6, wo1, [j]]
+      - [f, tcc0, wo5, [n]]
+      - [h, gclk, io3]
+  pb18:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint2]
+      - [c, sercom5, pad2]
+      - [d, sercom3, pad2]
+      - [h, gclk, io4]
+  pb19:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint3]
+      - [c, sercom5, pad3]
+      - [d, sercom3, pad3]
+      - [h, gclk, io5]
+  pb20:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint4]
+      - [c, sercom3, pad0]
+      - [d, sercom2, pad0]
+      - [h, gclk, io6]
+  pb21:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint5]
+      - [c, sercom3, pad1]
+      - [d, sercom2, pad2]
+      - [h, gclk, io7]
+  pa20:
+    pincodes: [g, j, n]
+    periph:
+      - [a, eic, extint4]
+      - [b, ptc, x8]
+      - [c, sercom5, pad2]
+      - [d, sercom3, pad2]
+      - [e, tc3, wo0, [n]]
+      - [e, tc7, wo0, [g, j]]
+      - [f, tcc0, wo6, [n]]
+      - [f, tcc2, wo0, [g, j]]
+      - [h, gclk, io4]
+  pa21:
+    pincodes: [g, j, n]
+    periph:
+      - [a, eic, extint5]
+      - [b, ptc, x9]
+      - [c, sercom5, pad3]
+      - [d, sercom3, pad3]
+      - [e, tc3, wo1, [n]]
+      - [e, tc7, wo1, [g, j]]
+      - [f, tcc0, wo7, [n]]
+      - [f, tcc2, wo1, [g, j]]
+      - [h, gclk, io5]
+  pa22:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint6]
+      - [b, ptc, x10]
+      - [c, sercom3, pad0]
+      - [d, sercom5, pad0]
+      - [e, tc0, wo0, [n]]
+      - [e, tc4, wo0, [e, g, j]]
+      - [f, tcc0, wo4, [n]]
+      - [f, tcc1, wo0, [e, g, j]]
+      - [g, can0, tx, [c20, e, g, j]]
+      - [h, gclk, io6]
+  pa23:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint7]
+      - [b, ptc, x11]
+      - [c, sercom3, pad1]
+      - [d, sercom5, pad1]
+      - [e, tc0, wo1, [n]]
+      - [e, tc4, wo1, [e, g, j]]
+      - [f, tcc0, wo5, [n]]
+      - [f, tcc1, wo1, [e, g, j]]
+      - [g, can0, rx, [c20, e, g, j]]
+      - [h, gclk, io7]
+  pa24:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint12]
+      - [c, sercom3, pad2]
+      - [d, sercom5, pad2]
+      - [e, tc1, wo0, [n]]
+      - [e, tc5, wo0, [e, g, j]]
+      - [f, tcc1, wo2, [n]]
+      - [f, tcc2, wo0, [e, g, j]]
+      - [g, can0, tx, [c20]]
+      - [h, ac, cmp2]
+  pa25:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint13]
+      - [c, sercom3, pad3]
+      - [d, sercom5, pad3]
+      - [e, tc1, wo1, [n]]
+      - [e, tc5, wo1, [e, g, j]]
+      - [f, tcc1, wo3, [n]]
+      - [f, tcc2, wo1, [e, g, j]]
+      - [g, can0, rx, [c20]]
+      - [h, ac, cmp3]
+  pb22:
+    pincodes: [g, j, n]
+    periph:
+      - [a, eic, extint6]
+      - [c, sercom0, pad2, [e, g, j]]
+      - [d, sercom5, pad2]
+      - [e, tc3, wo0, [n]]
+      - [e, tc7, wo0, [e, g, j]]
+      - [f, tcc1, wo2, [e, g, j]]
+      - [g, can0, tx, [c20, n]]
+      - [h, gclk, io0]
+  pb23:
+    pincodes: [g, j, n]
+    periph:
+      - [a, eic, extint7]
+      - [c, sercom0, pad3, [e, g, j]]
+      - [d, sercom5, pad3]
+      - [e, tc3, wo1, [n]]
+      - [e, tc7, wo1, [e, g, j]]
+      - [f, tcc1, wo3, [e, g, j]]
+      - [g, can0, rx, [c20, n]]
+      - [h, gclk, io1]
+  pb24:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint7]
+      - [c, sercom0, pad0]
+      - [d, sercom4, pad0]
+      - [h, ac, cmp0]
+  pb25:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint8]
+      - [c, sercom0, pad1]
+      - [d, sercom4, pad1]
+      - [h, ac, cmp1]
+  pc24:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint0]
+      - [c, sercom0, pad2]
+      - [d, sercom4, pad2]
+  pc25:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint1]
+      - [c, sercom0, pad3]  
+      - [d, sercom4, pad3]  
+  pc26:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint2]
+  pc27:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint3]
+      - [d, sercom1, pad0]
+  pc28:
+    pincodes: [n]
+    periph:
+      - [a, eic, extint4]
+      - [d, sercom1, pad1]    
+  pa27:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint15]
+      - [h, gclk, io0]
+  pa28:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint8]
+      - [h, gclk, io0]
+  pa30:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint10]
+      - [d, sercom1, pad2]
+      - [e, tcc1, wo0, [n]]
+      - [e, tc1, wo0, [e, g, j]]
+      - [g, swd, clk]
+      - [h, gclk, io0]
+  pa31:
+    pincodes: [e, g, j, n]
+    periph:
+      - [a, eic, extint11]
+      - [d, sercom1, pad3]
+      - [e, tcc1, wo1, [n]]
+      - [e, tc1, wo1, [e, g, j]]
+      - [g, swd, io]
+  pb30:
+    pincodes: [j, n]
+    periph:
+      - [a, eic, extint14]
+      - [d, sercom5, pad0]
+      - [e, tcc0, wo0, [n]]
+      - [e, tc0, wo0, [j]]
+      - [f, tcc1, wo2, [n]]
+      - [h, ac, cmp2]
+  pb31:
+    pincodes: [j, n]
+    periph:
+      - [a, eic, extint15]
+      - [d, sercom5, pad1]
+      - [e, tcc0, wo1, [n]]
+      - [e, tc0, wo1, [j]]
+      - [f, tcc1, wo3, [n]]
+      - [h, ac, cmp3]
+  pb00:
+    pincodes: [j, n]
+    periph:
+      - [a, eic, extint0]
+      - [b, adc1, ain0, [c20]]
+      - [b, ptc, y6]
+      - [d, sercom5, pad2]
+      - [e, tc3, wo0, [n]]
+      - [e, tc7, wo0, [j]]
+  pb01:
+    pincodes: [j, n]
+    periph:
+      - [a, eic, extint1]
+      - [b, adc1, ain1, [c20]]
+      - [b, ptc, y7]
+      - [d, sercom5, pad3]
+      - [e, tc3, wo1, [n]]
+      - [e, tc7, wo1, [j]]
+  pb02:
+    pincodes: [g, j, n]
+    periph:
+      - [a, eic, extint2]
+      - [b, adc1, ain2, [c20]]
+      - [b, ptc, y8]
+      - [d, sercom5, pad0]
+      - [e, tc2, wo0, [n]]
+      - [e, tc6, wo0, [g, j]]
+  pb03:
+    pincodes: [g, j, n]
+    periph:
+      - [a, eic, extint3]
+      - [b, adc1, ain3, [c20]]
+      - [b, ptc, y9]
+      - [d, sercom5, pad1]
+      - [e, tc2, wo1, [n]]
+      - [e, tc6, wo1, [g, j]]