pinctrl: sam-c2x: Add pinconfigs and include files

Add Atmel SAM0 C20/C21 family of pinconfigs definitions and auto
generated files to be used in pinctrl devicetree files.

Signed-off-by: Kamil Serwus <kserwus@gmail.com>
master
Kamil Serwus 4 months ago committed by Gerson Fernando Budke
parent 3eaaa0b581
commit ffe91910e5

@ -0,0 +1,715 @@
/*
* Autogenerated file
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <dt-bindings/pinctrl/atmel_sam_pinctrl.h>
/* pa0_gpio */
#define PA0_GPIO \
SAM_PINMUX(a, 0, gpio, gpio)
/* pa0a_eic_extint0 */
#define PA0A_EIC_EXTINT0 \
SAM_PINMUX(a, 0, a, periph)
/* pa0d_sercom1_pad0 */
#define PA0D_SERCOM1_PAD0 \
SAM_PINMUX(a, 0, d, periph)
/* pa0e_tc2_wo0 */
#define PA0E_TC2_WO0 \
SAM_PINMUX(a, 0, e, periph)
/* pa0h_ac_cmp2 */
#define PA0H_AC_CMP2 \
SAM_PINMUX(a, 0, h, periph)
/* pa1_gpio */
#define PA1_GPIO \
SAM_PINMUX(a, 1, gpio, gpio)
/* pa1a_eic_extint1 */
#define PA1A_EIC_EXTINT1 \
SAM_PINMUX(a, 1, a, periph)
/* pa1d_sercom1_pad1 */
#define PA1D_SERCOM1_PAD1 \
SAM_PINMUX(a, 1, d, periph)
/* pa1e_tc2_wo1 */
#define PA1E_TC2_WO1 \
SAM_PINMUX(a, 1, e, periph)
/* pa1h_ac_cmp3 */
#define PA1H_AC_CMP3 \
SAM_PINMUX(a, 1, h, periph)
/* pa2_gpio */
#define PA2_GPIO \
SAM_PINMUX(a, 2, gpio, gpio)
/* pa2a_eic_extint2 */
#define PA2A_EIC_EXTINT2 \
SAM_PINMUX(a, 2, a, periph)
/* pa2b_adc0_ain0 */
#define PA2B_ADC0_AIN0 \
SAM_PINMUX(a, 2, b, periph)
/* pa2b_ac_ain4 */
#define PA2B_AC_AIN4 \
SAM_PINMUX(a, 2, b, periph)
/* pa2b_ptc_y0 */
#define PA2B_PTC_Y0 \
SAM_PINMUX(a, 2, b, periph)
/* pa3_gpio */
#define PA3_GPIO \
SAM_PINMUX(a, 3, gpio, gpio)
/* pa3a_eic_extint3 */
#define PA3A_EIC_EXTINT3 \
SAM_PINMUX(a, 3, a, periph)
/* pa3b_anaref_vrefa */
#define PA3B_ANAREF_VREFA \
SAM_PINMUX(a, 3, b, periph)
/* pa3b_adc0_ain5 */
#define PA3B_ADC0_AIN5 \
SAM_PINMUX(a, 3, b, periph)
/* pa3b_ac_ain4 */
#define PA3B_AC_AIN4 \
SAM_PINMUX(a, 3, b, periph)
/* pa3b_ptc_y1 */
#define PA3B_PTC_Y1 \
SAM_PINMUX(a, 3, b, periph)
/* pa4_gpio */
#define PA4_GPIO \
SAM_PINMUX(a, 4, gpio, gpio)
/* pa4a_eic_extint4 */
#define PA4A_EIC_EXTINT4 \
SAM_PINMUX(a, 4, a, periph)
/* pa4b_anaref_vrefb */
#define PA4B_ANAREF_VREFB \
SAM_PINMUX(a, 4, b, periph)
/* pa4b_adc0_ain4 */
#define PA4B_ADC0_AIN4 \
SAM_PINMUX(a, 4, b, periph)
/* pa4b_ac_ain0 */
#define PA4B_AC_AIN0 \
SAM_PINMUX(a, 4, b, periph)
/* pa4b_ptc_y2 */
#define PA4B_PTC_Y2 \
SAM_PINMUX(a, 4, b, periph)
/* pa4d_sercom0_pad0 */
#define PA4D_SERCOM0_PAD0 \
SAM_PINMUX(a, 4, d, periph)
/* pa4e_tcc0_wo0 */
#define PA4E_TCC0_WO0 \
SAM_PINMUX(a, 4, e, periph)
/* pa5_gpio */
#define PA5_GPIO \
SAM_PINMUX(a, 5, gpio, gpio)
/* pa5a_eic_extint5 */
#define PA5A_EIC_EXTINT5 \
SAM_PINMUX(a, 5, a, periph)
/* pa5b_adc0_ain5 */
#define PA5B_ADC0_AIN5 \
SAM_PINMUX(a, 5, b, periph)
/* pa5b_ac_ain1 */
#define PA5B_AC_AIN1 \
SAM_PINMUX(a, 5, b, periph)
/* pa5b_ptc_y3 */
#define PA5B_PTC_Y3 \
SAM_PINMUX(a, 5, b, periph)
/* pa5d_sercom0_pad1 */
#define PA5D_SERCOM0_PAD1 \
SAM_PINMUX(a, 5, d, periph)
/* pa5e_tcc0_wo1 */
#define PA5E_TCC0_WO1 \
SAM_PINMUX(a, 5, e, periph)
/* pa6_gpio */
#define PA6_GPIO \
SAM_PINMUX(a, 6, gpio, gpio)
/* pa6a_eic_extint6 */
#define PA6A_EIC_EXTINT6 \
SAM_PINMUX(a, 6, a, periph)
/* pa6b_adc0_ain6 */
#define PA6B_ADC0_AIN6 \
SAM_PINMUX(a, 6, b, periph)
/* pa6b_ac_ain2 */
#define PA6B_AC_AIN2 \
SAM_PINMUX(a, 6, b, periph)
/* pa6b_ptc_y4 */
#define PA6B_PTC_Y4 \
SAM_PINMUX(a, 6, b, periph)
/* pa6d_sercom0_pad2 */
#define PA6D_SERCOM0_PAD2 \
SAM_PINMUX(a, 6, d, periph)
/* pa6e_tcc1_wo0 */
#define PA6E_TCC1_WO0 \
SAM_PINMUX(a, 6, e, periph)
/* pa7_gpio */
#define PA7_GPIO \
SAM_PINMUX(a, 7, gpio, gpio)
/* pa7a_eic_extint7 */
#define PA7A_EIC_EXTINT7 \
SAM_PINMUX(a, 7, a, periph)
/* pa7b_adc0_ain7 */
#define PA7B_ADC0_AIN7 \
SAM_PINMUX(a, 7, b, periph)
/* pa7b_ac_ain3 */
#define PA7B_AC_AIN3 \
SAM_PINMUX(a, 7, b, periph)
/* pa7b_ptc_y5 */
#define PA7B_PTC_Y5 \
SAM_PINMUX(a, 7, b, periph)
/* pa7d_sercom0_pad3 */
#define PA7D_SERCOM0_PAD3 \
SAM_PINMUX(a, 7, d, periph)
/* pa7e_tcc1_wo1 */
#define PA7E_TCC1_WO1 \
SAM_PINMUX(a, 7, e, periph)
/* pa8_gpio */
#define PA8_GPIO \
SAM_PINMUX(a, 8, gpio, gpio)
/* pa8a_eic_nmi */
#define PA8A_EIC_NMI \
SAM_PINMUX(a, 8, a, periph)
/* pa8b_adc0_ain8 */
#define PA8B_ADC0_AIN8 \
SAM_PINMUX(a, 8, b, periph)
/* pa8b_ptc_xy16 */
#define PA8B_PTC_XY16 \
SAM_PINMUX(a, 8, b, periph)
/* pa8c_sercom0_pad0 */
#define PA8C_SERCOM0_PAD0 \
SAM_PINMUX(a, 8, c, periph)
/* pa8d_sercom2_pad0 */
#define PA8D_SERCOM2_PAD0 \
SAM_PINMUX(a, 8, d, periph)
/* pa8e_tcc0_wo0 */
#define PA8E_TCC0_WO0 \
SAM_PINMUX(a, 8, e, periph)
/* pa8f_tcc1_wo2 */
#define PA8F_TCC1_WO2 \
SAM_PINMUX(a, 8, f, periph)
/* pa9_gpio */
#define PA9_GPIO \
SAM_PINMUX(a, 9, gpio, gpio)
/* pa9a_eic_extint9 */
#define PA9A_EIC_EXTINT9 \
SAM_PINMUX(a, 9, a, periph)
/* pa9b_adc0_ain9 */
#define PA9B_ADC0_AIN9 \
SAM_PINMUX(a, 9, b, periph)
/* pa9b_ptc_x1 */
#define PA9B_PTC_X1 \
SAM_PINMUX(a, 9, b, periph)
/* pa9c_sercom0_pad1 */
#define PA9C_SERCOM0_PAD1 \
SAM_PINMUX(a, 9, c, periph)
/* pa9d_sercom2_pad1 */
#define PA9D_SERCOM2_PAD1 \
SAM_PINMUX(a, 9, d, periph)
/* pa9e_tcc0_wo1 */
#define PA9E_TCC0_WO1 \
SAM_PINMUX(a, 9, e, periph)
/* pa9f_tcc1_wo3 */
#define PA9F_TCC1_WO3 \
SAM_PINMUX(a, 9, f, periph)
/* pa10_gpio */
#define PA10_GPIO \
SAM_PINMUX(a, 10, gpio, gpio)
/* pa10a_eic_extint10 */
#define PA10A_EIC_EXTINT10 \
SAM_PINMUX(a, 10, a, periph)
/* pa10b_adc0_ain10 */
#define PA10B_ADC0_AIN10 \
SAM_PINMUX(a, 10, b, periph)
/* pa10b_ptc_x2 */
#define PA10B_PTC_X2 \
SAM_PINMUX(a, 10, b, periph)
/* pa10c_sercom0_pad2 */
#define PA10C_SERCOM0_PAD2 \
SAM_PINMUX(a, 10, c, periph)
/* pa10d_sercom2_pad2 */
#define PA10D_SERCOM2_PAD2 \
SAM_PINMUX(a, 10, d, periph)
/* pa10e_tcc1_wo0 */
#define PA10E_TCC1_WO0 \
SAM_PINMUX(a, 10, e, periph)
/* pa10f_tcc0_wo2 */
#define PA10F_TCC0_WO2 \
SAM_PINMUX(a, 10, f, periph)
/* pa10h_gclk_io4 */
#define PA10H_GCLK_IO4 \
SAM_PINMUX(a, 10, h, periph)
/* pa11_gpio */
#define PA11_GPIO \
SAM_PINMUX(a, 11, gpio, gpio)
/* pa11a_eic_extint11 */
#define PA11A_EIC_EXTINT11 \
SAM_PINMUX(a, 11, a, periph)
/* pa11b_adc0_ain11 */
#define PA11B_ADC0_AIN11 \
SAM_PINMUX(a, 11, b, periph)
/* pa11b_ptc_x3 */
#define PA11B_PTC_X3 \
SAM_PINMUX(a, 11, b, periph)
/* pa11c_sercom0_pad3 */
#define PA11C_SERCOM0_PAD3 \
SAM_PINMUX(a, 11, c, periph)
/* pa11d_sercom2_pad3 */
#define PA11D_SERCOM2_PAD3 \
SAM_PINMUX(a, 11, d, periph)
/* pa11e_tcc1_wo1 */
#define PA11E_TCC1_WO1 \
SAM_PINMUX(a, 11, e, periph)
/* pa11f_tcc0_wo3 */
#define PA11F_TCC0_WO3 \
SAM_PINMUX(a, 11, f, periph)
/* pa11h_gclk_io5 */
#define PA11H_GCLK_IO5 \
SAM_PINMUX(a, 11, h, periph)
/* pa14_gpio */
#define PA14_GPIO \
SAM_PINMUX(a, 14, gpio, gpio)
/* pa14a_eic_extint14 */
#define PA14A_EIC_EXTINT14 \
SAM_PINMUX(a, 14, a, periph)
/* pa14c_sercom2_pad2 */
#define PA14C_SERCOM2_PAD2 \
SAM_PINMUX(a, 14, c, periph)
/* pa14d_sercom4_pad2 */
#define PA14D_SERCOM4_PAD2 \
SAM_PINMUX(a, 14, d, periph)
/* pa14e_tc4_wo0 */
#define PA14E_TC4_WO0 \
SAM_PINMUX(a, 14, e, periph)
/* pa14f_tcc0_wo4 */
#define PA14F_TCC0_WO4 \
SAM_PINMUX(a, 14, f, periph)
/* pa14h_gclk_io0 */
#define PA14H_GCLK_IO0 \
SAM_PINMUX(a, 14, h, periph)
/* pa15_gpio */
#define PA15_GPIO \
SAM_PINMUX(a, 15, gpio, gpio)
/* pa15a_eic_extint15 */
#define PA15A_EIC_EXTINT15 \
SAM_PINMUX(a, 15, a, periph)
/* pa15c_sercom2_pad3 */
#define PA15C_SERCOM2_PAD3 \
SAM_PINMUX(a, 15, c, periph)
/* pa15d_sercom4_pad3 */
#define PA15D_SERCOM4_PAD3 \
SAM_PINMUX(a, 15, d, periph)
/* pa15e_tc4_wo1 */
#define PA15E_TC4_WO1 \
SAM_PINMUX(a, 15, e, periph)
/* pa15f_tcc0_wo5 */
#define PA15F_TCC0_WO5 \
SAM_PINMUX(a, 15, f, periph)
/* pa15h_gclk_io1 */
#define PA15H_GCLK_IO1 \
SAM_PINMUX(a, 15, h, periph)
/* pa16_gpio */
#define PA16_GPIO \
SAM_PINMUX(a, 16, gpio, gpio)
/* pa16a_eic_extint0 */
#define PA16A_EIC_EXTINT0 \
SAM_PINMUX(a, 16, a, periph)
/* pa16b_ptc_x4 */
#define PA16B_PTC_X4 \
SAM_PINMUX(a, 16, b, periph)
/* pa16c_sercom1_pad0 */
#define PA16C_SERCOM1_PAD0 \
SAM_PINMUX(a, 16, c, periph)
/* pa16d_sercom3_pad0 */
#define PA16D_SERCOM3_PAD0 \
SAM_PINMUX(a, 16, d, periph)
/* pa16e_tcc2_wo0 */
#define PA16E_TCC2_WO0 \
SAM_PINMUX(a, 16, e, periph)
/* pa16f_tcc0_wo6 */
#define PA16F_TCC0_WO6 \
SAM_PINMUX(a, 16, f, periph)
/* pa16h_gclk_io2 */
#define PA16H_GCLK_IO2 \
SAM_PINMUX(a, 16, h, periph)
/* pa17_gpio */
#define PA17_GPIO \
SAM_PINMUX(a, 17, gpio, gpio)
/* pa17a_eic_extint1 */
#define PA17A_EIC_EXTINT1 \
SAM_PINMUX(a, 17, a, periph)
/* pa17b_ptc_x5 */
#define PA17B_PTC_X5 \
SAM_PINMUX(a, 17, b, periph)
/* pa17c_sercom1_pad1 */
#define PA17C_SERCOM1_PAD1 \
SAM_PINMUX(a, 17, c, periph)
/* pa17d_sercom3_pad1 */
#define PA17D_SERCOM3_PAD1 \
SAM_PINMUX(a, 17, d, periph)
/* pa17e_tcc2_wo1 */
#define PA17E_TCC2_WO1 \
SAM_PINMUX(a, 17, e, periph)
/* pa17f_tcc0_wo7 */
#define PA17F_TCC0_WO7 \
SAM_PINMUX(a, 17, f, periph)
/* pa17h_gclk_io3 */
#define PA17H_GCLK_IO3 \
SAM_PINMUX(a, 17, h, periph)
/* pa18_gpio */
#define PA18_GPIO \
SAM_PINMUX(a, 18, gpio, gpio)
/* pa18a_eic_extint2 */
#define PA18A_EIC_EXTINT2 \
SAM_PINMUX(a, 18, a, periph)
/* pa18b_ptc_x6 */
#define PA18B_PTC_X6 \
SAM_PINMUX(a, 18, b, periph)
/* pa18c_sercom1_pad2 */
#define PA18C_SERCOM1_PAD2 \
SAM_PINMUX(a, 18, c, periph)
/* pa18d_sercom3_pad2 */
#define PA18D_SERCOM3_PAD2 \
SAM_PINMUX(a, 18, d, periph)
/* pa18e_tc4_wo0 */
#define PA18E_TC4_WO0 \
SAM_PINMUX(a, 18, e, periph)
/* pa18f_tcc0_wo2 */
#define PA18F_TCC0_WO2 \
SAM_PINMUX(a, 18, f, periph)
/* pa18h_ac_cmp0 */
#define PA18H_AC_CMP0 \
SAM_PINMUX(a, 18, h, periph)
/* pa19_gpio */
#define PA19_GPIO \
SAM_PINMUX(a, 19, gpio, gpio)
/* pa19a_eic_extint3 */
#define PA19A_EIC_EXTINT3 \
SAM_PINMUX(a, 19, a, periph)
/* pa19b_ptc_x7 */
#define PA19B_PTC_X7 \
SAM_PINMUX(a, 19, b, periph)
/* pa19c_sercom1_pad3 */
#define PA19C_SERCOM1_PAD3 \
SAM_PINMUX(a, 19, c, periph)
/* pa19d_sercom3_pad3 */
#define PA19D_SERCOM3_PAD3 \
SAM_PINMUX(a, 19, d, periph)
/* pa19e_tc4_wo1 */
#define PA19E_TC4_WO1 \
SAM_PINMUX(a, 19, e, periph)
/* pa19f_tcc0_wo3 */
#define PA19F_TCC0_WO3 \
SAM_PINMUX(a, 19, f, periph)
/* pa19h_ac_cmp1 */
#define PA19H_AC_CMP1 \
SAM_PINMUX(a, 19, h, periph)
/* pa22_gpio */
#define PA22_GPIO \
SAM_PINMUX(a, 22, gpio, gpio)
/* pa22a_eic_extint6 */
#define PA22A_EIC_EXTINT6 \
SAM_PINMUX(a, 22, a, periph)
/* pa22b_ptc_x10 */
#define PA22B_PTC_X10 \
SAM_PINMUX(a, 22, b, periph)
/* pa22c_sercom3_pad0 */
#define PA22C_SERCOM3_PAD0 \
SAM_PINMUX(a, 22, c, periph)
/* pa22d_sercom5_pad0 */
#define PA22D_SERCOM5_PAD0 \
SAM_PINMUX(a, 22, d, periph)
/* pa22e_tc0_wo0 */
#define PA22E_TC0_WO0 \
SAM_PINMUX(a, 22, e, periph)
/* pa22f_tcc0_wo4 */
#define PA22F_TCC0_WO4 \
SAM_PINMUX(a, 22, f, periph)
/* pa22h_gclk_io6 */
#define PA22H_GCLK_IO6 \
SAM_PINMUX(a, 22, h, periph)
/* pa23_gpio */
#define PA23_GPIO \
SAM_PINMUX(a, 23, gpio, gpio)
/* pa23a_eic_extint7 */
#define PA23A_EIC_EXTINT7 \
SAM_PINMUX(a, 23, a, periph)
/* pa23b_ptc_x11 */
#define PA23B_PTC_X11 \
SAM_PINMUX(a, 23, b, periph)
/* pa23c_sercom3_pad1 */
#define PA23C_SERCOM3_PAD1 \
SAM_PINMUX(a, 23, c, periph)
/* pa23d_sercom5_pad1 */
#define PA23D_SERCOM5_PAD1 \
SAM_PINMUX(a, 23, d, periph)
/* pa23e_tc0_wo1 */
#define PA23E_TC0_WO1 \
SAM_PINMUX(a, 23, e, periph)
/* pa23f_tcc0_wo5 */
#define PA23F_TCC0_WO5 \
SAM_PINMUX(a, 23, f, periph)
/* pa23h_gclk_io7 */
#define PA23H_GCLK_IO7 \
SAM_PINMUX(a, 23, h, periph)
/* pa24_gpio */
#define PA24_GPIO \
SAM_PINMUX(a, 24, gpio, gpio)
/* pa24a_eic_extint12 */
#define PA24A_EIC_EXTINT12 \
SAM_PINMUX(a, 24, a, periph)
/* pa24c_sercom3_pad2 */
#define PA24C_SERCOM3_PAD2 \
SAM_PINMUX(a, 24, c, periph)
/* pa24d_sercom5_pad2 */
#define PA24D_SERCOM5_PAD2 \
SAM_PINMUX(a, 24, d, periph)
/* pa24e_tc1_wo0 */
#define PA24E_TC1_WO0 \
SAM_PINMUX(a, 24, e, periph)
/* pa24f_tcc1_wo2 */
#define PA24F_TCC1_WO2 \
SAM_PINMUX(a, 24, f, periph)
/* pa24h_ac_cmp2 */
#define PA24H_AC_CMP2 \
SAM_PINMUX(a, 24, h, periph)
/* pa25_gpio */
#define PA25_GPIO \
SAM_PINMUX(a, 25, gpio, gpio)
/* pa25a_eic_extint13 */
#define PA25A_EIC_EXTINT13 \
SAM_PINMUX(a, 25, a, periph)
/* pa25c_sercom3_pad3 */
#define PA25C_SERCOM3_PAD3 \
SAM_PINMUX(a, 25, c, periph)
/* pa25d_sercom5_pad3 */
#define PA25D_SERCOM5_PAD3 \
SAM_PINMUX(a, 25, d, periph)
/* pa25e_tc1_wo1 */
#define PA25E_TC1_WO1 \
SAM_PINMUX(a, 25, e, periph)
/* pa25f_tcc1_wo3 */
#define PA25F_TCC1_WO3 \
SAM_PINMUX(a, 25, f, periph)
/* pa25h_ac_cmp3 */
#define PA25H_AC_CMP3 \
SAM_PINMUX(a, 25, h, periph)
/* pa27_gpio */
#define PA27_GPIO \
SAM_PINMUX(a, 27, gpio, gpio)
/* pa27a_eic_extint15 */
#define PA27A_EIC_EXTINT15 \
SAM_PINMUX(a, 27, a, periph)
/* pa27h_gclk_io0 */
#define PA27H_GCLK_IO0 \
SAM_PINMUX(a, 27, h, periph)
/* pa28_gpio */
#define PA28_GPIO \
SAM_PINMUX(a, 28, gpio, gpio)
/* pa28a_eic_extint8 */
#define PA28A_EIC_EXTINT8 \
SAM_PINMUX(a, 28, a, periph)
/* pa28h_gclk_io0 */
#define PA28H_GCLK_IO0 \
SAM_PINMUX(a, 28, h, periph)
/* pa30_gpio */
#define PA30_GPIO \
SAM_PINMUX(a, 30, gpio, gpio)
/* pa30a_eic_extint10 */
#define PA30A_EIC_EXTINT10 \
SAM_PINMUX(a, 30, a, periph)
/* pa30d_sercom1_pad2 */
#define PA30D_SERCOM1_PAD2 \
SAM_PINMUX(a, 30, d, periph)
/* pa30e_tcc1_wo0 */
#define PA30E_TCC1_WO0 \
SAM_PINMUX(a, 30, e, periph)
/* pa30g_swd_clk */
#define PA30G_SWD_CLK \
SAM_PINMUX(a, 30, g, periph)
/* pa30h_gclk_io0 */
#define PA30H_GCLK_IO0 \
SAM_PINMUX(a, 30, h, periph)
/* pa31_gpio */
#define PA31_GPIO \
SAM_PINMUX(a, 31, gpio, gpio)
/* pa31a_eic_extint11 */
#define PA31A_EIC_EXTINT11 \
SAM_PINMUX(a, 31, a, periph)
/* pa31d_sercom1_pad3 */
#define PA31D_SERCOM1_PAD3 \
SAM_PINMUX(a, 31, d, periph)
/* pa31e_tcc1_wo1 */
#define PA31E_TCC1_WO1 \
SAM_PINMUX(a, 31, e, periph)
/* pa31g_swd_io */
#define PA31G_SWD_IO \
SAM_PINMUX(a, 31, g, periph)

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/*
* Autogenerated file
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <dt-bindings/pinctrl/atmel_sam_pinctrl.h>
/* pa0_gpio */
#define PA0_GPIO \
SAM_PINMUX(a, 0, gpio, gpio)
/* pa0a_eic_extint0 */
#define PA0A_EIC_EXTINT0 \
SAM_PINMUX(a, 0, a, periph)
/* pa0d_sercom1_pad0 */
#define PA0D_SERCOM1_PAD0 \
SAM_PINMUX(a, 0, d, periph)
/* pa0e_tc2_wo0 */
#define PA0E_TC2_WO0 \
SAM_PINMUX(a, 0, e, periph)
/* pa0h_ac_cmp2 */
#define PA0H_AC_CMP2 \
SAM_PINMUX(a, 0, h, periph)
/* pa1_gpio */
#define PA1_GPIO \
SAM_PINMUX(a, 1, gpio, gpio)
/* pa1a_eic_extint1 */
#define PA1A_EIC_EXTINT1 \
SAM_PINMUX(a, 1, a, periph)
/* pa1d_sercom1_pad1 */
#define PA1D_SERCOM1_PAD1 \
SAM_PINMUX(a, 1, d, periph)
/* pa1e_tc2_wo1 */
#define PA1E_TC2_WO1 \
SAM_PINMUX(a, 1, e, periph)
/* pa1h_ac_cmp3 */
#define PA1H_AC_CMP3 \
SAM_PINMUX(a, 1, h, periph)
/* pa2_gpio */
#define PA2_GPIO \
SAM_PINMUX(a, 2, gpio, gpio)
/* pa2a_eic_extint2 */
#define PA2A_EIC_EXTINT2 \
SAM_PINMUX(a, 2, a, periph)
/* pa2b_adc0_ain0 */
#define PA2B_ADC0_AIN0 \
SAM_PINMUX(a, 2, b, periph)
/* pa2b_ac_ain4 */
#define PA2B_AC_AIN4 \
SAM_PINMUX(a, 2, b, periph)
/* pa2b_ptc_y0 */
#define PA2B_PTC_Y0 \
SAM_PINMUX(a, 2, b, periph)
/* pa2b_dac_vout */
#define PA2B_DAC_VOUT \
SAM_PINMUX(a, 2, b, periph)
/* pa3_gpio */
#define PA3_GPIO \
SAM_PINMUX(a, 3, gpio, gpio)
/* pa3a_eic_extint3 */
#define PA3A_EIC_EXTINT3 \
SAM_PINMUX(a, 3, a, periph)
/* pa3b_anaref_vrefa */
#define PA3B_ANAREF_VREFA \
SAM_PINMUX(a, 3, b, periph)
/* pa3b_adc0_ain5 */
#define PA3B_ADC0_AIN5 \
SAM_PINMUX(a, 3, b, periph)
/* pa3b_ac_ain4 */
#define PA3B_AC_AIN4 \
SAM_PINMUX(a, 3, b, periph)
/* pa3b_ptc_y1 */
#define PA3B_PTC_Y1 \
SAM_PINMUX(a, 3, b, periph)
/* pa4_gpio */
#define PA4_GPIO \
SAM_PINMUX(a, 4, gpio, gpio)
/* pa4a_eic_extint4 */
#define PA4A_EIC_EXTINT4 \
SAM_PINMUX(a, 4, a, periph)
/* pa4b_anaref_vrefb */
#define PA4B_ANAREF_VREFB \
SAM_PINMUX(a, 4, b, periph)
/* pa4b_adc0_ain4 */
#define PA4B_ADC0_AIN4 \
SAM_PINMUX(a, 4, b, periph)
/* pa4b_ac_ain0 */
#define PA4B_AC_AIN0 \
SAM_PINMUX(a, 4, b, periph)
/* pa4b_ptc_y2 */
#define PA4B_PTC_Y2 \
SAM_PINMUX(a, 4, b, periph)
/* pa4d_sercom0_pad0 */
#define PA4D_SERCOM0_PAD0 \
SAM_PINMUX(a, 4, d, periph)
/* pa4e_tcc0_wo0 */
#define PA4E_TCC0_WO0 \
SAM_PINMUX(a, 4, e, periph)
/* pa5_gpio */
#define PA5_GPIO \
SAM_PINMUX(a, 5, gpio, gpio)
/* pa5a_eic_extint5 */
#define PA5A_EIC_EXTINT5 \
SAM_PINMUX(a, 5, a, periph)
/* pa5b_adc0_ain5 */
#define PA5B_ADC0_AIN5 \
SAM_PINMUX(a, 5, b, periph)
/* pa5b_ac_ain1 */
#define PA5B_AC_AIN1 \
SAM_PINMUX(a, 5, b, periph)
/* pa5b_ptc_y3 */
#define PA5B_PTC_Y3 \
SAM_PINMUX(a, 5, b, periph)
/* pa5d_sercom0_pad1 */
#define PA5D_SERCOM0_PAD1 \
SAM_PINMUX(a, 5, d, periph)
/* pa5e_tcc0_wo1 */
#define PA5E_TCC0_WO1 \
SAM_PINMUX(a, 5, e, periph)
/* pa6_gpio */
#define PA6_GPIO \
SAM_PINMUX(a, 6, gpio, gpio)
/* pa6a_eic_extint6 */
#define PA6A_EIC_EXTINT6 \
SAM_PINMUX(a, 6, a, periph)
/* pa6b_adc0_ain6 */
#define PA6B_ADC0_AIN6 \
SAM_PINMUX(a, 6, b, periph)
/* pa6b_ac_ain2 */
#define PA6B_AC_AIN2 \
SAM_PINMUX(a, 6, b, periph)
/* pa6b_ptc_y4 */
#define PA6B_PTC_Y4 \
SAM_PINMUX(a, 6, b, periph)
/* pa6b_sdadc0_ainn0 */
#define PA6B_SDADC0_AINN0 \
SAM_PINMUX(a, 6, b, periph)
/* pa6d_sercom0_pad2 */
#define PA6D_SERCOM0_PAD2 \
SAM_PINMUX(a, 6, d, periph)
/* pa6e_tcc1_wo0 */
#define PA6E_TCC1_WO0 \
SAM_PINMUX(a, 6, e, periph)
/* pa7_gpio */
#define PA7_GPIO \
SAM_PINMUX(a, 7, gpio, gpio)
/* pa7a_eic_extint7 */
#define PA7A_EIC_EXTINT7 \
SAM_PINMUX(a, 7, a, periph)
/* pa7b_adc0_ain7 */
#define PA7B_ADC0_AIN7 \
SAM_PINMUX(a, 7, b, periph)
/* pa7b_ac_ain3 */
#define PA7B_AC_AIN3 \
SAM_PINMUX(a, 7, b, periph)
/* pa7b_ptc_y5 */
#define PA7B_PTC_Y5 \
SAM_PINMUX(a, 7, b, periph)
/* pa7b_sdadc0_ainp0 */
#define PA7B_SDADC0_AINP0 \
SAM_PINMUX(a, 7, b, periph)
/* pa7d_sercom0_pad3 */
#define PA7D_SERCOM0_PAD3 \
SAM_PINMUX(a, 7, d, periph)
/* pa7e_tcc1_wo1 */
#define PA7E_TCC1_WO1 \
SAM_PINMUX(a, 7, e, periph)
/* pa8_gpio */
#define PA8_GPIO \
SAM_PINMUX(a, 8, gpio, gpio)
/* pa8a_eic_nmi */
#define PA8A_EIC_NMI \
SAM_PINMUX(a, 8, a, periph)
/* pa8b_adc0_ain8 */
#define PA8B_ADC0_AIN8 \
SAM_PINMUX(a, 8, b, periph)
/* pa8b_adc1_ain10 */
#define PA8B_ADC1_AIN10 \
SAM_PINMUX(a, 8, b, periph)
/* pa8b_ptc_xy16 */
#define PA8B_PTC_XY16 \
SAM_PINMUX(a, 8, b, periph)
/* pa8c_sercom0_pad0 */
#define PA8C_SERCOM0_PAD0 \
SAM_PINMUX(a, 8, c, periph)
/* pa8d_sercom2_pad0 */
#define PA8D_SERCOM2_PAD0 \
SAM_PINMUX(a, 8, d, periph)
/* pa8e_tcc0_wo0 */
#define PA8E_TCC0_WO0 \
SAM_PINMUX(a, 8, e, periph)
/* pa8f_tcc1_wo2 */
#define PA8F_TCC1_WO2 \
SAM_PINMUX(a, 8, f, periph)
/* pa9_gpio */
#define PA9_GPIO \
SAM_PINMUX(a, 9, gpio, gpio)
/* pa9a_eic_extint9 */
#define PA9A_EIC_EXTINT9 \
SAM_PINMUX(a, 9, a, periph)
/* pa9b_adc0_ain9 */
#define PA9B_ADC0_AIN9 \
SAM_PINMUX(a, 9, b, periph)
/* pa9b_adc1_ain11 */
#define PA9B_ADC1_AIN11 \
SAM_PINMUX(a, 9, b, periph)
/* pa9b_ptc_x1 */
#define PA9B_PTC_X1 \
SAM_PINMUX(a, 9, b, periph)
/* pa9c_sercom0_pad1 */
#define PA9C_SERCOM0_PAD1 \
SAM_PINMUX(a, 9, c, periph)
/* pa9d_sercom2_pad1 */
#define PA9D_SERCOM2_PAD1 \
SAM_PINMUX(a, 9, d, periph)
/* pa9e_tcc0_wo1 */
#define PA9E_TCC0_WO1 \
SAM_PINMUX(a, 9, e, periph)
/* pa9f_tcc1_wo3 */
#define PA9F_TCC1_WO3 \
SAM_PINMUX(a, 9, f, periph)
/* pa10_gpio */
#define PA10_GPIO \
SAM_PINMUX(a, 10, gpio, gpio)
/* pa10a_eic_extint10 */
#define PA10A_EIC_EXTINT10 \
SAM_PINMUX(a, 10, a, periph)
/* pa10b_adc0_ain10 */
#define PA10B_ADC0_AIN10 \
SAM_PINMUX(a, 10, b, periph)
/* pa10b_ptc_x2 */
#define PA10B_PTC_X2 \
SAM_PINMUX(a, 10, b, periph)
/* pa10c_sercom0_pad2 */
#define PA10C_SERCOM0_PAD2 \
SAM_PINMUX(a, 10, c, periph)
/* pa10d_sercom2_pad2 */
#define PA10D_SERCOM2_PAD2 \
SAM_PINMUX(a, 10, d, periph)
/* pa10e_tcc1_wo0 */
#define PA10E_TCC1_WO0 \
SAM_PINMUX(a, 10, e, periph)
/* pa10f_tcc0_wo2 */
#define PA10F_TCC0_WO2 \
SAM_PINMUX(a, 10, f, periph)
/* pa10h_gclk_io4 */
#define PA10H_GCLK_IO4 \
SAM_PINMUX(a, 10, h, periph)
/* pa11_gpio */
#define PA11_GPIO \
SAM_PINMUX(a, 11, gpio, gpio)
/* pa11a_eic_extint11 */
#define PA11A_EIC_EXTINT11 \
SAM_PINMUX(a, 11, a, periph)
/* pa11b_adc0_ain11 */
#define PA11B_ADC0_AIN11 \
SAM_PINMUX(a, 11, b, periph)
/* pa11b_ptc_x3 */
#define PA11B_PTC_X3 \
SAM_PINMUX(a, 11, b, periph)
/* pa11c_sercom0_pad3 */
#define PA11C_SERCOM0_PAD3 \
SAM_PINMUX(a, 11, c, periph)
/* pa11d_sercom2_pad3 */
#define PA11D_SERCOM2_PAD3 \
SAM_PINMUX(a, 11, d, periph)
/* pa11e_tcc1_wo1 */
#define PA11E_TCC1_WO1 \
SAM_PINMUX(a, 11, e, periph)
/* pa11f_tcc0_wo3 */
#define PA11F_TCC0_WO3 \
SAM_PINMUX(a, 11, f, periph)
/* pa11h_gclk_io5 */
#define PA11H_GCLK_IO5 \
SAM_PINMUX(a, 11, h, periph)
/* pa14_gpio */
#define PA14_GPIO \
SAM_PINMUX(a, 14, gpio, gpio)
/* pa14a_eic_extint14 */
#define PA14A_EIC_EXTINT14 \
SAM_PINMUX(a, 14, a, periph)
/* pa14c_sercom2_pad2 */
#define PA14C_SERCOM2_PAD2 \
SAM_PINMUX(a, 14, c, periph)
/* pa14d_sercom4_pad2 */
#define PA14D_SERCOM4_PAD2 \
SAM_PINMUX(a, 14, d, periph)
/* pa14e_tc4_wo0 */
#define PA14E_TC4_WO0 \
SAM_PINMUX(a, 14, e, periph)
/* pa14f_tcc0_wo4 */
#define PA14F_TCC0_WO4 \
SAM_PINMUX(a, 14, f, periph)
/* pa14h_gclk_io0 */
#define PA14H_GCLK_IO0 \
SAM_PINMUX(a, 14, h, periph)
/* pa15_gpio */
#define PA15_GPIO \
SAM_PINMUX(a, 15, gpio, gpio)
/* pa15a_eic_extint15 */
#define PA15A_EIC_EXTINT15 \
SAM_PINMUX(a, 15, a, periph)
/* pa15c_sercom2_pad3 */
#define PA15C_SERCOM2_PAD3 \
SAM_PINMUX(a, 15, c, periph)
/* pa15d_sercom4_pad3 */
#define PA15D_SERCOM4_PAD3 \
SAM_PINMUX(a, 15, d, periph)
/* pa15e_tc4_wo1 */
#define PA15E_TC4_WO1 \
SAM_PINMUX(a, 15, e, periph)
/* pa15f_tcc0_wo5 */
#define PA15F_TCC0_WO5 \
SAM_PINMUX(a, 15, f, periph)
/* pa15h_gclk_io1 */
#define PA15H_GCLK_IO1 \
SAM_PINMUX(a, 15, h, periph)
/* pa16_gpio */
#define PA16_GPIO \
SAM_PINMUX(a, 16, gpio, gpio)
/* pa16a_eic_extint0 */
#define PA16A_EIC_EXTINT0 \
SAM_PINMUX(a, 16, a, periph)
/* pa16b_ptc_x4 */
#define PA16B_PTC_X4 \
SAM_PINMUX(a, 16, b, periph)
/* pa16c_sercom1_pad0 */
#define PA16C_SERCOM1_PAD0 \
SAM_PINMUX(a, 16, c, periph)
/* pa16d_sercom3_pad0 */
#define PA16D_SERCOM3_PAD0 \
SAM_PINMUX(a, 16, d, periph)
/* pa16e_tcc2_wo0 */
#define PA16E_TCC2_WO0 \
SAM_PINMUX(a, 16, e, periph)
/* pa16f_tcc0_wo6 */
#define PA16F_TCC0_WO6 \
SAM_PINMUX(a, 16, f, periph)
/* pa16h_gclk_io2 */
#define PA16H_GCLK_IO2 \
SAM_PINMUX(a, 16, h, periph)
/* pa17_gpio */
#define PA17_GPIO \
SAM_PINMUX(a, 17, gpio, gpio)
/* pa17a_eic_extint1 */
#define PA17A_EIC_EXTINT1 \
SAM_PINMUX(a, 17, a, periph)
/* pa17b_ptc_x5 */
#define PA17B_PTC_X5 \
SAM_PINMUX(a, 17, b, periph)
/* pa17c_sercom1_pad1 */
#define PA17C_SERCOM1_PAD1 \
SAM_PINMUX(a, 17, c, periph)
/* pa17d_sercom3_pad1 */
#define PA17D_SERCOM3_PAD1 \
SAM_PINMUX(a, 17, d, periph)
/* pa17e_tcc2_wo1 */
#define PA17E_TCC2_WO1 \
SAM_PINMUX(a, 17, e, periph)
/* pa17f_tcc0_wo7 */
#define PA17F_TCC0_WO7 \
SAM_PINMUX(a, 17, f, periph)
/* pa17h_gclk_io3 */
#define PA17H_GCLK_IO3 \
SAM_PINMUX(a, 17, h, periph)
/* pa18_gpio */
#define PA18_GPIO \
SAM_PINMUX(a, 18, gpio, gpio)
/* pa18a_eic_extint2 */
#define PA18A_EIC_EXTINT2 \
SAM_PINMUX(a, 18, a, periph)
/* pa18b_ptc_x6 */
#define PA18B_PTC_X6 \
SAM_PINMUX(a, 18, b, periph)
/* pa18c_sercom1_pad2 */
#define PA18C_SERCOM1_PAD2 \
SAM_PINMUX(a, 18, c, periph)
/* pa18d_sercom3_pad2 */
#define PA18D_SERCOM3_PAD2 \
SAM_PINMUX(a, 18, d, periph)
/* pa18e_tc4_wo0 */
#define PA18E_TC4_WO0 \
SAM_PINMUX(a, 18, e, periph)
/* pa18f_tcc0_wo2 */
#define PA18F_TCC0_WO2 \
SAM_PINMUX(a, 18, f, periph)
/* pa18h_ac_cmp0 */
#define PA18H_AC_CMP0 \
SAM_PINMUX(a, 18, h, periph)
/* pa19_gpio */
#define PA19_GPIO \
SAM_PINMUX(a, 19, gpio, gpio)
/* pa19a_eic_extint3 */
#define PA19A_EIC_EXTINT3 \
SAM_PINMUX(a, 19, a, periph)
/* pa19b_ptc_x7 */
#define PA19B_PTC_X7 \
SAM_PINMUX(a, 19, b, periph)
/* pa19c_sercom1_pad3 */
#define PA19C_SERCOM1_PAD3 \
SAM_PINMUX(a, 19, c, periph)
/* pa19d_sercom3_pad3 */
#define PA19D_SERCOM3_PAD3 \
SAM_PINMUX(a, 19, d, periph)
/* pa19e_tc4_wo1 */
#define PA19E_TC4_WO1 \
SAM_PINMUX(a, 19, e, periph)
/* pa19f_tcc0_wo3 */
#define PA19F_TCC0_WO3 \
SAM_PINMUX(a, 19, f, periph)
/* pa19h_ac_cmp1 */
#define PA19H_AC_CMP1 \
SAM_PINMUX(a, 19, h, periph)
/* pa22_gpio */
#define PA22_GPIO \
SAM_PINMUX(a, 22, gpio, gpio)
/* pa22a_eic_extint6 */
#define PA22A_EIC_EXTINT6 \
SAM_PINMUX(a, 22, a, periph)
/* pa22b_ptc_x10 */
#define PA22B_PTC_X10 \
SAM_PINMUX(a, 22, b, periph)
/* pa22c_sercom3_pad0 */
#define PA22C_SERCOM3_PAD0 \
SAM_PINMUX(a, 22, c, periph)
/* pa22d_sercom5_pad0 */
#define PA22D_SERCOM5_PAD0 \
SAM_PINMUX(a, 22, d, periph)
/* pa22e_tc0_wo0 */
#define PA22E_TC0_WO0 \
SAM_PINMUX(a, 22, e, periph)
/* pa22f_tcc0_wo4 */
#define PA22F_TCC0_WO4 \
SAM_PINMUX(a, 22, f, periph)
/* pa22h_gclk_io6 */
#define PA22H_GCLK_IO6 \
SAM_PINMUX(a, 22, h, periph)
/* pa23_gpio */
#define PA23_GPIO \
SAM_PINMUX(a, 23, gpio, gpio)
/* pa23a_eic_extint7 */
#define PA23A_EIC_EXTINT7 \
SAM_PINMUX(a, 23, a, periph)
/* pa23b_ptc_x11 */
#define PA23B_PTC_X11 \
SAM_PINMUX(a, 23, b, periph)
/* pa23c_sercom3_pad1 */
#define PA23C_SERCOM3_PAD1 \
SAM_PINMUX(a, 23, c, periph)
/* pa23d_sercom5_pad1 */
#define PA23D_SERCOM5_PAD1 \
SAM_PINMUX(a, 23, d, periph)
/* pa23e_tc0_wo1 */
#define PA23E_TC0_WO1 \
SAM_PINMUX(a, 23, e, periph)
/* pa23f_tcc0_wo5 */
#define PA23F_TCC0_WO5 \
SAM_PINMUX(a, 23, f, periph)
/* pa23h_gclk_io7 */
#define PA23H_GCLK_IO7 \
SAM_PINMUX(a, 23, h, periph)
/* pa24_gpio */
#define PA24_GPIO \
SAM_PINMUX(a, 24, gpio, gpio)
/* pa24a_eic_extint12 */
#define PA24A_EIC_EXTINT12 \
SAM_PINMUX(a, 24, a, periph)
/* pa24c_sercom3_pad2 */
#define PA24C_SERCOM3_PAD2 \
SAM_PINMUX(a, 24, c, periph)
/* pa24d_sercom5_pad2 */
#define PA24D_SERCOM5_PAD2 \
SAM_PINMUX(a, 24, d, periph)
/* pa24e_tc1_wo0 */
#define PA24E_TC1_WO0 \
SAM_PINMUX(a, 24, e, periph)
/* pa24f_tcc1_wo2 */
#define PA24F_TCC1_WO2 \
SAM_PINMUX(a, 24, f, periph)
/* pa24g_can0_tx */
#define PA24G_CAN0_TX \
SAM_PINMUX(a, 24, g, periph)
/* pa24h_ac_cmp2 */
#define PA24H_AC_CMP2 \
SAM_PINMUX(a, 24, h, periph)
/* pa25_gpio */
#define PA25_GPIO \
SAM_PINMUX(a, 25, gpio, gpio)
/* pa25a_eic_extint13 */
#define PA25A_EIC_EXTINT13 \
SAM_PINMUX(a, 25, a, periph)
/* pa25c_sercom3_pad3 */
#define PA25C_SERCOM3_PAD3 \
SAM_PINMUX(a, 25, c, periph)
/* pa25d_sercom5_pad3 */
#define PA25D_SERCOM5_PAD3 \
SAM_PINMUX(a, 25, d, periph)
/* pa25e_tc1_wo1 */
#define PA25E_TC1_WO1 \
SAM_PINMUX(a, 25, e, periph)
/* pa25f_tcc1_wo3 */
#define PA25F_TCC1_WO3 \
SAM_PINMUX(a, 25, f, periph)
/* pa25g_can0_rx */
#define PA25G_CAN0_RX \
SAM_PINMUX(a, 25, g, periph)
/* pa25h_ac_cmp3 */
#define PA25H_AC_CMP3 \
SAM_PINMUX(a, 25, h, periph)
/* pa27_gpio */
#define PA27_GPIO \
SAM_PINMUX(a, 27, gpio, gpio)
/* pa27a_eic_extint15 */
#define PA27A_EIC_EXTINT15 \
SAM_PINMUX(a, 27, a, periph)
/* pa27h_gclk_io0 */
#define PA27H_GCLK_IO0 \
SAM_PINMUX(a, 27, h, periph)
/* pa28_gpio */
#define PA28_GPIO \
SAM_PINMUX(a, 28, gpio, gpio)
/* pa28a_eic_extint8 */
#define PA28A_EIC_EXTINT8 \
SAM_PINMUX(a, 28, a, periph)
/* pa28h_gclk_io0 */
#define PA28H_GCLK_IO0 \
SAM_PINMUX(a, 28, h, periph)
/* pa30_gpio */
#define PA30_GPIO \
SAM_PINMUX(a, 30, gpio, gpio)
/* pa30a_eic_extint10 */
#define PA30A_EIC_EXTINT10 \
SAM_PINMUX(a, 30, a, periph)
/* pa30d_sercom1_pad2 */
#define PA30D_SERCOM1_PAD2 \
SAM_PINMUX(a, 30, d, periph)
/* pa30e_tcc1_wo0 */
#define PA30E_TCC1_WO0 \
SAM_PINMUX(a, 30, e, periph)
/* pa30g_swd_clk */
#define PA30G_SWD_CLK \
SAM_PINMUX(a, 30, g, periph)
/* pa30h_gclk_io0 */
#define PA30H_GCLK_IO0 \
SAM_PINMUX(a, 30, h, periph)
/* pa31_gpio */
#define PA31_GPIO \
SAM_PINMUX(a, 31, gpio, gpio)
/* pa31a_eic_extint11 */
#define PA31A_EIC_EXTINT11 \
SAM_PINMUX(a, 31, a, periph)
/* pa31d_sercom1_pad3 */
#define PA31D_SERCOM1_PAD3 \
SAM_PINMUX(a, 31, d, periph)
/* pa31e_tcc1_wo1 */
#define PA31E_TCC1_WO1 \
SAM_PINMUX(a, 31, e, periph)
/* pa31g_swd_io */
#define PA31G_SWD_IO \
SAM_PINMUX(a, 31, g, periph)

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@ -0,0 +1,735 @@
# Copyright (c) 2022 Kamil Serwus
# SPDX-License-Identifier: Apache-2.0
#
# Sources:
# - SAM_C20_C21_Family_Data_Sheet_DS60001479D (Revision D - 01/2020)
#
# Pin codes:
#
# - 32 pins: e
# - 48 pins: g
# - 64 pins: j
# - 100 pins: n
#
# SoC Revision (variant) supported:
#
# - SAMC20
# - A = Default Variant
#
# - SAMC21
# - A = Default Variant
model: atmel,sam
family: c2x
map: SAM_PINMUX
series: [c20, c21]
variants:
- pincode: e
series: [c20, c21]
- pincode: g
series: [c20, c21]
- pincode: j
series: [c20, c21]
- pincode: n
series: [c20, c21]
pins:
pa00:
pincodes: [e, g, j, n]
periph:
- [a, eic, extint0]
- [d, sercom1, pad0]
- [e, tc2, wo0]
- [h, ac, cmp2]
pa01:
pincodes: [e, g, j, n]
periph:
- [a, eic, extint1]
- [d, sercom1, pad1]
- [e, tc2, wo1]
- [h, ac, cmp3]
pc00:
pincodes: [n]
periph:
- [a, eic, extint8]
- [b, adc0, ain8]
pc01:
pincodes: [n]
periph:
- [a, eic, extint9]
- [b, adc0, ain9]
pc02:
pincodes: [n]
periph:
- [a, eic, extint10]
- [b, adc0, ain10]
pc03:
pincodes: [n]
periph:
- [a, eic, extint11]
- [b, adc0, ain11]
- [c, sercom7, pad0]
- [f, tcc2, wo0]
pa02:
pincodes: [e, g, j, n]
periph:
- [a, eic, extint2]
- [b, adc0, ain0]
- [b, ac, ain4]
- [b, ptc, y0]
- [b, dac, vout, [c20]]
pa03:
pincodes: [e, g, j, n]
periph:
- [a, eic, extint3]
- [b, anaref, vrefa]
- [b, adc0, ain5]
- [b, ac, ain4]
- [b, ptc, y1]
pb04:
pincodes: [j, n]
periph:
- [a, eic, extint4]
- [b, adc0, ain6]
- [b, ptc, y10]
pb05:
pincodes: [j, n]
periph:
- [a, eic, extint5]
- [b, adc0, ain7]
- [b, ac, ain6]
- [b, ptc, y11]
pb06:
pincodes: [j, n]
periph:
- [a, eic, extint6]
- [b, adc0, ain8]
- [b, ac, ain7]
- [b, ptc, y12]
- [b, sdadc0, ainn2, [c20]]
- [c, sercom7, pad1, [j]]
pb07:
pincodes: [j, n]
periph:
- [a, eic, extint7]
- [b, adc0, ain9]
- [b, ptc, y13]
- [b, sdadc0, ainp2, [c20]]
- [c, sercom7, pad3, [j]]
- [d, sercom7, pad2, [j]]
pb08:
pincodes: [g, j, n]
periph:
- [a, eic, extint8]
- [b, adc0, ain2]
- [b, adc1, ain4, [c20]]
- [b, ptc, y14]
- [b, sdadc0, ainn1, [c20]]
- [c, sercom7, pad2, [g, j]]
- [d, sercom4, pad0, [n]]
- [d, sercom7, pad3, [g, j]]
- [e, tc0, wo0, [n]]
- [e, tc4, wo0, [g, j]]
pb09:
pincodes: [g, j, n]
periph:
- [a, eic, extint9]
- [b, adc0, ain3]
- [b, adc1, ain5, [c20]]
- [b, ptc, y15]
- [b, sdadc0, ainp1, [c20]]
- [d, sercom4, pad1]
- [e, tc0, wo1, [n]]
- [e, tc4, wo1, [g, j]]
pa04:
pincodes: [e, g, j, n]
periph:
- [a, eic, extint4]
- [b, anaref, vrefb]
- [b, adc0, ain4]
- [b, ac, ain0]
- [b, ptc, y2]
- [d, sercom0, pad0]
- [e, tcc0, wo0, [n]]
- [e, tc0, wo0, [e, g, j]]
pa05:
pincodes: [e, g, j, n]
periph:
- [a, eic, extint5]
- [b, adc0, ain5]
- [b, ac, ain1]
- [b, ptc, y3]
- [d, sercom0, pad1]
- [e, tcc0, wo1, [n]]
- [e, tc0, wo1, [e, g, j]]
pa06:
pincodes: [e, g, j, n]
periph:
- [a, eic, extint6]
- [b, adc0, ain6]
- [b, ac, ain2]
- [b, ptc, y4]
- [b, sdadc0, ainn0, [c20]]