feat(sdio_slave): add headers for sdio slave components: slc, host, hinf
This commit is contained in:
Michael (XIAO Xufeng)
parent
92c469b599
commit
c73575de4f
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@ -6,14 +6,17 @@ PROVIDE ( SIGMADELTA = 0x3ff44f00 );
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PROVIDE ( RTCCNTL = 0x3ff48000 );
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PROVIDE ( RTCIO = 0x3ff48400 );
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PROVIDE ( SENS = 0x3ff48800 );
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PROVIDE ( HINF = 0x3ff4B000 );
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PROVIDE ( UHCI1 = 0x3ff4C000 );
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PROVIDE ( I2S0 = 0x3ff4F000 );
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PROVIDE ( UART1 = 0x3ff50000 );
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PROVIDE ( I2C0 = 0x3ff53000 );
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PROVIDE ( UHCI0 = 0x3ff54000 );
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PROVIDE ( HOST = 0x3ff55000 );
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PROVIDE ( RMT = 0x3ff56000 );
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PROVIDE ( RMTMEM = 0x3ff56800 );
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PROVIDE ( PCNT = 0x3ff57000 );
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PROVIDE ( SLC = 0x3ff58000 );
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PROVIDE ( LEDC = 0x3ff59000 );
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PROVIDE ( MCPWM0 = 0x3ff5E000 );
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PROVIDE ( TIMERG0 = 0x3ff5F000 );
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@ -0,0 +1,248 @@
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// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_HINF_REG_H_
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#define _SOC_HINF_REG_H_
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#include "soc.h"
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#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
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/* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */
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/*description: */
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#define HINF_DEVICE_ID_FN1 0x0000FFFF
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#define HINF_DEVICE_ID_FN1_M ((HINF_DEVICE_ID_FN1_V)<<(HINF_DEVICE_ID_FN1_S))
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#define HINF_DEVICE_ID_FN1_V 0xFFFF
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#define HINF_DEVICE_ID_FN1_S 16
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/* HINF_USER_ID_FN1 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
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/*description: */
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#define HINF_USER_ID_FN1 0x0000FFFF
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#define HINF_USER_ID_FN1_M ((HINF_USER_ID_FN1_V)<<(HINF_USER_ID_FN1_S))
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#define HINF_USER_ID_FN1_V 0xFFFF
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#define HINF_USER_ID_FN1_S 0
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#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
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/* HINF_SDIO20_CONF1 : R/W ;bitpos:[31:29] ;default: 3'h0 ; */
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/*description: */
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#define HINF_SDIO20_CONF1 0x00000007
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#define HINF_SDIO20_CONF1_M ((HINF_SDIO20_CONF1_V)<<(HINF_SDIO20_CONF1_S))
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#define HINF_SDIO20_CONF1_V 0x7
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#define HINF_SDIO20_CONF1_S 29
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/* HINF_FUNC2_EPS : RO ;bitpos:[28] ;default: 1'b0 ; */
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/*description: */
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#define HINF_FUNC2_EPS (BIT(28))
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#define HINF_FUNC2_EPS_M (BIT(28))
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#define HINF_FUNC2_EPS_V 0x1
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#define HINF_FUNC2_EPS_S 28
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/* HINF_SDIO_VER : R/W ;bitpos:[27:16] ;default: 12'h111 ; */
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/*description: */
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#define HINF_SDIO_VER 0x00000FFF
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#define HINF_SDIO_VER_M ((HINF_SDIO_VER_V)<<(HINF_SDIO_VER_S))
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#define HINF_SDIO_VER_V 0xFFF
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#define HINF_SDIO_VER_S 16
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/* HINF_SDIO20_CONF0 : R/W ;bitpos:[15:12] ;default: 4'b0 ; */
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/*description: */
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#define HINF_SDIO20_CONF0 0x0000000F
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#define HINF_SDIO20_CONF0_M ((HINF_SDIO20_CONF0_V)<<(HINF_SDIO20_CONF0_S))
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#define HINF_SDIO20_CONF0_V 0xF
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#define HINF_SDIO20_CONF0_S 12
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/* HINF_IOENABLE1 : RO ;bitpos:[11] ;default: 1'b0 ; */
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/*description: */
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#define HINF_IOENABLE1 (BIT(11))
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#define HINF_IOENABLE1_M (BIT(11))
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#define HINF_IOENABLE1_V 0x1
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#define HINF_IOENABLE1_S 11
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/* HINF_EMP : RO ;bitpos:[10] ;default: 1'b0 ; */
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/*description: */
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#define HINF_EMP (BIT(10))
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#define HINF_EMP_M (BIT(10))
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#define HINF_EMP_V 0x1
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#define HINF_EMP_S 10
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/* HINF_FUNC1_EPS : RO ;bitpos:[9] ;default: 1'b0 ; */
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/*description: */
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#define HINF_FUNC1_EPS (BIT(9))
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#define HINF_FUNC1_EPS_M (BIT(9))
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#define HINF_FUNC1_EPS_V 0x1
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#define HINF_FUNC1_EPS_S 9
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/* HINF_CD_DISABLE : RO ;bitpos:[8] ;default: 1'b0 ; */
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/*description: */
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#define HINF_CD_DISABLE (BIT(8))
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#define HINF_CD_DISABLE_M (BIT(8))
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#define HINF_CD_DISABLE_V 0x1
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#define HINF_CD_DISABLE_S 8
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/* HINF_IOENABLE2 : RO ;bitpos:[7] ;default: 1'b0 ; */
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/*description: */
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#define HINF_IOENABLE2 (BIT(7))
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#define HINF_IOENABLE2_M (BIT(7))
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#define HINF_IOENABLE2_V 0x1
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#define HINF_IOENABLE2_S 7
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/* HINF_SDIO_INT_MASK : R/W ;bitpos:[6] ;default: 1'b0 ; */
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/*description: */
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#define HINF_SDIO_INT_MASK (BIT(6))
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#define HINF_SDIO_INT_MASK_M (BIT(6))
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#define HINF_SDIO_INT_MASK_V 0x1
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#define HINF_SDIO_INT_MASK_S 6
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/* HINF_SDIO_IOREADY2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
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/*description: */
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#define HINF_SDIO_IOREADY2 (BIT(5))
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#define HINF_SDIO_IOREADY2_M (BIT(5))
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#define HINF_SDIO_IOREADY2_V 0x1
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#define HINF_SDIO_IOREADY2_S 5
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/* HINF_SDIO_CD_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */
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/*description: */
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#define HINF_SDIO_CD_ENABLE (BIT(4))
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#define HINF_SDIO_CD_ENABLE_M (BIT(4))
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#define HINF_SDIO_CD_ENABLE_V 0x1
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#define HINF_SDIO_CD_ENABLE_S 4
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/* HINF_HIGHSPEED_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */
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/*description: */
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#define HINF_HIGHSPEED_MODE (BIT(3))
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#define HINF_HIGHSPEED_MODE_M (BIT(3))
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#define HINF_HIGHSPEED_MODE_V 0x1
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#define HINF_HIGHSPEED_MODE_S 3
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/* HINF_HIGHSPEED_ENABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
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/*description: */
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#define HINF_HIGHSPEED_ENABLE (BIT(2))
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#define HINF_HIGHSPEED_ENABLE_M (BIT(2))
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#define HINF_HIGHSPEED_ENABLE_V 0x1
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#define HINF_HIGHSPEED_ENABLE_S 2
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/* HINF_SDIO_IOREADY1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: */
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#define HINF_SDIO_IOREADY1 (BIT(1))
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#define HINF_SDIO_IOREADY1_M (BIT(1))
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#define HINF_SDIO_IOREADY1_V 0x1
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#define HINF_SDIO_IOREADY1_S 1
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/* HINF_SDIO_ENABLE : R/W ;bitpos:[0] ;default: 1'b1 ; */
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/*description: */
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#define HINF_SDIO_ENABLE (BIT(0))
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#define HINF_SDIO_ENABLE_M (BIT(0))
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#define HINF_SDIO_ENABLE_V 0x1
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#define HINF_SDIO_ENABLE_S 0
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#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1C)
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/* HINF_SDIO_IOREADY0 : R/W ;bitpos:[17] ;default: 1'b1 ; */
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/*description: */
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#define HINF_SDIO_IOREADY0 (BIT(17))
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#define HINF_SDIO_IOREADY0_M (BIT(17))
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#define HINF_SDIO_IOREADY0_V 0x1
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#define HINF_SDIO_IOREADY0_S 17
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/* HINF_SDIO_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
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/*description: */
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#define HINF_SDIO_RST (BIT(16))
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#define HINF_SDIO_RST_M (BIT(16))
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#define HINF_SDIO_RST_V 0x1
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#define HINF_SDIO_RST_S 16
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/* HINF_CHIP_STATE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
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/*description: */
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#define HINF_CHIP_STATE 0x000000FF
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#define HINF_CHIP_STATE_M ((HINF_CHIP_STATE_V)<<(HINF_CHIP_STATE_S))
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#define HINF_CHIP_STATE_V 0xFF
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#define HINF_CHIP_STATE_S 8
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/* HINF_PIN_STATE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
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/*description: */
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#define HINF_PIN_STATE 0x000000FF
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#define HINF_PIN_STATE_M ((HINF_PIN_STATE_V)<<(HINF_PIN_STATE_S))
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#define HINF_PIN_STATE_V 0xFF
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#define HINF_PIN_STATE_S 0
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#define HINF_CIS_CONF0_REG (DR_REG_HINF_BASE + 0x20)
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/* HINF_CIS_CONF_W0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W0 0xFFFFFFFF
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#define HINF_CIS_CONF_W0_M ((HINF_CIS_CONF_W0_V)<<(HINF_CIS_CONF_W0_S))
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#define HINF_CIS_CONF_W0_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W0_S 0
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#define HINF_CIS_CONF1_REG (DR_REG_HINF_BASE + 0x24)
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/* HINF_CIS_CONF_W1 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W1 0xFFFFFFFF
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#define HINF_CIS_CONF_W1_M ((HINF_CIS_CONF_W1_V)<<(HINF_CIS_CONF_W1_S))
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#define HINF_CIS_CONF_W1_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W1_S 0
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#define HINF_CIS_CONF2_REG (DR_REG_HINF_BASE + 0x28)
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/* HINF_CIS_CONF_W2 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W2 0xFFFFFFFF
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#define HINF_CIS_CONF_W2_M ((HINF_CIS_CONF_W2_V)<<(HINF_CIS_CONF_W2_S))
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#define HINF_CIS_CONF_W2_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W2_S 0
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#define HINF_CIS_CONF3_REG (DR_REG_HINF_BASE + 0x2C)
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/* HINF_CIS_CONF_W3 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W3 0xFFFFFFFF
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#define HINF_CIS_CONF_W3_M ((HINF_CIS_CONF_W3_V)<<(HINF_CIS_CONF_W3_S))
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#define HINF_CIS_CONF_W3_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W3_S 0
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#define HINF_CIS_CONF4_REG (DR_REG_HINF_BASE + 0x30)
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/* HINF_CIS_CONF_W4 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W4 0xFFFFFFFF
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#define HINF_CIS_CONF_W4_M ((HINF_CIS_CONF_W4_V)<<(HINF_CIS_CONF_W4_S))
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#define HINF_CIS_CONF_W4_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W4_S 0
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#define HINF_CIS_CONF5_REG (DR_REG_HINF_BASE + 0x34)
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/* HINF_CIS_CONF_W5 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W5 0xFFFFFFFF
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#define HINF_CIS_CONF_W5_M ((HINF_CIS_CONF_W5_V)<<(HINF_CIS_CONF_W5_S))
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#define HINF_CIS_CONF_W5_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W5_S 0
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#define HINF_CIS_CONF6_REG (DR_REG_HINF_BASE + 0x38)
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/* HINF_CIS_CONF_W6 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W6 0xFFFFFFFF
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#define HINF_CIS_CONF_W6_M ((HINF_CIS_CONF_W6_V)<<(HINF_CIS_CONF_W6_S))
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#define HINF_CIS_CONF_W6_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W6_S 0
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#define HINF_CIS_CONF7_REG (DR_REG_HINF_BASE + 0x3C)
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/* HINF_CIS_CONF_W7 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W7 0xFFFFFFFF
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#define HINF_CIS_CONF_W7_M ((HINF_CIS_CONF_W7_V)<<(HINF_CIS_CONF_W7_S))
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#define HINF_CIS_CONF_W7_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W7_S 0
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#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
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/* HINF_DEVICE_ID_FN2 : R/W ;bitpos:[31:16] ;default: 16'h3333 ; */
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/*description: */
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#define HINF_DEVICE_ID_FN2 0x0000FFFF
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#define HINF_DEVICE_ID_FN2_M ((HINF_DEVICE_ID_FN2_V)<<(HINF_DEVICE_ID_FN2_S))
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#define HINF_DEVICE_ID_FN2_V 0xFFFF
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#define HINF_DEVICE_ID_FN2_S 16
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/* HINF_USER_ID_FN2 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
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/*description: */
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#define HINF_USER_ID_FN2 0x0000FFFF
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#define HINF_USER_ID_FN2_M ((HINF_USER_ID_FN2_V)<<(HINF_USER_ID_FN2_S))
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#define HINF_USER_ID_FN2_V 0xFFFF
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#define HINF_USER_ID_FN2_S 0
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#define HINF_DATE_REG (DR_REG_HINF_BASE + 0xFC)
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/* HINF_SDIO_DATE : R/W ;bitpos:[31:0] ;default: 32'h15030200 ; */
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/*description: */
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#define HINF_SDIO_DATE 0xFFFFFFFF
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#define HINF_SDIO_DATE_M ((HINF_SDIO_DATE_V)<<(HINF_SDIO_DATE_S))
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#define HINF_SDIO_DATE_V 0xFFFFFFFF
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#define HINF_SDIO_DATE_S 0
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#endif /*_SOC_HINF_REG_H_ */
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@ -0,0 +1,134 @@
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// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_HINF_STRUCT_H_
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#define _SOC_HINF_STRUCT_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct {
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union {
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struct {
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uint32_t user_id_fn1: 16;
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uint32_t device_id_fn1:16;
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};
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uint32_t val;
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} cfg_data0;
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union {
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struct {
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uint32_t sdio_enable: 1;
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uint32_t sdio_ioready1: 1;
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uint32_t highspeed_enable: 1;
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uint32_t highspeed_mode: 1;
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uint32_t sdio_cd_enable: 1;
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uint32_t sdio_ioready2: 1;
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uint32_t sdio_int_mask: 1;
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uint32_t ioenable2: 1;
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uint32_t cd_disable: 1;
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uint32_t func1_eps: 1;
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uint32_t emp: 1;
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uint32_t ioenable1: 1;
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uint32_t sdio20_conf0: 4;
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uint32_t sdio_ver: 12;
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uint32_t func2_eps: 1;
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uint32_t sdio20_conf1: 3;
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};
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uint32_t val;
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} cfg_data1;
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uint32_t reserved_8;
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uint32_t reserved_c;
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uint32_t reserved_10;
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uint32_t reserved_14;
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uint32_t reserved_18;
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union {
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struct {
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uint32_t pin_state: 8;
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uint32_t chip_state: 8;
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uint32_t sdio_rst: 1;
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uint32_t sdio_ioready0: 1;
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uint32_t reserved18: 14;
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};
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uint32_t val;
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} cfg_data7;
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uint32_t cis_conf0; /**/
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uint32_t cis_conf1; /**/
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uint32_t cis_conf2; /**/
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uint32_t cis_conf3; /**/
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uint32_t cis_conf4; /**/
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uint32_t cis_conf5; /**/
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uint32_t cis_conf6; /**/
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uint32_t cis_conf7; /**/
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union {
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struct {
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uint32_t user_id_fn2: 16;
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uint32_t device_id_fn2:16;
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};
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uint32_t val;
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} cfg_data16;
|
||||
uint32_t reserved_44;
|
||||
uint32_t reserved_48;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t date; /**/
|
||||
} hinf_dev_t;
|
||||
extern hinf_dev_t HINF;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_HINF_STRUCT_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,891 @@
|
|||
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_HOST_STRUCT_H_
|
||||
#define _SOC_HOST_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
uint32_t reserved_0;
|
||||
uint32_t reserved_4;
|
||||
uint32_t reserved_8;
|
||||
uint32_t reserved_c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 24;
|
||||
uint32_t func2_int: 1;
|
||||
uint32_t reserved25: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} func2_0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t func2_int_en: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} func2_1;
|
||||
uint32_t reserved_18;
|
||||
uint32_t reserved_1c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t func1_mdstat: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} func2_2;
|
||||
uint32_t reserved_24;
|
||||
uint32_t reserved_28;
|
||||
uint32_t reserved_2c;
|
||||
uint32_t reserved_30;
|
||||
uint32_t gpio_status0; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_int1: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_status1;
|
||||
uint32_t gpio_in0; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_in1: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_in1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t token0: 12;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t reserved13: 3;
|
||||
uint32_t reg_token1: 12;
|
||||
uint32_t rx_pf_eof: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_token_rdata;
|
||||
uint32_t slc0_pf; /**/
|
||||
uint32_t slc1_pf; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t gpio_sdio: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t wifi_rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t bt_rx_new_packet: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t gpio_sdio: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t wifi_rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t bt_rx_new_packet: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_slc0_len: 20;
|
||||
uint32_t reg_slc0_len_check:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} pkt_len;
|
||||
union {
|
||||
struct {
|
||||
uint32_t state0: 8;
|
||||
uint32_t state1: 8;
|
||||
uint32_t state2: 8;
|
||||
uint32_t state3: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} state_w0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t state4: 8;
|
||||
uint32_t state5: 8;
|
||||
uint32_t state6: 8;
|
||||
uint32_t state7: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} state_w1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf0: 8;
|
||||
uint32_t conf1: 8;
|
||||
uint32_t conf2: 8;
|
||||
uint32_t conf3: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf4: 8;
|
||||
uint32_t conf5: 8;
|
||||
uint32_t conf6: 8;
|
||||
uint32_t conf7: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf8: 8;
|
||||
uint32_t conf9: 8;
|
||||
uint32_t conf10: 8;
|
||||
uint32_t conf11: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf12: 8;
|
||||
uint32_t conf13: 8;
|
||||
uint32_t conf14: 8;
|
||||
uint32_t conf15: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf16: 8; /*SLC timeout value*/
|
||||
uint32_t conf17: 8; /*SLC timeout enable*/
|
||||
uint32_t conf18: 8;
|
||||
uint32_t conf19: 8; /*Interrupt to target CPU*/
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf20: 8;
|
||||
uint32_t conf21: 8;
|
||||
uint32_t conf22: 8;
|
||||
uint32_t conf23: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w5;
|
||||
uint32_t win_cmd; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf24: 8;
|
||||
uint32_t conf25: 8;
|
||||
uint32_t conf26: 8;
|
||||
uint32_t conf27: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w6;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf28: 8;
|
||||
uint32_t conf29: 8;
|
||||
uint32_t conf30: 8;
|
||||
uint32_t conf31: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w7;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_slc0_len0:20;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} pkt_len0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_slc0_len1:20;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} pkt_len1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_slc0_len2:20;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} pkt_len2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf32: 8;
|
||||
uint32_t conf33: 8;
|
||||
uint32_t conf34: 8;
|
||||
uint32_t conf35: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf36: 8;
|
||||
uint32_t conf37: 8;
|
||||
uint32_t conf38: 8;
|
||||
uint32_t conf39: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w9;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf40: 8;
|
||||
uint32_t conf41: 8;
|
||||
uint32_t conf42: 8;
|
||||
uint32_t conf43: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w10;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf44: 8;
|
||||
uint32_t conf45: 8;
|
||||
uint32_t conf46: 8;
|
||||
uint32_t conf47: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w11;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf48: 8;
|
||||
uint32_t conf49: 8;
|
||||
uint32_t conf50: 8;
|
||||
uint32_t conf51: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w12;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf52: 8;
|
||||
uint32_t conf53: 8;
|
||||
uint32_t conf54: 8;
|
||||
uint32_t conf55: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w13;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf56: 8;
|
||||
uint32_t conf57: 8;
|
||||
uint32_t conf58: 8;
|
||||
uint32_t conf59: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w14;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf60: 8;
|
||||
uint32_t conf61: 8;
|
||||
uint32_t conf62: 8;
|
||||
uint32_t conf63: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w15;
|
||||
uint32_t check_sum0; /**/
|
||||
uint32_t check_sum1; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t token0: 12;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t reserved13: 3;
|
||||
uint32_t reg_token1: 12;
|
||||
uint32_t rx_pf_eof: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_token_rdata;
|
||||
union {
|
||||
struct {
|
||||
uint32_t token0_wd: 12;
|
||||
uint32_t reserved12: 4;
|
||||
uint32_t token1_wd: 12;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_token_wdata;
|
||||
union {
|
||||
struct {
|
||||
uint32_t token0_wd: 12;
|
||||
uint32_t reserved12: 4;
|
||||
uint32_t token1_wd: 12;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_token_wdata;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_token0_dec: 1;
|
||||
uint32_t slc0_token1_dec: 1;
|
||||
uint32_t slc0_token0_wr: 1;
|
||||
uint32_t slc0_token1_wr: 1;
|
||||
uint32_t slc1_token0_dec: 1;
|
||||
uint32_t slc1_token1_dec: 1;
|
||||
uint32_t slc1_token0_wr: 1;
|
||||
uint32_t slc1_token1_wr: 1;
|
||||
uint32_t slc0_len_wr: 1;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} token_con;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t gpio_sdio: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t wifi_rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t bt_rx_new_packet: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t gpio_sdio: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_func1_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t wifi_rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t bt_rx_new_packet: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_func1_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t gpio_sdio: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_func2_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t wifi_rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t bt_rx_new_packet: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_func2_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t gpio_sdio: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t wifi_rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t bt_rx_new_packet: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infor: 20;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_rx_infor;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infor: 20;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_rx_infor;
|
||||
uint32_t slc0_len_wd; /**/
|
||||
uint32_t apbwin_wdata; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr: 28;
|
||||
uint32_t wr: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} apbwin_conf;
|
||||
uint32_t apbwin_rdata; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t bit7_clraddr: 9;
|
||||
uint32_t bit6_clraddr: 9;
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_rdclr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t bit7_clraddr: 9;
|
||||
uint32_t bit6_clraddr: 9;
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_rdclr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit01: 1;
|
||||
uint32_t tohost_bit11: 1;
|
||||
uint32_t tohost_bit21: 1;
|
||||
uint32_t tohost_bit31: 1;
|
||||
uint32_t tohost_bit41: 1;
|
||||
uint32_t tohost_bit51: 1;
|
||||
uint32_t tohost_bit61: 1;
|
||||
uint32_t tohost_bit71: 1;
|
||||
uint32_t token0_1to01: 1;
|
||||
uint32_t token1_1to01: 1;
|
||||
uint32_t token0_0to11: 1;
|
||||
uint32_t token1_0to11: 1;
|
||||
uint32_t rx_sof1: 1;
|
||||
uint32_t rx_eof1: 1;
|
||||
uint32_t rx_start1: 1;
|
||||
uint32_t tx_start1: 1;
|
||||
uint32_t rx_udf1: 1;
|
||||
uint32_t tx_ovf1: 1;
|
||||
uint32_t rx_pf_valid1: 1;
|
||||
uint32_t ext_bit01: 1;
|
||||
uint32_t ext_bit11: 1;
|
||||
uint32_t ext_bit21: 1;
|
||||
uint32_t ext_bit31: 1;
|
||||
uint32_t rx_new_packet1: 1;
|
||||
uint32_t rd_retry1: 1;
|
||||
uint32_t gpio_sdio1: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_ena1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit01: 1;
|
||||
uint32_t tohost_bit11: 1;
|
||||
uint32_t tohost_bit21: 1;
|
||||
uint32_t tohost_bit31: 1;
|
||||
uint32_t tohost_bit41: 1;
|
||||
uint32_t tohost_bit51: 1;
|
||||
uint32_t tohost_bit61: 1;
|
||||
uint32_t tohost_bit71: 1;
|
||||
uint32_t token0_1to01: 1;
|
||||
uint32_t token1_1to01: 1;
|
||||
uint32_t token0_0to11: 1;
|
||||
uint32_t token1_0to11: 1;
|
||||
uint32_t rx_sof1: 1;
|
||||
uint32_t rx_eof1: 1;
|
||||
uint32_t rx_start1: 1;
|
||||
uint32_t tx_start1: 1;
|
||||
uint32_t rx_udf1: 1;
|
||||
uint32_t tx_ovf1: 1;
|
||||
uint32_t rx_pf_valid1: 1;
|
||||
uint32_t ext_bit01: 1;
|
||||
uint32_t ext_bit11: 1;
|
||||
uint32_t ext_bit21: 1;
|
||||
uint32_t ext_bit31: 1;
|
||||
uint32_t wifi_rx_new_packet1: 1;
|
||||
uint32_t rd_retry1: 1;
|
||||
uint32_t bt_rx_new_packet1: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_int_ena1;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t date; /**/
|
||||
uint32_t id; /**/
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frc_sdio11: 5;
|
||||
uint32_t frc_sdio20: 5;
|
||||
uint32_t frc_neg_samp: 5;
|
||||
uint32_t frc_pos_samp: 5;
|
||||
uint32_t frc_quick_in: 5;
|
||||
uint32_t sdio20_int_delay: 1;
|
||||
uint32_t sdio_pad_pullup: 1;
|
||||
uint32_t hspeed_con_en: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio20_mode: 5;
|
||||
uint32_t sdio_neg_samp: 5;
|
||||
uint32_t sdio_quick_in: 5;
|
||||
uint32_t reserved15: 17;
|
||||
};
|
||||
uint32_t val;
|
||||
} inf_st;
|
||||
} host_dev_t;
|
||||
extern host_dev_t HOST;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_HOST_STRUCT_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,858 @@
|
|||
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_SLC_STRUCT_H_
|
||||
#define _SOC_SLC_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_tx_rst: 1;
|
||||
uint32_t slc0_rx_rst: 1;
|
||||
uint32_t ahbm_fifo_rst: 1;
|
||||
uint32_t ahbm_rst: 1;
|
||||
uint32_t slc0_tx_loop_test: 1;
|
||||
uint32_t slc0_rx_loop_test: 1;
|
||||
uint32_t slc0_rx_auto_wrback: 1;
|
||||
uint32_t slc0_rx_no_restart_clr: 1;
|
||||
uint32_t slc0_rxdscr_burst_en: 1;
|
||||
uint32_t slc0_rxdata_burst_en: 1;
|
||||
uint32_t slc0_rxlink_auto_ret: 1;
|
||||
uint32_t slc0_txlink_auto_ret: 1;
|
||||
uint32_t slc0_txdscr_burst_en: 1;
|
||||
uint32_t slc0_txdata_burst_en: 1;
|
||||
uint32_t slc0_token_auto_clr: 1;
|
||||
uint32_t slc0_token_sel: 1;
|
||||
uint32_t slc1_tx_rst: 1;
|
||||
uint32_t slc1_rx_rst: 1;
|
||||
uint32_t slc0_wr_retry_mask_en: 1;
|
||||
uint32_t slc1_wr_retry_mask_en: 1;
|
||||
uint32_t slc1_tx_loop_test: 1;
|
||||
uint32_t slc1_rx_loop_test: 1;
|
||||
uint32_t slc1_rx_auto_wrback: 1;
|
||||
uint32_t slc1_rx_no_restart_clr: 1;
|
||||
uint32_t slc1_rxdscr_burst_en: 1;
|
||||
uint32_t slc1_rxdata_burst_en: 1;
|
||||
uint32_t slc1_rxlink_auto_ret: 1;
|
||||
uint32_t slc1_txlink_auto_ret: 1;
|
||||
uint32_t slc1_txdscr_burst_en: 1;
|
||||
uint32_t slc1_txdata_burst_en: 1;
|
||||
uint32_t slc1_token_auto_clr: 1;
|
||||
uint32_t slc1_token_sel: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit0: 1;
|
||||
uint32_t frhost_bit1: 1;
|
||||
uint32_t frhost_bit2: 1;
|
||||
uint32_t frhost_bit3: 1;
|
||||
uint32_t frhost_bit4: 1;
|
||||
uint32_t frhost_bit5: 1;
|
||||
uint32_t frhost_bit6: 1;
|
||||
uint32_t frhost_bit7: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t tx_done: 1;
|
||||
uint32_t tx_suc_eof: 1;
|
||||
uint32_t rx_done: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t tohost: 1;
|
||||
uint32_t tx_dscr_err: 1;
|
||||
uint32_t rx_dscr_err: 1;
|
||||
uint32_t tx_dscr_empty: 1;
|
||||
uint32_t host_rd_ack: 1;
|
||||
uint32_t wr_retry_done: 1;
|
||||
uint32_t tx_err_eof: 1;
|
||||
uint32_t cmd_dtc: 1;
|
||||
uint32_t rx_quick_eof: 1;
|
||||
uint32_t reserved27: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit0: 1;
|
||||
uint32_t frhost_bit1: 1;
|
||||
uint32_t frhost_bit2: 1;
|
||||
uint32_t frhost_bit3: 1;
|
||||
uint32_t frhost_bit4: 1;
|
||||
uint32_t frhost_bit5: 1;
|
||||
uint32_t frhost_bit6: 1;
|
||||
uint32_t frhost_bit7: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t tx_done: 1;
|
||||
uint32_t tx_suc_eof: 1;
|
||||
uint32_t rx_done: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t tohost: 1;
|
||||
uint32_t tx_dscr_err: 1;
|
||||
uint32_t rx_dscr_err: 1;
|
||||
uint32_t tx_dscr_empty: 1;
|
||||
uint32_t host_rd_ack: 1;
|
||||
uint32_t wr_retry_done: 1;
|
||||
uint32_t tx_err_eof: 1;
|
||||
uint32_t cmd_dtc: 1;
|
||||
uint32_t rx_quick_eof: 1;
|
||||
uint32_t reserved27: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit0: 1;
|
||||
uint32_t frhost_bit1: 1;
|
||||
uint32_t frhost_bit2: 1;
|
||||
uint32_t frhost_bit3: 1;
|
||||
uint32_t frhost_bit4: 1;
|
||||
uint32_t frhost_bit5: 1;
|
||||
uint32_t frhost_bit6: 1;
|
||||
uint32_t frhost_bit7: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t tx_done: 1;
|
||||
uint32_t tx_suc_eof: 1;
|
||||
uint32_t rx_done: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t tohost: 1;
|
||||
uint32_t tx_dscr_err: 1;
|
||||
uint32_t rx_dscr_err: 1;
|
||||
uint32_t tx_dscr_empty: 1;
|
||||
uint32_t host_rd_ack: 1;
|
||||
uint32_t wr_retry_done: 1;
|
||||
uint32_t tx_err_eof: 1;
|
||||
uint32_t cmd_dtc: 1;
|
||||
uint32_t rx_quick_eof: 1;
|
||||
uint32_t reserved27: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit0: 1;
|
||||
uint32_t frhost_bit1: 1;
|
||||
uint32_t frhost_bit2: 1;
|
||||
uint32_t frhost_bit3: 1;
|
||||
uint32_t frhost_bit4: 1;
|
||||
uint32_t frhost_bit5: 1;
|
||||
uint32_t frhost_bit6: 1;
|
||||
uint32_t frhost_bit7: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t tx_done: 1;
|
||||
uint32_t tx_suc_eof: 1;
|
||||
uint32_t rx_done: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t tohost: 1;
|
||||
uint32_t tx_dscr_err: 1;
|
||||
uint32_t rx_dscr_err: 1;
|
||||
uint32_t tx_dscr_empty: 1;
|
||||
uint32_t host_rd_ack: 1;
|
||||
uint32_t wr_retry_done: 1;
|
||||
uint32_t tx_err_eof: 1;
|
||||
uint32_t cmd_dtc: 1;
|
||||
uint32_t rx_quick_eof: 1;
|
||||
uint32_t reserved27: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit8: 1;
|
||||
uint32_t frhost_bit9: 1;
|
||||
uint32_t frhost_bit10: 1;
|
||||
uint32_t frhost_bit11: 1;
|
||||
uint32_t frhost_bit12: 1;
|
||||
uint32_t frhost_bit13: 1;
|
||||
uint32_t frhost_bit14: 1;
|
||||
uint32_t frhost_bit15: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t tx_done: 1;
|
||||
uint32_t tx_suc_eof: 1;
|
||||
uint32_t rx_done: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t tohost: 1;
|
||||
uint32_t tx_dscr_err: 1;
|
||||
uint32_t rx_dscr_err: 1;
|
||||
uint32_t tx_dscr_empty: 1;
|
||||
uint32_t host_rd_ack: 1;
|
||||
uint32_t wr_retry_done: 1;
|
||||
uint32_t tx_err_eof: 1;
|
||||
uint32_t reserved25: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit8: 1;
|
||||
uint32_t frhost_bit9: 1;
|
||||
uint32_t frhost_bit10: 1;
|
||||
uint32_t frhost_bit11: 1;
|
||||
uint32_t frhost_bit12: 1;
|
||||
uint32_t frhost_bit13: 1;
|
||||
uint32_t frhost_bit14: 1;
|
||||
uint32_t frhost_bit15: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t tx_done: 1;
|
||||
uint32_t tx_suc_eof: 1;
|
||||
uint32_t rx_done: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t tohost: 1;
|
||||
uint32_t tx_dscr_err: 1;
|
||||
uint32_t rx_dscr_err: 1;
|
||||
uint32_t tx_dscr_empty: 1;
|
||||
uint32_t host_rd_ack: 1;
|
||||
uint32_t wr_retry_done: 1;
|
||||
uint32_t tx_err_eof: 1;
|
||||
uint32_t reserved25: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit8: 1;
|
||||
uint32_t frhost_bit9: 1;
|
||||
uint32_t frhost_bit10: 1;
|
||||
uint32_t frhost_bit11: 1;
|
||||
uint32_t frhost_bit12: 1;
|
||||
uint32_t frhost_bit13: 1;
|
||||
uint32_t frhost_bit14: 1;
|
||||
uint32_t frhost_bit15: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t tx_done: 1;
|
||||
uint32_t tx_suc_eof: 1;
|
||||
uint32_t rx_done: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t tohost: 1;
|
||||
uint32_t tx_dscr_err: 1;
|
||||
uint32_t rx_dscr_err: 1;
|
||||
uint32_t tx_dscr_empty: 1;
|
||||
uint32_t host_rd_ack: 1;
|
||||
uint32_t wr_retry_done: 1;
|
||||
uint32_t tx_err_eof: 1;
|
||||
uint32_t reserved25: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit8: 1;
|
||||
uint32_t frhost_bit9: 1;
|
||||
uint32_t frhost_bit10: 1;
|
||||
uint32_t frhost_bit11: 1;
|
||||
uint32_t frhost_bit12: 1;
|
||||
uint32_t frhost_bit13: 1;
|
||||
uint32_t frhost_bit14: 1;
|
||||
uint32_t frhost_bit15: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t tx_done: 1;
|
||||
uint32_t tx_suc_eof: 1;
|
||||
uint32_t rx_done: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t tohost: 1;
|
||||
uint32_t tx_dscr_err: 1;
|
||||
uint32_t rx_dscr_err: 1;
|
||||
uint32_t tx_dscr_empty: 1;
|
||||
uint32_t host_rd_ack: 1;
|
||||
uint32_t wr_retry_done: 1;
|
||||
uint32_t tx_err_eof: 1;
|
||||
uint32_t reserved25: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_rx_full: 1;
|
||||
uint32_t slc0_rx_empty: 1;
|
||||
uint32_t reserved2: 14;
|
||||
uint32_t slc1_rx_full: 1;
|
||||
uint32_t slc1_rx_empty: 1;
|
||||
uint32_t reserved18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxfifo_wdata: 9;
|
||||
uint32_t reserved9: 7;
|
||||
uint32_t rxfifo_push: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_rxfifo_push;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxfifo_wdata: 9;
|
||||
uint32_t reserved9: 7;
|
||||
uint32_t rxfifo_push: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_rxfifo_push;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_tx_full: 1;
|
||||
uint32_t slc0_tx_empty: 1;
|
||||
uint32_t reserved2: 14;
|
||||
uint32_t slc1_tx_full: 1;
|
||||
uint32_t slc1_tx_empty: 1;
|
||||
uint32_t reserved18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t txfifo_rdata: 11;
|
||||
uint32_t reserved11: 5;
|
||||
uint32_t txfifo_pop: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_txfifo_pop;
|
||||
union {
|
||||
struct {
|
||||
uint32_t txfifo_rdata: 11;
|
||||
uint32_t reserved11: 5;
|
||||
uint32_t txfifo_pop: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_txfifo_pop;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr: 20;
|
||||
uint32_t reserved20: 8;
|
||||
uint32_t stop: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t restart: 1;
|
||||
uint32_t park: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_rx_link;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr: 20;
|
||||
uint32_t reserved20: 8;
|
||||
uint32_t stop: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t restart: 1;
|
||||
uint32_t park: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_tx_link;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr: 20;
|
||||
uint32_t bt_packet: 1;
|
||||
uint32_t reserved21: 7;
|
||||
uint32_t stop: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t restart: 1;
|
||||
uint32_t park: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_rx_link;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr: 20;
|
||||
uint32_t reserved20: 8;
|
||||
uint32_t stop: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t restart: 1;
|
||||
uint32_t park: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_tx_link;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_intvec: 8;
|
||||
uint32_t reserved8: 8;
|
||||
uint32_t slc1_intvec: 8;
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} intvec_tohost;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wdata: 12;
|
||||
uint32_t wr: 1;
|
||||
uint32_t inc: 1;
|
||||
uint32_t inc_more: 1;
|
||||
uint32_t reserved15: 1;
|
||||
uint32_t token0: 12;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_token0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wdata: 12;
|
||||
uint32_t wr: 1;
|
||||
uint32_t inc: 1;
|
||||
uint32_t inc_more: 1;
|
||||
uint32_t reserved15: 1;
|
||||
uint32_t token1: 12;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_token1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wdata: 12;
|
||||
uint32_t wr: 1;
|
||||
uint32_t inc: 1;
|
||||
uint32_t inc_more: 1;
|
||||
uint32_t reserved15: 1;
|
||||
uint32_t token0: 12;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_token0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wdata: 12;
|
||||
uint32_t wr: 1;
|
||||
uint32_t inc: 1;
|
||||
uint32_t inc_more: 1;
|
||||
uint32_t reserved15: 1;
|
||||
uint32_t token1: 12;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_token1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_check_owner: 1;
|
||||
uint32_t slc0_tx_check_sum_en: 1;
|
||||
uint32_t slc0_rx_check_sum_en: 1;
|
||||
uint32_t cmd_hold_en: 1;
|
||||
uint32_t slc0_len_auto_clr: 1;
|
||||
uint32_t slc0_tx_stitch_en: 1;
|
||||
uint32_t slc0_rx_stitch_en: 1;
|
||||
uint32_t reserved7: 9;
|
||||
uint32_t slc1_check_owner: 1;
|
||||
uint32_t slc1_tx_check_sum_en: 1;
|
||||
uint32_t slc1_rx_check_sum_en: 1;
|
||||
uint32_t host_int_level_sel: 1;
|
||||
uint32_t slc1_tx_stitch_en: 1;
|
||||
uint32_t slc1_rx_stitch_en: 1;
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t reserved23: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf1;
|
||||
uint32_t slc0_state0; /**/
|
||||
uint32_t slc0_state1; /**/
|
||||
uint32_t slc1_state0; /**/
|
||||
uint32_t slc1_state1; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t txeof_ena: 6;
|
||||
uint32_t reserved6: 2;
|
||||
uint32_t fifo_map_ena: 4;
|
||||
uint32_t slc0_tx_dummy_mode: 1;
|
||||
uint32_t hda_map_128k: 1;
|
||||
uint32_t slc1_tx_dummy_mode: 1;
|
||||
uint32_t reserved15: 1;
|
||||
uint32_t tx_push_idle_num:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} bridge_conf;
|
||||
uint32_t slc0_to_eof_des_addr; /**/
|
||||
uint32_t slc0_tx_eof_des_addr; /**/
|
||||
uint32_t slc0_to_eof_bfr_des_addr; /**/
|
||||
uint32_t slc1_to_eof_des_addr; /**/
|
||||
uint32_t slc1_tx_eof_des_addr; /**/
|
||||
uint32_t slc1_to_eof_bfr_des_addr; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t mode: 3;
|
||||
uint32_t reserved3: 1;
|
||||
uint32_t addr: 2;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} ahb_test;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cmd_st: 3;
|
||||
uint32_t reserved3: 1;
|
||||
uint32_t func_st: 4;
|
||||
uint32_t sdio_wakeup: 1;
|
||||
uint32_t reserved9: 3;
|
||||
uint32_t bus_st: 3;
|
||||
uint32_t reserved15: 1;
|
||||
uint32_t func1_acc_state: 5;
|
||||
uint32_t reserved21: 3;
|
||||
uint32_t func2_acc_state: 5;
|
||||
uint32_t reserved29: 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_token_no_replace: 1;
|
||||
uint32_t slc0_infor_no_replace: 1;
|
||||
uint32_t slc0_rx_fill_mode: 1;
|
||||
uint32_t slc0_rx_eof_mode: 1;
|
||||
uint32_t slc0_rx_fill_en: 1;
|
||||
uint32_t slc0_rd_retry_threshold:11;
|
||||
uint32_t slc1_token_no_replace: 1;
|
||||
uint32_t slc1_infor_no_replace: 1;
|
||||
uint32_t slc1_rx_fill_mode: 1;
|
||||
uint32_t slc1_rx_eof_mode: 1;
|
||||
uint32_t slc1_rx_fill_en: 1;
|
||||
uint32_t slc1_rd_retry_threshold:11;
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_dscr_conf;
|
||||
uint32_t slc0_txlink_dscr; /**/
|
||||
uint32_t slc0_txlink_dscr_bf0; /**/
|
||||
uint32_t slc0_txlink_dscr_bf1; /**/
|
||||
uint32_t slc0_rxlink_dscr; /**/
|
||||
uint32_t slc0_rxlink_dscr_bf0; /**/
|
||||
uint32_t slc0_rxlink_dscr_bf1; /**/
|
||||
uint32_t slc1_txlink_dscr; /**/
|
||||
uint32_t slc1_txlink_dscr_bf0; /**/
|
||||
uint32_t slc1_txlink_dscr_bf1; /**/
|
||||
uint32_t slc1_rxlink_dscr; /**/
|
||||
uint32_t slc1_rxlink_dscr_bf0; /**/
|
||||
uint32_t slc1_rxlink_dscr_bf1; /**/
|
||||
uint32_t slc0_tx_erreof_des_addr; /**/
|
||||
uint32_t slc1_tx_erreof_des_addr; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_token:12;
|
||||
uint32_t reserved12: 4;
|
||||
uint32_t slc1_token:12;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} token_lat;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wr_retry_threshold:11;
|
||||
uint32_t reserved11: 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_dscr_conf;
|
||||
uint32_t cmd_infor0; /**/
|
||||
uint32_t cmd_infor1; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t len_wdata: 20;
|
||||
uint32_t len_wr: 1;
|
||||
uint32_t len_inc: 1;
|
||||
uint32_t len_inc_more: 1;
|
||||
uint32_t rx_packet_load_en: 1;
|
||||
uint32_t tx_packet_load_en: 1;
|
||||
uint32_t rx_get_used_dscr: 1;
|
||||
uint32_t tx_get_used_dscr: 1;
|
||||
uint32_t rx_new_pkt_ind: 1;
|
||||
uint32_t tx_new_pkt_ind: 1;
|
||||
uint32_t reserved29: 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_len_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t len: 20;
|
||||
uint32_t reserved20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_length;
|
||||
uint32_t slc0_txpkt_h_dscr; /**/
|
||||
uint32_t slc0_txpkt_e_dscr; /**/
|
||||
uint32_t slc0_rxpkt_h_dscr; /**/
|
||||
uint32_t slc0_rxpkt_e_dscr; /**/
|
||||
uint32_t slc0_txpktu_h_dscr; /**/
|
||||
uint32_t slc0_txpktu_e_dscr; /**/
|
||||
uint32_t slc0_rxpktu_h_dscr; /**/
|
||||
uint32_t slc0_rxpktu_e_dscr; /**/
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_position: 8;
|
||||
uint32_t slc1_position: 8;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} seq_position;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_dscr_rec_lim: 10;
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_dscr_rec_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dat0_crc_err_cnt: 8;
|
||||
uint32_t dat1_crc_err_cnt: 8;
|
||||
uint32_t dat2_crc_err_cnt: 8;
|
||||
uint32_t dat3_crc_err_cnt: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_crc_st0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cmd_crc_err_cnt: 8;
|
||||
uint32_t reserved8: 23;
|
||||
uint32_t err_cnt_clr: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_crc_st1;
|
||||
uint32_t slc0_eof_start_des; /**/
|
||||
uint32_t slc0_push_dscr_addr; /**/
|
||||
uint32_t slc0_done_dscr_addr; /**/
|
||||
uint32_t slc0_sub_start_des; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_dscr_cnt_lat: 10;
|
||||
uint32_t reserved10: 6;
|
||||
uint32_t rx_get_eof_occ: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_dscr_cnt;
|
||||
union {
|
||||
struct {
|
||||
uint32_t len_lim: 20;
|
||||
uint32_t reserved20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_len_lim_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit01: 1;
|
||||
uint32_t frhost_bit11: 1;
|
||||
uint32_t frhost_bit21: 1;
|
||||
uint32_t frhost_bit31: 1;
|
||||
uint32_t frhost_bit41: 1;
|
||||
uint32_t frhost_bit51: 1;
|
||||
uint32_t frhost_bit61: 1;
|
||||
uint32_t frhost_bit71: 1;
|
||||
uint32_t rx_start1: 1;
|
||||
uint32_t tx_start1: 1;
|
||||
uint32_t rx_udf1: 1;
|
||||
uint32_t tx_ovf1: 1;
|
||||
uint32_t token0_1to01: 1;
|
||||
uint32_t token1_1to01: 1;
|
||||
uint32_t tx_done1: 1;
|
||||
uint32_t tx_suc_eof1: 1;
|
||||
uint32_t rx_done1: 1;
|
||||
uint32_t rx_eof1: 1;
|
||||
uint32_t tohost1: 1;
|
||||
uint32_t tx_dscr_err1: 1;
|
||||
uint32_t rx_dscr_err1: 1;
|
||||
uint32_t tx_dscr_empty1: 1;
|
||||
uint32_t host_rd_ack1: 1;
|
||||
uint32_t wr_retry_done1: 1;
|
||||
uint32_t tx_err_eof1: 1;
|
||||
uint32_t cmd_dtc1: 1;
|
||||
uint32_t rx_quick_eof1: 1;
|
||||
uint32_t reserved27: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_st1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit01: 1;
|
||||
uint32_t frhost_bit11: 1;
|
||||
uint32_t frhost_bit21: 1;
|
||||
uint32_t frhost_bit31: 1;
|
||||
uint32_t frhost_bit41: 1;
|
||||
uint32_t frhost_bit51: 1;
|
||||
uint32_t frhost_bit61: 1;
|
||||
uint32_t frhost_bit71: 1;
|
||||
uint32_t rx_start1: 1;
|
||||
uint32_t tx_start1: 1;
|
||||
uint32_t rx_udf1: 1;
|
||||
uint32_t tx_ovf1: 1;
|
||||
uint32_t token0_1to01: 1;
|
||||
uint32_t token1_1to01: 1;
|
||||
uint32_t tx_done1: 1;
|
||||
uint32_t tx_suc_eof1: 1;
|
||||
uint32_t rx_done1: 1;
|
||||
uint32_t rx_eof1: 1;
|
||||
uint32_t tohost1: 1;
|
||||
uint32_t tx_dscr_err1: 1;
|
||||
uint32_t rx_dscr_err1: 1;
|
||||
uint32_t tx_dscr_empty1: 1;
|
||||
uint32_t host_rd_ack1: 1;
|
||||
uint32_t wr_retry_done1: 1;
|
||||
uint32_t tx_err_eof1: 1;
|
||||
uint32_t cmd_dtc1: 1;
|
||||
uint32_t rx_quick_eof1: 1;
|
||||
uint32_t reserved27: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_ena1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit81: 1;
|
||||
uint32_t frhost_bit91: 1;
|
||||
uint32_t frhost_bit101: 1;
|
||||
uint32_t frhost_bit111: 1;
|
||||
uint32_t frhost_bit121: 1;
|
||||
uint32_t frhost_bit131: 1;
|
||||
uint32_t frhost_bit141: 1;
|
||||
uint32_t frhost_bit151: 1;
|
||||
uint32_t rx_start1: 1;
|
||||
uint32_t tx_start1: 1;
|
||||
uint32_t rx_udf1: 1;
|
||||
uint32_t tx_ovf1: 1;
|
||||
uint32_t token0_1to01: 1;
|
||||
uint32_t token1_1to01: 1;
|
||||
uint32_t tx_done1: 1;
|
||||
uint32_t tx_suc_eof1: 1;
|
||||
uint32_t rx_done1: 1;
|
||||
uint32_t rx_eof1: 1;
|
||||
uint32_t tohost1: 1;
|
||||
uint32_t tx_dscr_err1: 1;
|
||||
uint32_t rx_dscr_err1: 1;
|
||||
uint32_t tx_dscr_empty1: 1;
|
||||
uint32_t host_rd_ack1: 1;
|
||||
uint32_t wr_retry_done1: 1;
|
||||
uint32_t tx_err_eof1: 1;
|
||||
uint32_t reserved25: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_int_st1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit81: 1;
|
||||
uint32_t frhost_bit91: 1;
|
||||
uint32_t frhost_bit101: 1;
|
||||
uint32_t frhost_bit111: 1;
|
||||
uint32_t frhost_bit121: 1;
|
||||
uint32_t frhost_bit131: 1;
|
||||
uint32_t frhost_bit141: 1;
|
||||
uint32_t frhost_bit151: 1;
|
||||
uint32_t rx_start1: 1;
|
||||
uint32_t tx_start1: 1;
|
||||
uint32_t rx_udf1: 1;
|
||||
uint32_t tx_ovf1: 1;
|
||||
uint32_t token0_1to01: 1;
|
||||
uint32_t token1_1to01: 1;
|
||||
uint32_t tx_done1: 1;
|
||||
uint32_t tx_suc_eof1: 1;
|
||||
uint32_t rx_done1: 1;
|
||||
uint32_t rx_eof1: 1;
|
||||
uint32_t tohost1: 1;
|
||||
uint32_t tx_dscr_err1: 1;
|
||||
uint32_t rx_dscr_err1: 1;
|
||||
uint32_t tx_dscr_empty1: 1;
|
||||
uint32_t host_rd_ack1: 1;
|
||||
uint32_t wr_retry_done1: 1;
|
||||
uint32_t tx_err_eof1: 1;
|
||||
uint32_t reserved25: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc1_int_ena1;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t date; /**/
|
||||
uint32_t id; /**/
|
||||
} slc_dev_t;
|
||||
extern slc_dev_t SLC;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_SLC_STRUCT_H_ */
|
||||
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Reference in New Issue